atomic.cc revision 3119 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
42    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
43{
44}
45
46
47void
48AtomicSimpleCPU::TickEvent::process()
49{
50    cpu->tick();
51}
52
53const char *
54AtomicSimpleCPU::TickEvent::description()
55{
56    return "AtomicSimpleCPU tick event";
57}
58
59Port *
60AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
61{
62    if (if_name == "dcache_port")
63        return &dcachePort;
64    else if (if_name == "icache_port")
65        return &icachePort;
66    else
67        panic("No Such Port\n");
68}
69
70void
71AtomicSimpleCPU::init()
72{
73    //Create Memory Ports (conect them up)
74//    Port *mem_dport = mem->getPort("");
75//    dcachePort.setPeer(mem_dport);
76//    mem_dport->setPeer(&dcachePort);
77
78//    Port *mem_iport = mem->getPort("");
79//    icachePort.setPeer(mem_iport);
80//    mem_iport->setPeer(&icachePort);
81
82    BaseCPU::init();
83#if FULL_SYSTEM
84    for (int i = 0; i < threadContexts.size(); ++i) {
85        ThreadContext *tc = threadContexts[i];
86
87        // initialize CPU, including PC
88        TheISA::initCPU(tc, tc->readCpuId());
89    }
90#endif
91}
92
93bool
94AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
95{
96    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
97    return true;
98}
99
100Tick
101AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
102{
103    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
104    return curTick;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
109{
110    panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
111}
112
113void
114AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
115{
116    if (status == RangeChange)
117        return;
118
119    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
120}
121
122void
123AtomicSimpleCPU::CpuPort::recvRetry()
124{
125    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
126}
127
128
129AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
130    : BaseSimpleCPU(p), tickEvent(this),
131      width(p->width), simulate_stalls(p->simulate_stalls),
132      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
133{
134    _status = Idle;
135
136    // @todo fix me and get the real cpu id & thread number!!!
137    ifetch_req = new Request();
138    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
139    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
140    ifetch_pkt->dataStatic(&inst);
141
142    data_read_req = new Request();
143    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
144    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
145                               Packet::Broadcast);
146    data_read_pkt->dataStatic(&dataReg);
147
148    data_write_req = new Request();
149    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
150    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
151                                Packet::Broadcast);
152}
153
154
155AtomicSimpleCPU::~AtomicSimpleCPU()
156{
157}
158
159void
160AtomicSimpleCPU::serialize(ostream &os)
161{
162    SimObject::State so_state = SimObject::getState();
163    SERIALIZE_ENUM(so_state);
164    nameOut(os, csprintf("%s.tickEvent", name()));
165    tickEvent.serialize(os);
166    BaseSimpleCPU::serialize(os);
167}
168
169void
170AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
171{
172    SimObject::State so_state;
173    UNSERIALIZE_ENUM(so_state);
174    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
175    BaseSimpleCPU::unserialize(cp, section);
176}
177
178void
179AtomicSimpleCPU::resume()
180{
181    assert(system->getMemoryMode() == System::Atomic);
182    changeState(SimObject::Running);
183    if (thread->status() == ThreadContext::Active) {
184        if (!tickEvent.scheduled())
185            tickEvent.schedule(curTick);
186    }
187}
188
189void
190AtomicSimpleCPU::switchOut()
191{
192    assert(status() == Running || status() == Idle);
193    _status = SwitchedOut;
194
195    tickEvent.squash();
196}
197
198
199void
200AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
201{
202    BaseCPU::takeOverFrom(oldCPU);
203
204    assert(!tickEvent.scheduled());
205
206    // if any of this CPU's ThreadContexts are active, mark the CPU as
207    // running and schedule its tick event.
208    for (int i = 0; i < threadContexts.size(); ++i) {
209        ThreadContext *tc = threadContexts[i];
210        if (tc->status() == ThreadContext::Active && _status != Running) {
211            _status = Running;
212            tickEvent.schedule(curTick);
213            break;
214        }
215    }
216}
217
218
219void
220AtomicSimpleCPU::activateContext(int thread_num, int delay)
221{
222    assert(thread_num == 0);
223    assert(thread);
224
225    assert(_status == Idle);
226    assert(!tickEvent.scheduled());
227
228    notIdleFraction++;
229    tickEvent.schedule(curTick + cycles(delay));
230    _status = Running;
231}
232
233
234void
235AtomicSimpleCPU::suspendContext(int thread_num)
236{
237    assert(thread_num == 0);
238    assert(thread);
239
240    assert(_status == Running);
241
242    // tick event may not be scheduled if this gets called from inside
243    // an instruction's execution, e.g. "quiesce"
244    if (tickEvent.scheduled())
245        tickEvent.deschedule();
246
247    notIdleFraction--;
248    _status = Idle;
249}
250
251
252template <class T>
253Fault
254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
255{
256    data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
257
258    if (traceData) {
259        traceData->setAddr(addr);
260    }
261
262    // translate to physical address
263    Fault fault = thread->translateDataReadReq(data_read_req);
264
265    // Now do the access.
266    if (fault == NoFault) {
267        data_read_pkt->reinitFromRequest();
268
269        dcache_latency = dcachePort.sendAtomic(data_read_pkt);
270        dcache_access = true;
271
272        assert(data_read_pkt->result == Packet::Success);
273        data = data_read_pkt->get<T>();
274
275    }
276
277    // This will need a new way to tell if it has a dcache attached.
278    if (data_read_req->getFlags() & UNCACHEABLE)
279        recordEvent("Uncached Read");
280
281    return fault;
282}
283
284#ifndef DOXYGEN_SHOULD_SKIP_THIS
285
286template
287Fault
288AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
289
290template
291Fault
292AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
293
294template
295Fault
296AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
297
298template
299Fault
300AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
301
302#endif //DOXYGEN_SHOULD_SKIP_THIS
303
304template<>
305Fault
306AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
307{
308    return read(addr, *(uint64_t*)&data, flags);
309}
310
311template<>
312Fault
313AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
314{
315    return read(addr, *(uint32_t*)&data, flags);
316}
317
318
319template<>
320Fault
321AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
322{
323    return read(addr, (uint32_t&)data, flags);
324}
325
326
327template <class T>
328Fault
329AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
330{
331    data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
332
333    if (traceData) {
334        traceData->setAddr(addr);
335    }
336
337    // translate to physical address
338    Fault fault = thread->translateDataWriteReq(data_write_req);
339
340    // Now do the access.
341    if (fault == NoFault) {
342        data = htog(data);
343        data_write_pkt->reinitFromRequest();
344        data_write_pkt->dataStatic(&data);
345
346        dcache_latency = dcachePort.sendAtomic(data_write_pkt);
347        dcache_access = true;
348
349        assert(data_write_pkt->result == Packet::Success);
350
351        if (res && data_write_req->getFlags() & LOCKED) {
352            *res = data_write_req->getScResult();
353        }
354    }
355
356    // This will need a new way to tell if it's hooked up to a cache or not.
357    if (data_write_req->getFlags() & UNCACHEABLE)
358        recordEvent("Uncached Write");
359
360    // If the write needs to have a fault on the access, consider calling
361    // changeStatus() and changing it to "bad addr write" or something.
362    return fault;
363}
364
365
366#ifndef DOXYGEN_SHOULD_SKIP_THIS
367template
368Fault
369AtomicSimpleCPU::write(uint64_t data, Addr addr,
370                       unsigned flags, uint64_t *res);
371
372template
373Fault
374AtomicSimpleCPU::write(uint32_t data, Addr addr,
375                       unsigned flags, uint64_t *res);
376
377template
378Fault
379AtomicSimpleCPU::write(uint16_t data, Addr addr,
380                       unsigned flags, uint64_t *res);
381
382template
383Fault
384AtomicSimpleCPU::write(uint8_t data, Addr addr,
385                       unsigned flags, uint64_t *res);
386
387#endif //DOXYGEN_SHOULD_SKIP_THIS
388
389template<>
390Fault
391AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
392{
393    return write(*(uint64_t*)&data, addr, flags, res);
394}
395
396template<>
397Fault
398AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
399{
400    return write(*(uint32_t*)&data, addr, flags, res);
401}
402
403
404template<>
405Fault
406AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
407{
408    return write((uint32_t)data, addr, flags, res);
409}
410
411
412void
413AtomicSimpleCPU::tick()
414{
415    Tick latency = cycles(1); // instruction takes one cycle by default
416
417    for (int i = 0; i < width; ++i) {
418        numCycles++;
419
420        checkForInterrupts();
421
422        Fault fault = setupFetchRequest(ifetch_req);
423
424        if (fault == NoFault) {
425            ifetch_pkt->reinitFromRequest();
426
427            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
428            // ifetch_req is initialized to read the instruction directly
429            // into the CPU object's inst field.
430
431            dcache_access = false; // assume no dcache access
432            preExecute();
433            fault = curStaticInst->execute(this, traceData);
434            postExecute();
435
436            if (simulate_stalls) {
437                Tick icache_stall = icache_latency - cycles(1);
438                Tick dcache_stall =
439                    dcache_access ? dcache_latency - cycles(1) : 0;
440                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
441                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
442                    latency += cycles(stall_cycles+1);
443                else
444                    latency += cycles(stall_cycles);
445            }
446
447        }
448
449        advancePC(fault);
450    }
451
452    if (_status != Idle)
453        tickEvent.schedule(curTick + latency);
454}
455
456
457////////////////////////////////////////////////////////////////////////
458//
459//  AtomicSimpleCPU Simulation Object
460//
461BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
462
463    Param<Counter> max_insts_any_thread;
464    Param<Counter> max_insts_all_threads;
465    Param<Counter> max_loads_any_thread;
466    Param<Counter> max_loads_all_threads;
467    Param<Tick> progress_interval;
468    SimObjectParam<MemObject *> mem;
469    SimObjectParam<System *> system;
470
471#if FULL_SYSTEM
472    SimObjectParam<AlphaITB *> itb;
473    SimObjectParam<AlphaDTB *> dtb;
474    Param<int> cpu_id;
475    Param<Tick> profile;
476#else
477    SimObjectParam<Process *> workload;
478#endif // FULL_SYSTEM
479
480    Param<int> clock;
481
482    Param<bool> defer_registration;
483    Param<int> width;
484    Param<bool> function_trace;
485    Param<Tick> function_trace_start;
486    Param<bool> simulate_stalls;
487
488END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
489
490BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
491
492    INIT_PARAM(max_insts_any_thread,
493               "terminate when any thread reaches this inst count"),
494    INIT_PARAM(max_insts_all_threads,
495               "terminate when all threads have reached this inst count"),
496    INIT_PARAM(max_loads_any_thread,
497               "terminate when any thread reaches this load count"),
498    INIT_PARAM(max_loads_all_threads,
499               "terminate when all threads have reached this load count"),
500    INIT_PARAM(progress_interval, "Progress interval"),
501    INIT_PARAM(mem, "memory"),
502    INIT_PARAM(system, "system object"),
503
504#if FULL_SYSTEM
505    INIT_PARAM(itb, "Instruction TLB"),
506    INIT_PARAM(dtb, "Data TLB"),
507    INIT_PARAM(cpu_id, "processor ID"),
508    INIT_PARAM(profile, ""),
509#else
510    INIT_PARAM(workload, "processes to run"),
511#endif // FULL_SYSTEM
512
513    INIT_PARAM(clock, "clock speed"),
514    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
515    INIT_PARAM(width, "cpu width"),
516    INIT_PARAM(function_trace, "Enable function trace"),
517    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
518    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
519
520END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
521
522
523CREATE_SIM_OBJECT(AtomicSimpleCPU)
524{
525    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
526    params->name = getInstanceName();
527    params->numberOfThreads = 1;
528    params->max_insts_any_thread = max_insts_any_thread;
529    params->max_insts_all_threads = max_insts_all_threads;
530    params->max_loads_any_thread = max_loads_any_thread;
531    params->max_loads_all_threads = max_loads_all_threads;
532    params->progress_interval = progress_interval;
533    params->deferRegistration = defer_registration;
534    params->clock = clock;
535    params->functionTrace = function_trace;
536    params->functionTraceStart = function_trace_start;
537    params->width = width;
538    params->simulate_stalls = simulate_stalls;
539    params->mem = mem;
540    params->system = system;
541
542#if FULL_SYSTEM
543    params->itb = itb;
544    params->dtb = dtb;
545    params->cpu_id = cpu_id;
546    params->profile = profile;
547#else
548    params->process = workload;
549#endif
550
551    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
552    return cpu;
553}
554
555REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
556
557