atomic.cc revision 2915
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/atomic.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" 36 37using namespace std; 38using namespace TheISA; 39 40AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 41 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 42{ 43} 44 45 46void 47AtomicSimpleCPU::TickEvent::process() 48{ 49 cpu->tick(); 50} 51 52const char * 53AtomicSimpleCPU::TickEvent::description() 54{ 55 return "AtomicSimpleCPU tick event"; 56} 57 58Port * 59AtomicSimpleCPU::getPort(const std::string &if_name, int idx) 60{ 61 if (if_name == "dcache_port") 62 return &dcachePort; 63 else if (if_name == "icache_port") 64 return &icachePort; 65 else 66 panic("No Such Port\n"); 67} 68 69void 70AtomicSimpleCPU::init() 71{ 72 //Create Memory Ports (conect them up) 73// Port *mem_dport = mem->getPort(""); 74// dcachePort.setPeer(mem_dport); 75// mem_dport->setPeer(&dcachePort); 76 77// Port *mem_iport = mem->getPort(""); 78// icachePort.setPeer(mem_iport); 79// mem_iport->setPeer(&icachePort); 80 81 BaseCPU::init(); 82#if FULL_SYSTEM 83 for (int i = 0; i < threadContexts.size(); ++i) { 84 ThreadContext *tc = threadContexts[i]; 85 86 // initialize CPU, including PC 87 TheISA::initCPU(tc, tc->readCpuId()); 88 } 89#endif 90} 91 92bool 93AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 94{ 95 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 96 return true; 97} 98 99Tick 100AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 101{ 102 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 103 return curTick; 104} 105 106void 107AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 108{ 109 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 110} 111 112void 113AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 114{ 115 if (status == RangeChange) 116 return; 117 118 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 119} 120 121void 122AtomicSimpleCPU::CpuPort::recvRetry() 123{ 124 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 125} 126 127 128AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 129 : BaseSimpleCPU(p), tickEvent(this), 130 width(p->width), simulate_stalls(p->simulate_stalls), 131 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 132{ 133 _status = Idle; 134 135 // @todo fix me and get the real cpu id & thread number!!! 136 ifetch_req = new Request(); 137 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 138 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 139 ifetch_pkt->dataStatic(&inst); 140 141 data_read_req = new Request(); 142 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 143 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 144 Packet::Broadcast); 145 data_read_pkt->dataStatic(&dataReg); 146 147 data_write_req = new Request(); 148 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE 149 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 150 Packet::Broadcast); 151} 152 153 154AtomicSimpleCPU::~AtomicSimpleCPU() 155{ 156} 157 158void 159AtomicSimpleCPU::serialize(ostream &os) 160{ 161 SimObject::State so_state = SimObject::getState(); 162 SERIALIZE_ENUM(so_state); 163 nameOut(os, csprintf("%s.tickEvent", name())); 164 tickEvent.serialize(os); 165 BaseSimpleCPU::serialize(os); 166} 167 168void 169AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 170{ 171 SimObject::State so_state; 172 UNSERIALIZE_ENUM(so_state); 173 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 174 BaseSimpleCPU::unserialize(cp, section); 175} 176 177void 178AtomicSimpleCPU::resume() 179{ 180 if (thread->status() == ThreadContext::Active) { 181 if (!tickEvent.scheduled()) 182 tickEvent.schedule(curTick); 183 } 184} 185 186void 187AtomicSimpleCPU::switchOut() 188{ 189 assert(status() == Running || status() == Idle); 190 _status = SwitchedOut; 191 192 tickEvent.squash(); 193} 194 195 196void 197AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 198{ 199 BaseCPU::takeOverFrom(oldCPU); 200 201 assert(!tickEvent.scheduled()); 202 203 // if any of this CPU's ThreadContexts are active, mark the CPU as 204 // running and schedule its tick event. 205 for (int i = 0; i < threadContexts.size(); ++i) { 206 ThreadContext *tc = threadContexts[i]; 207 if (tc->status() == ThreadContext::Active && _status != Running) { 208 _status = Running; 209 tickEvent.schedule(curTick); 210 break; 211 } 212 } 213} 214 215 216void 217AtomicSimpleCPU::activateContext(int thread_num, int delay) 218{ 219 assert(thread_num == 0); 220 assert(thread); 221 222 assert(_status == Idle); 223 assert(!tickEvent.scheduled()); 224 225 notIdleFraction++; 226 tickEvent.schedule(curTick + cycles(delay)); 227 _status = Running; 228} 229 230 231void 232AtomicSimpleCPU::suspendContext(int thread_num) 233{ 234 assert(thread_num == 0); 235 assert(thread); 236 237 assert(_status == Running); 238 239 // tick event may not be scheduled if this gets called from inside 240 // an instruction's execution, e.g. "quiesce" 241 if (tickEvent.scheduled()) 242 tickEvent.deschedule(); 243 244 notIdleFraction--; 245 _status = Idle; 246} 247 248 249template <class T> 250Fault 251AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 252{ 253 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 254 255 if (traceData) { 256 traceData->setAddr(addr); 257 } 258 259 // translate to physical address 260 Fault fault = thread->translateDataReadReq(data_read_req); 261 262 // Now do the access. 263 if (fault == NoFault) { 264 data_read_pkt->reinitFromRequest(); 265 266 dcache_latency = dcachePort.sendAtomic(data_read_pkt); 267 dcache_access = true; 268 269 assert(data_read_pkt->result == Packet::Success); 270 data = data_read_pkt->get<T>(); 271 272 } 273 274 // This will need a new way to tell if it has a dcache attached. 275 if (data_read_req->getFlags() & UNCACHEABLE) 276 recordEvent("Uncached Read"); 277 278 return fault; 279} 280 281#ifndef DOXYGEN_SHOULD_SKIP_THIS 282 283template 284Fault 285AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 286 287template 288Fault 289AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 290 291template 292Fault 293AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 294 295template 296Fault 297AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 298 299#endif //DOXYGEN_SHOULD_SKIP_THIS 300 301template<> 302Fault 303AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 304{ 305 return read(addr, *(uint64_t*)&data, flags); 306} 307 308template<> 309Fault 310AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 311{ 312 return read(addr, *(uint32_t*)&data, flags); 313} 314 315 316template<> 317Fault 318AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 319{ 320 return read(addr, (uint32_t&)data, flags); 321} 322 323 324template <class T> 325Fault 326AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 327{ 328 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 329 330 if (traceData) { 331 traceData->setAddr(addr); 332 } 333 334 // translate to physical address 335 Fault fault = thread->translateDataWriteReq(data_write_req); 336 337 // Now do the access. 338 if (fault == NoFault) { 339 data = htog(data); 340 data_write_pkt->reinitFromRequest(); 341 data_write_pkt->dataStatic(&data); 342 343 dcache_latency = dcachePort.sendAtomic(data_write_pkt); 344 dcache_access = true; 345 346 assert(data_write_pkt->result == Packet::Success); 347 348 if (res && data_write_req->getFlags() & LOCKED) { 349 *res = data_write_req->getScResult(); 350 } 351 } 352 353 // This will need a new way to tell if it's hooked up to a cache or not. 354 if (data_write_req->getFlags() & UNCACHEABLE) 355 recordEvent("Uncached Write"); 356 357 // If the write needs to have a fault on the access, consider calling 358 // changeStatus() and changing it to "bad addr write" or something. 359 return fault; 360} 361 362 363#ifndef DOXYGEN_SHOULD_SKIP_THIS 364template 365Fault 366AtomicSimpleCPU::write(uint64_t data, Addr addr, 367 unsigned flags, uint64_t *res); 368 369template 370Fault 371AtomicSimpleCPU::write(uint32_t data, Addr addr, 372 unsigned flags, uint64_t *res); 373 374template 375Fault 376AtomicSimpleCPU::write(uint16_t data, Addr addr, 377 unsigned flags, uint64_t *res); 378 379template 380Fault 381AtomicSimpleCPU::write(uint8_t data, Addr addr, 382 unsigned flags, uint64_t *res); 383 384#endif //DOXYGEN_SHOULD_SKIP_THIS 385 386template<> 387Fault 388AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 389{ 390 return write(*(uint64_t*)&data, addr, flags, res); 391} 392 393template<> 394Fault 395AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 396{ 397 return write(*(uint32_t*)&data, addr, flags, res); 398} 399 400 401template<> 402Fault 403AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 404{ 405 return write((uint32_t)data, addr, flags, res); 406} 407 408 409void 410AtomicSimpleCPU::tick() 411{ 412 Tick latency = cycles(1); // instruction takes one cycle by default 413 414 for (int i = 0; i < width; ++i) { 415 numCycles++; 416 417 checkForInterrupts(); 418 419 Fault fault = setupFetchRequest(ifetch_req); 420 421 if (fault == NoFault) { 422 ifetch_pkt->reinitFromRequest(); 423 424 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 425 // ifetch_req is initialized to read the instruction directly 426 // into the CPU object's inst field. 427 428 dcache_access = false; // assume no dcache access 429 preExecute(); 430 fault = curStaticInst->execute(this, traceData); 431 postExecute(); 432 433 if (simulate_stalls) { 434 Tick icache_stall = icache_latency - cycles(1); 435 Tick dcache_stall = 436 dcache_access ? dcache_latency - cycles(1) : 0; 437 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 438 if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 439 latency += cycles(stall_cycles+1); 440 else 441 latency += cycles(stall_cycles); 442 } 443 444 } 445 446 advancePC(fault); 447 } 448 449 if (_status != Idle) 450 tickEvent.schedule(curTick + latency); 451} 452 453 454//////////////////////////////////////////////////////////////////////// 455// 456// AtomicSimpleCPU Simulation Object 457// 458BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 459 460 Param<Counter> max_insts_any_thread; 461 Param<Counter> max_insts_all_threads; 462 Param<Counter> max_loads_any_thread; 463 Param<Counter> max_loads_all_threads; 464 SimObjectParam<MemObject *> mem; 465 466#if FULL_SYSTEM 467 SimObjectParam<AlphaITB *> itb; 468 SimObjectParam<AlphaDTB *> dtb; 469 SimObjectParam<System *> system; 470 Param<int> cpu_id; 471 Param<Tick> profile; 472#else 473 SimObjectParam<Process *> workload; 474#endif // FULL_SYSTEM 475 476 Param<int> clock; 477 478 Param<bool> defer_registration; 479 Param<int> width; 480 Param<bool> function_trace; 481 Param<Tick> function_trace_start; 482 Param<bool> simulate_stalls; 483 484END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 485 486BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 487 488 INIT_PARAM(max_insts_any_thread, 489 "terminate when any thread reaches this inst count"), 490 INIT_PARAM(max_insts_all_threads, 491 "terminate when all threads have reached this inst count"), 492 INIT_PARAM(max_loads_any_thread, 493 "terminate when any thread reaches this load count"), 494 INIT_PARAM(max_loads_all_threads, 495 "terminate when all threads have reached this load count"), 496 INIT_PARAM(mem, "memory"), 497 498#if FULL_SYSTEM 499 INIT_PARAM(itb, "Instruction TLB"), 500 INIT_PARAM(dtb, "Data TLB"), 501 INIT_PARAM(system, "system object"), 502 INIT_PARAM(cpu_id, "processor ID"), 503 INIT_PARAM(profile, ""), 504#else 505 INIT_PARAM(workload, "processes to run"), 506#endif // FULL_SYSTEM 507 508 INIT_PARAM(clock, "clock speed"), 509 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 510 INIT_PARAM(width, "cpu width"), 511 INIT_PARAM(function_trace, "Enable function trace"), 512 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 513 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 514 515END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 516 517 518CREATE_SIM_OBJECT(AtomicSimpleCPU) 519{ 520 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 521 params->name = getInstanceName(); 522 params->numberOfThreads = 1; 523 params->max_insts_any_thread = max_insts_any_thread; 524 params->max_insts_all_threads = max_insts_all_threads; 525 params->max_loads_any_thread = max_loads_any_thread; 526 params->max_loads_all_threads = max_loads_all_threads; 527 params->deferRegistration = defer_registration; 528 params->clock = clock; 529 params->functionTrace = function_trace; 530 params->functionTraceStart = function_trace_start; 531 params->width = width; 532 params->simulate_stalls = simulate_stalls; 533 params->mem = mem; 534 535#if FULL_SYSTEM 536 params->itb = itb; 537 params->dtb = dtb; 538 params->system = system; 539 params->cpu_id = cpu_id; 540 params->profile = profile; 541#else 542 params->process = workload; 543#endif 544 545 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 546 return cpu; 547} 548 549REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 550 551