atomic.cc revision 11526:5b81895e5d5e
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013,2015 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "base/output.hh" 49#include "config/the_isa.hh" 50#include "cpu/simple/atomic.hh" 51#include "cpu/exetrace.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "mem/physical.hh" 58#include "params/AtomicSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/system.hh" 61#include "sim/full_system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 67 : Event(CPU_Tick_Pri), cpu(c) 68{ 69} 70 71 72void 73AtomicSimpleCPU::TickEvent::process() 74{ 75 cpu->tick(); 76} 77 78const char * 79AtomicSimpleCPU::TickEvent::description() const 80{ 81 return "AtomicSimpleCPU tick"; 82} 83 84void 85AtomicSimpleCPU::init() 86{ 87 BaseSimpleCPU::init(); 88 89 int cid = threadContexts[0]->contextId(); 90 ifetch_req.setContext(cid); 91 data_read_req.setContext(cid); 92 data_write_req.setContext(cid); 93} 94 95AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 96 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 97 simulate_data_stalls(p->simulate_data_stalls), 98 simulate_inst_stalls(p->simulate_inst_stalls), 99 icachePort(name() + ".icache_port", this), 100 dcachePort(name() + ".dcache_port", this), 101 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 102 ppCommit(nullptr) 103{ 104 _status = Idle; 105} 106 107 108AtomicSimpleCPU::~AtomicSimpleCPU() 109{ 110 if (tickEvent.scheduled()) { 111 deschedule(tickEvent); 112 } 113} 114 115DrainState 116AtomicSimpleCPU::drain() 117{ 118 if (switchedOut()) 119 return DrainState::Drained; 120 121 if (!isDrained()) { 122 DPRINTF(Drain, "Requesting drain.\n"); 123 return DrainState::Draining; 124 } else { 125 if (tickEvent.scheduled()) 126 deschedule(tickEvent); 127 128 activeThreads.clear(); 129 DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 130 return DrainState::Drained; 131 } 132} 133 134void 135AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 136{ 137 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 138 pkt->cmdString()); 139 140 for (ThreadID tid = 0; tid < numThreads; tid++) { 141 if (tid != sender) { 142 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 143 wakeup(tid); 144 } 145 146 TheISA::handleLockedSnoop(threadInfo[tid]->thread, 147 pkt, dcachePort.cacheBlockMask); 148 } 149 } 150} 151 152void 153AtomicSimpleCPU::drainResume() 154{ 155 assert(!tickEvent.scheduled()); 156 if (switchedOut()) 157 return; 158 159 DPRINTF(SimpleCPU, "Resume\n"); 160 verifyMemoryMode(); 161 162 assert(!threadContexts.empty()); 163 164 _status = BaseSimpleCPU::Idle; 165 166 for (ThreadID tid = 0; tid < numThreads; tid++) { 167 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 168 threadInfo[tid]->notIdleFraction = 1; 169 activeThreads.push_back(tid); 170 _status = BaseSimpleCPU::Running; 171 172 // Tick if any threads active 173 if (!tickEvent.scheduled()) { 174 schedule(tickEvent, nextCycle()); 175 } 176 } else { 177 threadInfo[tid]->notIdleFraction = 0; 178 } 179 } 180} 181 182bool 183AtomicSimpleCPU::tryCompleteDrain() 184{ 185 if (drainState() != DrainState::Draining) 186 return false; 187 188 DPRINTF(Drain, "tryCompleteDrain.\n"); 189 if (!isDrained()) 190 return false; 191 192 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 193 signalDrainDone(); 194 195 return true; 196} 197 198 199void 200AtomicSimpleCPU::switchOut() 201{ 202 BaseSimpleCPU::switchOut(); 203 204 assert(!tickEvent.scheduled()); 205 assert(_status == BaseSimpleCPU::Running || _status == Idle); 206 assert(isDrained()); 207} 208 209 210void 211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 212{ 213 BaseSimpleCPU::takeOverFrom(oldCPU); 214 215 // The tick event should have been descheduled by drain() 216 assert(!tickEvent.scheduled()); 217} 218 219void 220AtomicSimpleCPU::verifyMemoryMode() const 221{ 222 if (!system->isAtomicMode()) { 223 fatal("The atomic CPU requires the memory system to be in " 224 "'atomic' mode.\n"); 225 } 226} 227 228void 229AtomicSimpleCPU::activateContext(ThreadID thread_num) 230{ 231 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 232 233 assert(thread_num < numThreads); 234 235 threadInfo[thread_num]->notIdleFraction = 1; 236 Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 237 threadInfo[thread_num]->thread->lastSuspend); 238 numCycles += delta; 239 ppCycles->notify(delta); 240 241 if (!tickEvent.scheduled()) { 242 //Make sure ticks are still on multiples of cycles 243 schedule(tickEvent, clockEdge(Cycles(0))); 244 } 245 _status = BaseSimpleCPU::Running; 246 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 247 == activeThreads.end()) { 248 activeThreads.push_back(thread_num); 249 } 250 251 BaseCPU::activateContext(thread_num); 252} 253 254 255void 256AtomicSimpleCPU::suspendContext(ThreadID thread_num) 257{ 258 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 259 260 assert(thread_num < numThreads); 261 activeThreads.remove(thread_num); 262 263 if (_status == Idle) 264 return; 265 266 assert(_status == BaseSimpleCPU::Running); 267 268 threadInfo[thread_num]->notIdleFraction = 0; 269 270 if (activeThreads.empty()) { 271 _status = Idle; 272 273 if (tickEvent.scheduled()) { 274 deschedule(tickEvent); 275 } 276 } 277 278 BaseCPU::suspendContext(thread_num); 279} 280 281 282Tick 283AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 284{ 285 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 286 pkt->cmdString()); 287 288 // X86 ISA: Snooping an invalidation for monitor/mwait 289 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 290 291 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 292 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 293 cpu->wakeup(tid); 294 } 295 } 296 297 // if snoop invalidates, release any associated locks 298 // When run without caches, Invalidation packets will not be received 299 // hence we must check if the incoming packets are writes and wakeup 300 // the processor accordingly 301 if (pkt->isInvalidate() || pkt->isWrite()) { 302 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 303 pkt->getAddr()); 304 for (auto &t_info : cpu->threadInfo) { 305 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 306 } 307 } 308 309 return 0; 310} 311 312void 313AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 314{ 315 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 316 pkt->cmdString()); 317 318 // X86 ISA: Snooping an invalidation for monitor/mwait 319 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 320 for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 321 if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 322 cpu->wakeup(tid); 323 } 324 } 325 326 // if snoop invalidates, release any associated locks 327 if (pkt->isInvalidate()) { 328 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 329 pkt->getAddr()); 330 for (auto &t_info : cpu->threadInfo) { 331 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 332 } 333 } 334} 335 336Fault 337AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 338 unsigned size, unsigned flags) 339{ 340 SimpleExecContext& t_info = *threadInfo[curThread]; 341 SimpleThread* thread = t_info.thread; 342 343 // use the CPU's statically allocated read request and packet objects 344 Request *req = &data_read_req; 345 346 if (traceData) 347 traceData->setMem(addr, size, flags); 348 349 //The size of the data we're trying to read. 350 int fullSize = size; 351 352 //The address of the second part of this access if it needs to be split 353 //across a cache line boundary. 354 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 355 356 if (secondAddr > addr) 357 size = secondAddr - addr; 358 359 dcache_latency = 0; 360 361 req->taskId(taskId()); 362 while (1) { 363 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 364 365 // translate to physical address 366 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 367 BaseTLB::Read); 368 369 // Now do the access. 370 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 371 Packet pkt(req, Packet::makeReadCmd(req)); 372 pkt.dataStatic(data); 373 374 if (req->isMmappedIpr()) 375 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 376 else { 377 if (fastmem && system->isMemAddr(pkt.getAddr())) 378 system->getPhysMem().access(&pkt); 379 else 380 dcache_latency += dcachePort.sendAtomic(&pkt); 381 } 382 dcache_access = true; 383 384 assert(!pkt.isError()); 385 386 if (req->isLLSC()) { 387 TheISA::handleLockedRead(thread, req); 388 } 389 } 390 391 //If there's a fault, return it 392 if (fault != NoFault) { 393 if (req->isPrefetch()) { 394 return NoFault; 395 } else { 396 return fault; 397 } 398 } 399 400 //If we don't need to access a second cache line, stop now. 401 if (secondAddr <= addr) 402 { 403 if (req->isLockedRMW() && fault == NoFault) { 404 assert(!locked); 405 locked = true; 406 } 407 408 return fault; 409 } 410 411 /* 412 * Set up for accessing the second cache line. 413 */ 414 415 //Move the pointer we're reading into to the correct location. 416 data += size; 417 //Adjust the size to get the remaining bytes. 418 size = addr + fullSize - secondAddr; 419 //And access the right address. 420 addr = secondAddr; 421 } 422} 423 424Fault 425AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 426{ 427 panic("initiateMemRead() is for timing accesses, and should " 428 "never be called on AtomicSimpleCPU.\n"); 429} 430 431Fault 432AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 433 Addr addr, unsigned flags, uint64_t *res) 434{ 435 SimpleExecContext& t_info = *threadInfo[curThread]; 436 SimpleThread* thread = t_info.thread; 437 static uint8_t zero_array[64] = {}; 438 439 if (data == NULL) { 440 assert(size <= 64); 441 assert(flags & Request::CACHE_BLOCK_ZERO); 442 // This must be a cache block cleaning request 443 data = zero_array; 444 } 445 446 // use the CPU's statically allocated write request and packet objects 447 Request *req = &data_write_req; 448 449 if (traceData) 450 traceData->setMem(addr, size, flags); 451 452 //The size of the data we're trying to read. 453 int fullSize = size; 454 455 //The address of the second part of this access if it needs to be split 456 //across a cache line boundary. 457 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 458 459 if (secondAddr > addr) 460 size = secondAddr - addr; 461 462 dcache_latency = 0; 463 464 req->taskId(taskId()); 465 while (1) { 466 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 467 468 // translate to physical address 469 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 470 471 // Now do the access. 472 if (fault == NoFault) { 473 MemCmd cmd = MemCmd::WriteReq; // default 474 bool do_access = true; // flag to suppress cache access 475 476 if (req->isLLSC()) { 477 cmd = MemCmd::StoreCondReq; 478 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 479 } else if (req->isSwap()) { 480 cmd = MemCmd::SwapReq; 481 if (req->isCondSwap()) { 482 assert(res); 483 req->setExtraData(*res); 484 } 485 } 486 487 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 488 Packet pkt = Packet(req, cmd); 489 pkt.dataStatic(data); 490 491 if (req->isMmappedIpr()) { 492 dcache_latency += 493 TheISA::handleIprWrite(thread->getTC(), &pkt); 494 } else { 495 if (fastmem && system->isMemAddr(pkt.getAddr())) 496 system->getPhysMem().access(&pkt); 497 else 498 dcache_latency += dcachePort.sendAtomic(&pkt); 499 500 // Notify other threads on this CPU of write 501 threadSnoop(&pkt, curThread); 502 } 503 dcache_access = true; 504 assert(!pkt.isError()); 505 506 if (req->isSwap()) { 507 assert(res); 508 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 509 } 510 } 511 512 if (res && !req->isSwap()) { 513 *res = req->getExtraData(); 514 } 515 } 516 517 //If there's a fault or we don't need to access a second cache line, 518 //stop now. 519 if (fault != NoFault || secondAddr <= addr) 520 { 521 if (req->isLockedRMW() && fault == NoFault) { 522 assert(locked); 523 locked = false; 524 } 525 526 527 if (fault != NoFault && req->isPrefetch()) { 528 return NoFault; 529 } else { 530 return fault; 531 } 532 } 533 534 /* 535 * Set up for accessing the second cache line. 536 */ 537 538 //Move the pointer we're reading into to the correct location. 539 data += size; 540 //Adjust the size to get the remaining bytes. 541 size = addr + fullSize - secondAddr; 542 //And access the right address. 543 addr = secondAddr; 544 } 545} 546 547 548void 549AtomicSimpleCPU::tick() 550{ 551 DPRINTF(SimpleCPU, "Tick\n"); 552 553 // Change thread if multi-threaded 554 swapActiveThread(); 555 556 // Set memroy request ids to current thread 557 if (numThreads > 1) { 558 ContextID cid = threadContexts[curThread]->contextId(); 559 560 ifetch_req.setContext(cid); 561 data_read_req.setContext(cid); 562 data_write_req.setContext(cid); 563 } 564 565 SimpleExecContext& t_info = *threadInfo[curThread]; 566 SimpleThread* thread = t_info.thread; 567 568 Tick latency = 0; 569 570 for (int i = 0; i < width || locked; ++i) { 571 numCycles++; 572 ppCycles->notify(1); 573 574 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 575 checkForInterrupts(); 576 checkPcEventQueue(); 577 } 578 579 // We must have just got suspended by a PC event 580 if (_status == Idle) { 581 tryCompleteDrain(); 582 return; 583 } 584 585 Fault fault = NoFault; 586 587 TheISA::PCState pcState = thread->pcState(); 588 589 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 590 !curMacroStaticInst; 591 if (needToFetch) { 592 ifetch_req.taskId(taskId()); 593 setupFetchRequest(&ifetch_req); 594 fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 595 BaseTLB::Execute); 596 } 597 598 if (fault == NoFault) { 599 Tick icache_latency = 0; 600 bool icache_access = false; 601 dcache_access = false; // assume no dcache access 602 603 if (needToFetch) { 604 // This is commented out because the decoder would act like 605 // a tiny cache otherwise. It wouldn't be flushed when needed 606 // like the I cache. It should be flushed, and when that works 607 // this code should be uncommented. 608 //Fetch more instruction memory if necessary 609 //if (decoder.needMoreBytes()) 610 //{ 611 icache_access = true; 612 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 613 ifetch_pkt.dataStatic(&inst); 614 615 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 616 system->getPhysMem().access(&ifetch_pkt); 617 else 618 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 619 620 assert(!ifetch_pkt.isError()); 621 622 // ifetch_req is initialized to read the instruction directly 623 // into the CPU object's inst field. 624 //} 625 } 626 627 preExecute(); 628 629 if (curStaticInst) { 630 fault = curStaticInst->execute(&t_info, traceData); 631 632 // keep an instruction count 633 if (fault == NoFault) { 634 countInst(); 635 ppCommit->notify(std::make_pair(thread, curStaticInst)); 636 } 637 else if (traceData && !DTRACE(ExecFaulting)) { 638 delete traceData; 639 traceData = NULL; 640 } 641 642 postExecute(); 643 } 644 645 // @todo remove me after debugging with legion done 646 if (curStaticInst && (!curStaticInst->isMicroop() || 647 curStaticInst->isFirstMicroop())) 648 instCnt++; 649 650 Tick stall_ticks = 0; 651 if (simulate_inst_stalls && icache_access) 652 stall_ticks += icache_latency; 653 654 if (simulate_data_stalls && dcache_access) 655 stall_ticks += dcache_latency; 656 657 if (stall_ticks) { 658 // the atomic cpu does its accounting in ticks, so 659 // keep counting in ticks but round to the clock 660 // period 661 latency += divCeil(stall_ticks, clockPeriod()) * 662 clockPeriod(); 663 } 664 665 } 666 if (fault != NoFault || !t_info.stayAtPC) 667 advancePC(fault); 668 } 669 670 if (tryCompleteDrain()) 671 return; 672 673 // instruction takes at least one cycle 674 if (latency < clockPeriod()) 675 latency = clockPeriod(); 676 677 if (_status != Idle) 678 reschedule(tickEvent, curTick() + latency, true); 679} 680 681void 682AtomicSimpleCPU::regProbePoints() 683{ 684 BaseCPU::regProbePoints(); 685 686 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 687 (getProbeManager(), "Commit"); 688} 689 690void 691AtomicSimpleCPU::printAddr(Addr a) 692{ 693 dcachePort.printAddr(a); 694} 695 696//////////////////////////////////////////////////////////////////////// 697// 698// AtomicSimpleCPU Simulation Object 699// 700AtomicSimpleCPU * 701AtomicSimpleCPUParams::create() 702{ 703 return new AtomicSimpleCPU(this); 704} 705