atomic.cc revision 11303:f694764d656d
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/locked_mem.hh"
45#include "arch/mmapped_ipr.hh"
46#include "arch/utility.hh"
47#include "base/bigint.hh"
48#include "base/output.hh"
49#include "config/the_isa.hh"
50#include "cpu/simple/atomic.hh"
51#include "cpu/exetrace.hh"
52#include "debug/Drain.hh"
53#include "debug/ExecFaulting.hh"
54#include "debug/SimpleCPU.hh"
55#include "mem/packet.hh"
56#include "mem/packet_access.hh"
57#include "mem/physical.hh"
58#include "params/AtomicSimpleCPU.hh"
59#include "sim/faults.hh"
60#include "sim/system.hh"
61#include "sim/full_system.hh"
62
63using namespace std;
64using namespace TheISA;
65
66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
67    : Event(CPU_Tick_Pri), cpu(c)
68{
69}
70
71
72void
73AtomicSimpleCPU::TickEvent::process()
74{
75    cpu->tick();
76}
77
78const char *
79AtomicSimpleCPU::TickEvent::description() const
80{
81    return "AtomicSimpleCPU tick";
82}
83
84void
85AtomicSimpleCPU::init()
86{
87    BaseSimpleCPU::init();
88
89    int cid = threadContexts[0]->contextId();
90    ifetch_req.setThreadContext(cid, 0);
91    data_read_req.setThreadContext(cid, 0);
92    data_write_req.setThreadContext(cid, 0);
93}
94
95AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
96    : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
97      simulate_data_stalls(p->simulate_data_stalls),
98      simulate_inst_stalls(p->simulate_inst_stalls),
99      icachePort(name() + ".icache_port", this),
100      dcachePort(name() + ".dcache_port", this),
101      fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
102      ppCommit(nullptr)
103{
104    _status = Idle;
105}
106
107
108AtomicSimpleCPU::~AtomicSimpleCPU()
109{
110    if (tickEvent.scheduled()) {
111        deschedule(tickEvent);
112    }
113}
114
115DrainState
116AtomicSimpleCPU::drain()
117{
118    if (switchedOut())
119        return DrainState::Drained;
120
121    if (!isDrained()) {
122        DPRINTF(Drain, "Requesting drain.\n");
123        return DrainState::Draining;
124    } else {
125        if (tickEvent.scheduled())
126            deschedule(tickEvent);
127
128        activeThreads.clear();
129        DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
130        return DrainState::Drained;
131    }
132}
133
134void
135AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
136{
137    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
138            pkt->cmdString());
139
140    for (ThreadID tid = 0; tid < numThreads; tid++) {
141        if (tid != sender) {
142            if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
143                wakeup(tid);
144            }
145
146            TheISA::handleLockedSnoop(threadInfo[tid]->thread,
147                                      pkt, dcachePort.cacheBlockMask);
148        }
149    }
150}
151
152void
153AtomicSimpleCPU::drainResume()
154{
155    assert(!tickEvent.scheduled());
156    if (switchedOut())
157        return;
158
159    DPRINTF(SimpleCPU, "Resume\n");
160    verifyMemoryMode();
161
162    assert(!threadContexts.empty());
163
164    _status = BaseSimpleCPU::Idle;
165
166    for (ThreadID tid = 0; tid < numThreads; tid++) {
167        if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
168            threadInfo[tid]->notIdleFraction = 1;
169            activeThreads.push_back(tid);
170            _status = BaseSimpleCPU::Running;
171
172            // Tick if any threads active
173            if (!tickEvent.scheduled()) {
174                schedule(tickEvent, nextCycle());
175            }
176        } else {
177            threadInfo[tid]->notIdleFraction = 0;
178        }
179    }
180}
181
182bool
183AtomicSimpleCPU::tryCompleteDrain()
184{
185    if (drainState() != DrainState::Draining)
186        return false;
187
188    DPRINTF(Drain, "tryCompleteDrain.\n");
189    if (!isDrained())
190        return false;
191
192    DPRINTF(Drain, "CPU done draining, processing drain event\n");
193    signalDrainDone();
194
195    return true;
196}
197
198
199void
200AtomicSimpleCPU::switchOut()
201{
202    BaseSimpleCPU::switchOut();
203
204    assert(!tickEvent.scheduled());
205    assert(_status == BaseSimpleCPU::Running || _status == Idle);
206    assert(isDrained());
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213    BaseSimpleCPU::takeOverFrom(oldCPU);
214
215    // The tick event should have been descheduled by drain()
216    assert(!tickEvent.scheduled());
217}
218
219void
220AtomicSimpleCPU::verifyMemoryMode() const
221{
222    if (!system->isAtomicMode()) {
223        fatal("The atomic CPU requires the memory system to be in "
224              "'atomic' mode.\n");
225    }
226}
227
228void
229AtomicSimpleCPU::activateContext(ThreadID thread_num)
230{
231    DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
232
233    assert(thread_num < numThreads);
234
235    threadInfo[thread_num]->notIdleFraction = 1;
236    Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
237                                 threadInfo[thread_num]->thread->lastSuspend);
238    numCycles += delta;
239    ppCycles->notify(delta);
240
241    if (!tickEvent.scheduled()) {
242        //Make sure ticks are still on multiples of cycles
243        schedule(tickEvent, clockEdge(Cycles(0)));
244    }
245    _status = BaseSimpleCPU::Running;
246    if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
247        == activeThreads.end()) {
248        activeThreads.push_back(thread_num);
249    }
250}
251
252
253void
254AtomicSimpleCPU::suspendContext(ThreadID thread_num)
255{
256    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
257
258    assert(thread_num < numThreads);
259    activeThreads.remove(thread_num);
260
261    if (_status == Idle)
262        return;
263
264    assert(_status == BaseSimpleCPU::Running);
265
266    threadInfo[thread_num]->notIdleFraction = 0;
267
268    if (activeThreads.empty()) {
269        _status = Idle;
270
271        if (tickEvent.scheduled()) {
272            deschedule(tickEvent);
273        }
274    }
275
276}
277
278
279Tick
280AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
281{
282    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
283            pkt->cmdString());
284
285    // X86 ISA: Snooping an invalidation for monitor/mwait
286    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
287
288    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
289        if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
290            cpu->wakeup(tid);
291        }
292    }
293
294    // if snoop invalidates, release any associated locks
295    if (pkt->isInvalidate()) {
296        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
297                pkt->getAddr());
298        for (auto &t_info : cpu->threadInfo) {
299            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
300        }
301    }
302
303    return 0;
304}
305
306void
307AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
308{
309    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
310            pkt->cmdString());
311
312    // X86 ISA: Snooping an invalidation for monitor/mwait
313    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
314    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
315        if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
316            cpu->wakeup(tid);
317        }
318    }
319
320    // if snoop invalidates, release any associated locks
321    if (pkt->isInvalidate()) {
322        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
323                pkt->getAddr());
324        for (auto &t_info : cpu->threadInfo) {
325            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
326        }
327    }
328}
329
330Fault
331AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
332                         unsigned size, unsigned flags)
333{
334    SimpleExecContext& t_info = *threadInfo[curThread];
335    SimpleThread* thread = t_info.thread;
336
337    // use the CPU's statically allocated read request and packet objects
338    Request *req = &data_read_req;
339
340    if (traceData)
341        traceData->setMem(addr, size, flags);
342
343    //The size of the data we're trying to read.
344    int fullSize = size;
345
346    //The address of the second part of this access if it needs to be split
347    //across a cache line boundary.
348    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
349
350    if (secondAddr > addr)
351        size = secondAddr - addr;
352
353    dcache_latency = 0;
354
355    req->taskId(taskId());
356    while (1) {
357        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
358
359        // translate to physical address
360        Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
361                                                          BaseTLB::Read);
362
363        // Now do the access.
364        if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
365            Packet pkt(req, Packet::makeReadCmd(req));
366            pkt.dataStatic(data);
367
368            if (req->isMmappedIpr())
369                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
370            else {
371                if (fastmem && system->isMemAddr(pkt.getAddr()))
372                    system->getPhysMem().access(&pkt);
373                else
374                    dcache_latency += dcachePort.sendAtomic(&pkt);
375            }
376            dcache_access = true;
377
378            assert(!pkt.isError());
379
380            if (req->isLLSC()) {
381                TheISA::handleLockedRead(thread, req);
382            }
383        }
384
385        //If there's a fault, return it
386        if (fault != NoFault) {
387            if (req->isPrefetch()) {
388                return NoFault;
389            } else {
390                return fault;
391            }
392        }
393
394        //If we don't need to access a second cache line, stop now.
395        if (secondAddr <= addr)
396        {
397            if (req->isLockedRMW() && fault == NoFault) {
398                assert(!locked);
399                locked = true;
400            }
401
402            return fault;
403        }
404
405        /*
406         * Set up for accessing the second cache line.
407         */
408
409        //Move the pointer we're reading into to the correct location.
410        data += size;
411        //Adjust the size to get the remaining bytes.
412        size = addr + fullSize - secondAddr;
413        //And access the right address.
414        addr = secondAddr;
415    }
416}
417
418Fault
419AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
420{
421    panic("initiateMemRead() is for timing accesses, and should "
422          "never be called on AtomicSimpleCPU.\n");
423}
424
425Fault
426AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
427                          Addr addr, unsigned flags, uint64_t *res)
428{
429    SimpleExecContext& t_info = *threadInfo[curThread];
430    SimpleThread* thread = t_info.thread;
431    static uint8_t zero_array[64] = {};
432
433    if (data == NULL) {
434        assert(size <= 64);
435        assert(flags & Request::CACHE_BLOCK_ZERO);
436        // This must be a cache block cleaning request
437        data = zero_array;
438    }
439
440    // use the CPU's statically allocated write request and packet objects
441    Request *req = &data_write_req;
442
443    if (traceData)
444        traceData->setMem(addr, size, flags);
445
446    //The size of the data we're trying to read.
447    int fullSize = size;
448
449    //The address of the second part of this access if it needs to be split
450    //across a cache line boundary.
451    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
452
453    if(secondAddr > addr)
454        size = secondAddr - addr;
455
456    dcache_latency = 0;
457
458    req->taskId(taskId());
459    while(1) {
460        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
461
462        // translate to physical address
463        Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
464
465        // Now do the access.
466        if (fault == NoFault) {
467            MemCmd cmd = MemCmd::WriteReq; // default
468            bool do_access = true;  // flag to suppress cache access
469
470            if (req->isLLSC()) {
471                cmd = MemCmd::StoreCondReq;
472                do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
473            } else if (req->isSwap()) {
474                cmd = MemCmd::SwapReq;
475                if (req->isCondSwap()) {
476                    assert(res);
477                    req->setExtraData(*res);
478                }
479            }
480
481            if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
482                Packet pkt = Packet(req, cmd);
483                pkt.dataStatic(data);
484
485                if (req->isMmappedIpr()) {
486                    dcache_latency +=
487                        TheISA::handleIprWrite(thread->getTC(), &pkt);
488                } else {
489                    if (fastmem && system->isMemAddr(pkt.getAddr()))
490                        system->getPhysMem().access(&pkt);
491                    else
492                        dcache_latency += dcachePort.sendAtomic(&pkt);
493
494                    // Notify other threads on this CPU of write
495                    threadSnoop(&pkt, curThread);
496                }
497                dcache_access = true;
498                assert(!pkt.isError());
499
500                if (req->isSwap()) {
501                    assert(res);
502                    memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize);
503                }
504            }
505
506            if (res && !req->isSwap()) {
507                *res = req->getExtraData();
508            }
509        }
510
511        //If there's a fault or we don't need to access a second cache line,
512        //stop now.
513        if (fault != NoFault || secondAddr <= addr)
514        {
515            if (req->isLockedRMW() && fault == NoFault) {
516                assert(locked);
517                locked = false;
518            }
519
520
521            if (fault != NoFault && req->isPrefetch()) {
522                return NoFault;
523            } else {
524                return fault;
525            }
526        }
527
528        /*
529         * Set up for accessing the second cache line.
530         */
531
532        //Move the pointer we're reading into to the correct location.
533        data += size;
534        //Adjust the size to get the remaining bytes.
535        size = addr + fullSize - secondAddr;
536        //And access the right address.
537        addr = secondAddr;
538    }
539}
540
541
542void
543AtomicSimpleCPU::tick()
544{
545    DPRINTF(SimpleCPU, "Tick\n");
546
547    // Change thread if multi-threaded
548    swapActiveThread();
549
550    // Set memroy request ids to current thread
551    if (numThreads > 1) {
552        ContextID cid = threadContexts[curThread]->contextId();
553
554        ifetch_req.setThreadContext(cid, curThread);
555        data_read_req.setThreadContext(cid, curThread);
556        data_write_req.setThreadContext(cid, curThread);
557    }
558
559    SimpleExecContext& t_info = *threadInfo[curThread];
560    SimpleThread* thread = t_info.thread;
561
562    Tick latency = 0;
563
564    for (int i = 0; i < width || locked; ++i) {
565        numCycles++;
566        ppCycles->notify(1);
567
568        if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
569            checkForInterrupts();
570            checkPcEventQueue();
571        }
572
573        // We must have just got suspended by a PC event
574        if (_status == Idle) {
575            tryCompleteDrain();
576            return;
577        }
578
579        Fault fault = NoFault;
580
581        TheISA::PCState pcState = thread->pcState();
582
583        bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
584                           !curMacroStaticInst;
585        if (needToFetch) {
586            ifetch_req.taskId(taskId());
587            setupFetchRequest(&ifetch_req);
588            fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(),
589                                                 BaseTLB::Execute);
590        }
591
592        if (fault == NoFault) {
593            Tick icache_latency = 0;
594            bool icache_access = false;
595            dcache_access = false; // assume no dcache access
596
597            if (needToFetch) {
598                // This is commented out because the decoder would act like
599                // a tiny cache otherwise. It wouldn't be flushed when needed
600                // like the I cache. It should be flushed, and when that works
601                // this code should be uncommented.
602                //Fetch more instruction memory if necessary
603                //if(decoder.needMoreBytes())
604                //{
605                    icache_access = true;
606                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
607                    ifetch_pkt.dataStatic(&inst);
608
609                    if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
610                        system->getPhysMem().access(&ifetch_pkt);
611                    else
612                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
613
614                    assert(!ifetch_pkt.isError());
615
616                    // ifetch_req is initialized to read the instruction directly
617                    // into the CPU object's inst field.
618                //}
619            }
620
621            preExecute();
622
623            if (curStaticInst) {
624                fault = curStaticInst->execute(&t_info, traceData);
625
626                // keep an instruction count
627                if (fault == NoFault) {
628                    countInst();
629                    ppCommit->notify(std::make_pair(thread, curStaticInst));
630                }
631                else if (traceData && !DTRACE(ExecFaulting)) {
632                    delete traceData;
633                    traceData = NULL;
634                }
635
636                postExecute();
637            }
638
639            // @todo remove me after debugging with legion done
640            if (curStaticInst && (!curStaticInst->isMicroop() ||
641                        curStaticInst->isFirstMicroop()))
642                instCnt++;
643
644            Tick stall_ticks = 0;
645            if (simulate_inst_stalls && icache_access)
646                stall_ticks += icache_latency;
647
648            if (simulate_data_stalls && dcache_access)
649                stall_ticks += dcache_latency;
650
651            if (stall_ticks) {
652                // the atomic cpu does its accounting in ticks, so
653                // keep counting in ticks but round to the clock
654                // period
655                latency += divCeil(stall_ticks, clockPeriod()) *
656                    clockPeriod();
657            }
658
659        }
660        if(fault != NoFault || !t_info.stayAtPC)
661            advancePC(fault);
662    }
663
664    if (tryCompleteDrain())
665        return;
666
667    // instruction takes at least one cycle
668    if (latency < clockPeriod())
669        latency = clockPeriod();
670
671    if (_status != Idle)
672        reschedule(tickEvent, curTick() + latency, true);
673}
674
675void
676AtomicSimpleCPU::regProbePoints()
677{
678    BaseCPU::regProbePoints();
679
680    ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
681                                (getProbeManager(), "Commit");
682}
683
684void
685AtomicSimpleCPU::printAddr(Addr a)
686{
687    dcachePort.printAddr(a);
688}
689
690////////////////////////////////////////////////////////////////////////
691//
692//  AtomicSimpleCPU Simulation Object
693//
694AtomicSimpleCPU *
695AtomicSimpleCPUParams::create()
696{
697    return new AtomicSimpleCPU(this);
698}
699