atomic.cc revision 10739:4cfe55719da5
112810Sandreas.sandberg@arm.com/* 212810Sandreas.sandberg@arm.com * Copyright 2014 Google, Inc. 312810Sandreas.sandberg@arm.com * Copyright (c) 2012-2013 ARM Limited 412810Sandreas.sandberg@arm.com * All rights reserved. 512810Sandreas.sandberg@arm.com * 612810Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 712810Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 812810Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 912810Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 1012810Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1112810Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1212810Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1312810Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1412810Sandreas.sandberg@arm.com * 1512810Sandreas.sandberg@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1612810Sandreas.sandberg@arm.com * All rights reserved. 1712810Sandreas.sandberg@arm.com * 1812810Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1912810Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 2012810Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2112810Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2212810Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2312810Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2412810Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2512810Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2612810Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2712810Sandreas.sandberg@arm.com * this software without specific prior written permission. 2812810Sandreas.sandberg@arm.com * 2912810Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012810Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112810Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212810Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312810Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412810Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512810Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612810Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712810Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812810Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912810Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012810Sandreas.sandberg@arm.com * 4112810Sandreas.sandberg@arm.com * Authors: Steve Reinhardt 4212810Sandreas.sandberg@arm.com */ 4312810Sandreas.sandberg@arm.com 4412810Sandreas.sandberg@arm.com#include "arch/locked_mem.hh" 4512810Sandreas.sandberg@arm.com#include "arch/mmapped_ipr.hh" 4612810Sandreas.sandberg@arm.com#include "arch/utility.hh" 4712810Sandreas.sandberg@arm.com#include "base/bigint.hh" 4812810Sandreas.sandberg@arm.com#include "base/output.hh" 4912810Sandreas.sandberg@arm.com#include "config/the_isa.hh" 5012810Sandreas.sandberg@arm.com#include "cpu/simple/atomic.hh" 5112810Sandreas.sandberg@arm.com#include "cpu/exetrace.hh" 5212810Sandreas.sandberg@arm.com#include "debug/Drain.hh" 5312810Sandreas.sandberg@arm.com#include "debug/ExecFaulting.hh" 5412810Sandreas.sandberg@arm.com#include "debug/SimpleCPU.hh" 5512810Sandreas.sandberg@arm.com#include "mem/packet.hh" 5612810Sandreas.sandberg@arm.com#include "mem/packet_access.hh" 5712810Sandreas.sandberg@arm.com#include "mem/physical.hh" 5812810Sandreas.sandberg@arm.com#include "params/AtomicSimpleCPU.hh" 5912810Sandreas.sandberg@arm.com#include "sim/faults.hh" 6012810Sandreas.sandberg@arm.com#include "sim/system.hh" 6112810Sandreas.sandberg@arm.com#include "sim/full_system.hh" 6212810Sandreas.sandberg@arm.com 6312810Sandreas.sandberg@arm.comusing namespace std; 6412810Sandreas.sandberg@arm.comusing namespace TheISA; 6512810Sandreas.sandberg@arm.com 6612810Sandreas.sandberg@arm.comAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 6712810Sandreas.sandberg@arm.com : Event(CPU_Tick_Pri), cpu(c) 6812810Sandreas.sandberg@arm.com{ 6912810Sandreas.sandberg@arm.com} 7012810Sandreas.sandberg@arm.com 7112810Sandreas.sandberg@arm.com 7212810Sandreas.sandberg@arm.comvoid 7312810Sandreas.sandberg@arm.comAtomicSimpleCPU::TickEvent::process() 7412810Sandreas.sandberg@arm.com{ 7512810Sandreas.sandberg@arm.com cpu->tick(); 7612810Sandreas.sandberg@arm.com} 7712810Sandreas.sandberg@arm.com 7812810Sandreas.sandberg@arm.comconst char * 7912810Sandreas.sandberg@arm.comAtomicSimpleCPU::TickEvent::description() const 8012810Sandreas.sandberg@arm.com{ 8112810Sandreas.sandberg@arm.com return "AtomicSimpleCPU tick"; 8212810Sandreas.sandberg@arm.com} 8312810Sandreas.sandberg@arm.com 8412810Sandreas.sandberg@arm.comvoid 8512810Sandreas.sandberg@arm.comAtomicSimpleCPU::init() 8612810Sandreas.sandberg@arm.com{ 8712810Sandreas.sandberg@arm.com BaseCPU::init(); 8812810Sandreas.sandberg@arm.com 8912810Sandreas.sandberg@arm.com // Initialise the ThreadContext's memory proxies 9012810Sandreas.sandberg@arm.com tcBase()->initMemProxies(tcBase()); 9112810Sandreas.sandberg@arm.com 9212810Sandreas.sandberg@arm.com if (FullSystem && !params()->switched_out) { 9312810Sandreas.sandberg@arm.com ThreadID size = threadContexts.size(); 9412810Sandreas.sandberg@arm.com for (ThreadID i = 0; i < size; ++i) { 9512810Sandreas.sandberg@arm.com ThreadContext *tc = threadContexts[i]; 9612810Sandreas.sandberg@arm.com // initialize CPU, including PC 9712810Sandreas.sandberg@arm.com TheISA::initCPU(tc, tc->contextId()); 9812810Sandreas.sandberg@arm.com } 9912810Sandreas.sandberg@arm.com } 10012810Sandreas.sandberg@arm.com 10112810Sandreas.sandberg@arm.com // Atomic doesn't do MT right now, so contextId == threadId 10212810Sandreas.sandberg@arm.com ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 10312810Sandreas.sandberg@arm.com data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 10412810Sandreas.sandberg@arm.com data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 10512810Sandreas.sandberg@arm.com} 10612810Sandreas.sandberg@arm.com 10712810Sandreas.sandberg@arm.comAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 10812810Sandreas.sandberg@arm.com : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 10912810Sandreas.sandberg@arm.com simulate_data_stalls(p->simulate_data_stalls), 11012810Sandreas.sandberg@arm.com simulate_inst_stalls(p->simulate_inst_stalls), 11112810Sandreas.sandberg@arm.com drain_manager(NULL), 11212810Sandreas.sandberg@arm.com icachePort(name() + ".icache_port", this), 11312810Sandreas.sandberg@arm.com dcachePort(name() + ".dcache_port", this), 11412810Sandreas.sandberg@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 11512810Sandreas.sandberg@arm.com ppCommit(nullptr) 11612810Sandreas.sandberg@arm.com{ 11712810Sandreas.sandberg@arm.com _status = Idle; 11812810Sandreas.sandberg@arm.com} 11912810Sandreas.sandberg@arm.com 12012810Sandreas.sandberg@arm.com 12112810Sandreas.sandberg@arm.comAtomicSimpleCPU::~AtomicSimpleCPU() 12212810Sandreas.sandberg@arm.com{ 12312810Sandreas.sandberg@arm.com if (tickEvent.scheduled()) { 12412810Sandreas.sandberg@arm.com deschedule(tickEvent); 12512810Sandreas.sandberg@arm.com } 12612810Sandreas.sandberg@arm.com} 12712810Sandreas.sandberg@arm.com 12812810Sandreas.sandberg@arm.comunsigned int 12912810Sandreas.sandberg@arm.comAtomicSimpleCPU::drain(DrainManager *dm) 13012810Sandreas.sandberg@arm.com{ 13112810Sandreas.sandberg@arm.com assert(!drain_manager); 13212810Sandreas.sandberg@arm.com if (switchedOut()) 13312810Sandreas.sandberg@arm.com return 0; 13412810Sandreas.sandberg@arm.com 13512810Sandreas.sandberg@arm.com if (!isDrained()) { 13612810Sandreas.sandberg@arm.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 13712810Sandreas.sandberg@arm.com drain_manager = dm; 13812810Sandreas.sandberg@arm.com return 1; 13912810Sandreas.sandberg@arm.com } else { 14012810Sandreas.sandberg@arm.com if (tickEvent.scheduled()) 14112810Sandreas.sandberg@arm.com deschedule(tickEvent); 14212810Sandreas.sandberg@arm.com 14312810Sandreas.sandberg@arm.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 14412810Sandreas.sandberg@arm.com return 0; 14512810Sandreas.sandberg@arm.com } 14612810Sandreas.sandberg@arm.com} 14712810Sandreas.sandberg@arm.com 14812810Sandreas.sandberg@arm.comvoid 14912810Sandreas.sandberg@arm.comAtomicSimpleCPU::drainResume() 15012810Sandreas.sandberg@arm.com{ 15112810Sandreas.sandberg@arm.com assert(!tickEvent.scheduled()); 15212810Sandreas.sandberg@arm.com assert(!drain_manager); 15312810Sandreas.sandberg@arm.com if (switchedOut()) 15412810Sandreas.sandberg@arm.com return; 15512810Sandreas.sandberg@arm.com 15612810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "Resume\n"); 15712810Sandreas.sandberg@arm.com verifyMemoryMode(); 15812810Sandreas.sandberg@arm.com 15912810Sandreas.sandberg@arm.com assert(!threadContexts.empty()); 16012810Sandreas.sandberg@arm.com if (threadContexts.size() > 1) 16112810Sandreas.sandberg@arm.com fatal("The atomic CPU only supports one thread.\n"); 16212810Sandreas.sandberg@arm.com 16312810Sandreas.sandberg@arm.com if (thread->status() == ThreadContext::Active) { 16412810Sandreas.sandberg@arm.com schedule(tickEvent, nextCycle()); 16512810Sandreas.sandberg@arm.com _status = BaseSimpleCPU::Running; 16612810Sandreas.sandberg@arm.com notIdleFraction = 1; 16712810Sandreas.sandberg@arm.com } else { 16812810Sandreas.sandberg@arm.com _status = BaseSimpleCPU::Idle; 16912810Sandreas.sandberg@arm.com notIdleFraction = 0; 17012810Sandreas.sandberg@arm.com } 17112810Sandreas.sandberg@arm.com 17212810Sandreas.sandberg@arm.com system->totalNumInsts = 0; 17312810Sandreas.sandberg@arm.com} 17412810Sandreas.sandberg@arm.com 17512810Sandreas.sandberg@arm.combool 17612810Sandreas.sandberg@arm.comAtomicSimpleCPU::tryCompleteDrain() 17712810Sandreas.sandberg@arm.com{ 17812810Sandreas.sandberg@arm.com if (!drain_manager) 17912810Sandreas.sandberg@arm.com return false; 18012810Sandreas.sandberg@arm.com 18112810Sandreas.sandberg@arm.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 18212810Sandreas.sandberg@arm.com if (!isDrained()) 18312810Sandreas.sandberg@arm.com return false; 18412810Sandreas.sandberg@arm.com 18512810Sandreas.sandberg@arm.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 18612810Sandreas.sandberg@arm.com drain_manager->signalDrainDone(); 18712810Sandreas.sandberg@arm.com drain_manager = NULL; 18812810Sandreas.sandberg@arm.com 18912810Sandreas.sandberg@arm.com return true; 19012810Sandreas.sandberg@arm.com} 19112810Sandreas.sandberg@arm.com 19212810Sandreas.sandberg@arm.com 19312810Sandreas.sandberg@arm.comvoid 19412810Sandreas.sandberg@arm.comAtomicSimpleCPU::switchOut() 19512810Sandreas.sandberg@arm.com{ 19612810Sandreas.sandberg@arm.com BaseSimpleCPU::switchOut(); 19712810Sandreas.sandberg@arm.com 19812810Sandreas.sandberg@arm.com assert(!tickEvent.scheduled()); 19912810Sandreas.sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 20012810Sandreas.sandberg@arm.com assert(isDrained()); 20112810Sandreas.sandberg@arm.com} 20212810Sandreas.sandberg@arm.com 20312810Sandreas.sandberg@arm.com 20412810Sandreas.sandberg@arm.comvoid 20512810Sandreas.sandberg@arm.comAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 20612810Sandreas.sandberg@arm.com{ 20712810Sandreas.sandberg@arm.com BaseSimpleCPU::takeOverFrom(oldCPU); 20812810Sandreas.sandberg@arm.com 20912810Sandreas.sandberg@arm.com // The tick event should have been descheduled by drain() 21012810Sandreas.sandberg@arm.com assert(!tickEvent.scheduled()); 21112810Sandreas.sandberg@arm.com 21212810Sandreas.sandberg@arm.com ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 21312810Sandreas.sandberg@arm.com data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 21412810Sandreas.sandberg@arm.com data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 21512810Sandreas.sandberg@arm.com} 21612810Sandreas.sandberg@arm.com 21712810Sandreas.sandberg@arm.comvoid 21812810Sandreas.sandberg@arm.comAtomicSimpleCPU::verifyMemoryMode() const 21912810Sandreas.sandberg@arm.com{ 22012810Sandreas.sandberg@arm.com if (!system->isAtomicMode()) { 22112810Sandreas.sandberg@arm.com fatal("The atomic CPU requires the memory system to be in " 22212810Sandreas.sandberg@arm.com "'atomic' mode.\n"); 22312810Sandreas.sandberg@arm.com } 22412810Sandreas.sandberg@arm.com} 22512810Sandreas.sandberg@arm.com 22612810Sandreas.sandberg@arm.comvoid 22712810Sandreas.sandberg@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 22812810Sandreas.sandberg@arm.com{ 22912810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 23012810Sandreas.sandberg@arm.com 23112810Sandreas.sandberg@arm.com assert(thread_num == 0); 23212810Sandreas.sandberg@arm.com assert(thread); 23312810Sandreas.sandberg@arm.com 23412810Sandreas.sandberg@arm.com assert(_status == Idle); 23512810Sandreas.sandberg@arm.com assert(!tickEvent.scheduled()); 23612810Sandreas.sandberg@arm.com 23712810Sandreas.sandberg@arm.com notIdleFraction = 1; 23812810Sandreas.sandberg@arm.com Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend); 23912810Sandreas.sandberg@arm.com numCycles += delta; 24012810Sandreas.sandberg@arm.com ppCycles->notify(delta); 24112810Sandreas.sandberg@arm.com 24212810Sandreas.sandberg@arm.com //Make sure ticks are still on multiples of cycles 24312810Sandreas.sandberg@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 24412810Sandreas.sandberg@arm.com _status = BaseSimpleCPU::Running; 24512810Sandreas.sandberg@arm.com} 24612810Sandreas.sandberg@arm.com 24712810Sandreas.sandberg@arm.com 24812810Sandreas.sandberg@arm.comvoid 24912810Sandreas.sandberg@arm.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 25012810Sandreas.sandberg@arm.com{ 25112810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 25212810Sandreas.sandberg@arm.com 25312810Sandreas.sandberg@arm.com assert(thread_num == 0); 25412810Sandreas.sandberg@arm.com assert(thread); 25512810Sandreas.sandberg@arm.com 25612810Sandreas.sandberg@arm.com if (_status == Idle) 25712810Sandreas.sandberg@arm.com return; 25812810Sandreas.sandberg@arm.com 25912810Sandreas.sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 26012810Sandreas.sandberg@arm.com 26112810Sandreas.sandberg@arm.com // tick event may not be scheduled if this gets called from inside 26212810Sandreas.sandberg@arm.com // an instruction's execution, e.g. "quiesce" 26312810Sandreas.sandberg@arm.com if (tickEvent.scheduled()) 26412810Sandreas.sandberg@arm.com deschedule(tickEvent); 26512810Sandreas.sandberg@arm.com 26612810Sandreas.sandberg@arm.com notIdleFraction = 0; 26712810Sandreas.sandberg@arm.com _status = Idle; 26812810Sandreas.sandberg@arm.com} 26912810Sandreas.sandberg@arm.com 27012810Sandreas.sandberg@arm.com 27112810Sandreas.sandberg@arm.comTick 27212810Sandreas.sandberg@arm.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27312810Sandreas.sandberg@arm.com{ 27412810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27512810Sandreas.sandberg@arm.com pkt->cmdString()); 27612810Sandreas.sandberg@arm.com 27712810Sandreas.sandberg@arm.com // X86 ISA: Snooping an invalidation for monitor/mwait 27812810Sandreas.sandberg@arm.com AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 27912810Sandreas.sandberg@arm.com if(cpu->getAddrMonitor()->doMonitor(pkt)) { 28012810Sandreas.sandberg@arm.com cpu->wakeup(); 28112810Sandreas.sandberg@arm.com } 28212810Sandreas.sandberg@arm.com 28312810Sandreas.sandberg@arm.com // if snoop invalidates, release any associated locks 28412810Sandreas.sandberg@arm.com if (pkt->isInvalidate()) { 28512810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 28612810Sandreas.sandberg@arm.com pkt->getAddr()); 28712810Sandreas.sandberg@arm.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 28812810Sandreas.sandberg@arm.com } 28912810Sandreas.sandberg@arm.com 29012810Sandreas.sandberg@arm.com return 0; 29112810Sandreas.sandberg@arm.com} 29212810Sandreas.sandberg@arm.com 29312810Sandreas.sandberg@arm.comvoid 29412810Sandreas.sandberg@arm.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 29512810Sandreas.sandberg@arm.com{ 29612810Sandreas.sandberg@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 29712810Sandreas.sandberg@arm.com pkt->cmdString()); 29812810Sandreas.sandberg@arm.com 29912810Sandreas.sandberg@arm.com // X86 ISA: Snooping an invalidation for monitor/mwait 30012810Sandreas.sandberg@arm.com AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 30112810Sandreas.sandberg@arm.com if(cpu->getAddrMonitor()->doMonitor(pkt)) { 30212810Sandreas.sandberg@arm.com cpu->wakeup(); 30312810Sandreas.sandberg@arm.com } 30412810Sandreas.sandberg@arm.com 30512810Sandreas.sandberg@arm.com // if snoop invalidates, release any associated locks 30612810Sandreas.sandberg@arm.com if (pkt->isInvalidate()) { 307 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 308 pkt->getAddr()); 309 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 310 } 311} 312 313Fault 314AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 315 unsigned size, unsigned flags) 316{ 317 // use the CPU's statically allocated read request and packet objects 318 Request *req = &data_read_req; 319 320 if (traceData) 321 traceData->setMem(addr, size, flags); 322 323 //The size of the data we're trying to read. 324 int fullSize = size; 325 326 //The address of the second part of this access if it needs to be split 327 //across a cache line boundary. 328 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 329 330 if (secondAddr > addr) 331 size = secondAddr - addr; 332 333 dcache_latency = 0; 334 335 req->taskId(taskId()); 336 while (1) { 337 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 338 339 // translate to physical address 340 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 341 342 // Now do the access. 343 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 344 Packet pkt(req, Packet::makeReadCmd(req)); 345 pkt.dataStatic(data); 346 347 if (req->isMmappedIpr()) 348 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 349 else { 350 if (fastmem && system->isMemAddr(pkt.getAddr())) 351 system->getPhysMem().access(&pkt); 352 else 353 dcache_latency += dcachePort.sendAtomic(&pkt); 354 } 355 dcache_access = true; 356 357 assert(!pkt.isError()); 358 359 if (req->isLLSC()) { 360 TheISA::handleLockedRead(thread, req); 361 } 362 } 363 364 //If there's a fault, return it 365 if (fault != NoFault) { 366 if (req->isPrefetch()) { 367 return NoFault; 368 } else { 369 return fault; 370 } 371 } 372 373 //If we don't need to access a second cache line, stop now. 374 if (secondAddr <= addr) 375 { 376 if (req->isLocked() && fault == NoFault) { 377 assert(!locked); 378 locked = true; 379 } 380 return fault; 381 } 382 383 /* 384 * Set up for accessing the second cache line. 385 */ 386 387 //Move the pointer we're reading into to the correct location. 388 data += size; 389 //Adjust the size to get the remaining bytes. 390 size = addr + fullSize - secondAddr; 391 //And access the right address. 392 addr = secondAddr; 393 } 394} 395 396 397Fault 398AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 399 Addr addr, unsigned flags, uint64_t *res) 400{ 401 402 static uint8_t zero_array[64] = {}; 403 404 if (data == NULL) { 405 assert(size <= 64); 406 assert(flags & Request::CACHE_BLOCK_ZERO); 407 // This must be a cache block cleaning request 408 data = zero_array; 409 } 410 411 // use the CPU's statically allocated write request and packet objects 412 Request *req = &data_write_req; 413 414 if (traceData) 415 traceData->setMem(addr, size, flags); 416 417 //The size of the data we're trying to read. 418 int fullSize = size; 419 420 //The address of the second part of this access if it needs to be split 421 //across a cache line boundary. 422 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 423 424 if(secondAddr > addr) 425 size = secondAddr - addr; 426 427 dcache_latency = 0; 428 429 req->taskId(taskId()); 430 while(1) { 431 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 432 433 // translate to physical address 434 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 435 436 // Now do the access. 437 if (fault == NoFault) { 438 MemCmd cmd = MemCmd::WriteReq; // default 439 bool do_access = true; // flag to suppress cache access 440 441 if (req->isLLSC()) { 442 cmd = MemCmd::StoreCondReq; 443 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 444 } else if (req->isSwap()) { 445 cmd = MemCmd::SwapReq; 446 if (req->isCondSwap()) { 447 assert(res); 448 req->setExtraData(*res); 449 } 450 } 451 452 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 453 Packet pkt = Packet(req, cmd); 454 pkt.dataStatic(data); 455 456 if (req->isMmappedIpr()) { 457 dcache_latency += 458 TheISA::handleIprWrite(thread->getTC(), &pkt); 459 } else { 460 if (fastmem && system->isMemAddr(pkt.getAddr())) 461 system->getPhysMem().access(&pkt); 462 else 463 dcache_latency += dcachePort.sendAtomic(&pkt); 464 } 465 dcache_access = true; 466 assert(!pkt.isError()); 467 468 if (req->isSwap()) { 469 assert(res); 470 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 471 } 472 } 473 474 if (res && !req->isSwap()) { 475 *res = req->getExtraData(); 476 } 477 } 478 479 //If there's a fault or we don't need to access a second cache line, 480 //stop now. 481 if (fault != NoFault || secondAddr <= addr) 482 { 483 if (req->isLocked() && fault == NoFault) { 484 assert(locked); 485 locked = false; 486 } 487 if (fault != NoFault && req->isPrefetch()) { 488 return NoFault; 489 } else { 490 return fault; 491 } 492 } 493 494 /* 495 * Set up for accessing the second cache line. 496 */ 497 498 //Move the pointer we're reading into to the correct location. 499 data += size; 500 //Adjust the size to get the remaining bytes. 501 size = addr + fullSize - secondAddr; 502 //And access the right address. 503 addr = secondAddr; 504 } 505} 506 507 508void 509AtomicSimpleCPU::tick() 510{ 511 DPRINTF(SimpleCPU, "Tick\n"); 512 513 Tick latency = 0; 514 515 for (int i = 0; i < width || locked; ++i) { 516 numCycles++; 517 ppCycles->notify(1); 518 519 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 520 checkForInterrupts(); 521 checkPcEventQueue(); 522 } 523 524 // We must have just got suspended by a PC event 525 if (_status == Idle) { 526 tryCompleteDrain(); 527 return; 528 } 529 530 Fault fault = NoFault; 531 532 TheISA::PCState pcState = thread->pcState(); 533 534 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 535 !curMacroStaticInst; 536 if (needToFetch) { 537 ifetch_req.taskId(taskId()); 538 setupFetchRequest(&ifetch_req); 539 fault = thread->itb->translateAtomic(&ifetch_req, tc, 540 BaseTLB::Execute); 541 } 542 543 if (fault == NoFault) { 544 Tick icache_latency = 0; 545 bool icache_access = false; 546 dcache_access = false; // assume no dcache access 547 548 if (needToFetch) { 549 // This is commented out because the decoder would act like 550 // a tiny cache otherwise. It wouldn't be flushed when needed 551 // like the I cache. It should be flushed, and when that works 552 // this code should be uncommented. 553 //Fetch more instruction memory if necessary 554 //if(decoder.needMoreBytes()) 555 //{ 556 icache_access = true; 557 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 558 ifetch_pkt.dataStatic(&inst); 559 560 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 561 system->getPhysMem().access(&ifetch_pkt); 562 else 563 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 564 565 assert(!ifetch_pkt.isError()); 566 567 // ifetch_req is initialized to read the instruction directly 568 // into the CPU object's inst field. 569 //} 570 } 571 572 preExecute(); 573 574 if (curStaticInst) { 575 fault = curStaticInst->execute(this, traceData); 576 577 // keep an instruction count 578 if (fault == NoFault) { 579 countInst(); 580 ppCommit->notify(std::make_pair(thread, curStaticInst)); 581 } 582 else if (traceData && !DTRACE(ExecFaulting)) { 583 delete traceData; 584 traceData = NULL; 585 } 586 587 postExecute(); 588 } 589 590 // @todo remove me after debugging with legion done 591 if (curStaticInst && (!curStaticInst->isMicroop() || 592 curStaticInst->isFirstMicroop())) 593 instCnt++; 594 595 Tick stall_ticks = 0; 596 if (simulate_inst_stalls && icache_access) 597 stall_ticks += icache_latency; 598 599 if (simulate_data_stalls && dcache_access) 600 stall_ticks += dcache_latency; 601 602 if (stall_ticks) { 603 // the atomic cpu does its accounting in ticks, so 604 // keep counting in ticks but round to the clock 605 // period 606 latency += divCeil(stall_ticks, clockPeriod()) * 607 clockPeriod(); 608 } 609 610 } 611 if(fault != NoFault || !stayAtPC) 612 advancePC(fault); 613 } 614 615 if (tryCompleteDrain()) 616 return; 617 618 // instruction takes at least one cycle 619 if (latency < clockPeriod()) 620 latency = clockPeriod(); 621 622 if (_status != Idle) 623 schedule(tickEvent, curTick() + latency); 624} 625 626void 627AtomicSimpleCPU::regProbePoints() 628{ 629 BaseCPU::regProbePoints(); 630 631 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 632 (getProbeManager(), "Commit"); 633} 634 635void 636AtomicSimpleCPU::printAddr(Addr a) 637{ 638 dcachePort.printAddr(a); 639} 640 641//////////////////////////////////////////////////////////////////////// 642// 643// AtomicSimpleCPU Simulation Object 644// 645AtomicSimpleCPU * 646AtomicSimpleCPUParams::create() 647{ 648 numThreads = 1; 649 if (!FullSystem && workload.size() != 1) 650 panic("only one workload allowed"); 651 return new AtomicSimpleCPU(this); 652} 653