atomic.cc revision 10342
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "base/output.hh"
48#include "config/the_isa.hh"
49#include "cpu/simple/atomic.hh"
50#include "cpu/exetrace.hh"
51#include "debug/Drain.hh"
52#include "debug/ExecFaulting.hh"
53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "mem/physical.hh"
57#include "params/AtomicSimpleCPU.hh"
58#include "sim/faults.hh"
59#include "sim/system.hh"
60#include "sim/full_system.hh"
61
62using namespace std;
63using namespace TheISA;
64
65AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
66    : Event(CPU_Tick_Pri), cpu(c)
67{
68}
69
70
71void
72AtomicSimpleCPU::TickEvent::process()
73{
74    cpu->tick();
75}
76
77const char *
78AtomicSimpleCPU::TickEvent::description() const
79{
80    return "AtomicSimpleCPU tick";
81}
82
83void
84AtomicSimpleCPU::init()
85{
86    BaseCPU::init();
87
88    // Initialise the ThreadContext's memory proxies
89    tcBase()->initMemProxies(tcBase());
90
91    if (FullSystem && !params()->switched_out) {
92        ThreadID size = threadContexts.size();
93        for (ThreadID i = 0; i < size; ++i) {
94            ThreadContext *tc = threadContexts[i];
95            // initialize CPU, including PC
96            TheISA::initCPU(tc, tc->contextId());
97        }
98    }
99
100    // Atomic doesn't do MT right now, so contextId == threadId
101    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
102    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
103    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
104}
105
106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
107    : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
108      simulate_data_stalls(p->simulate_data_stalls),
109      simulate_inst_stalls(p->simulate_inst_stalls),
110      drain_manager(NULL),
111      icachePort(name() + ".icache_port", this),
112      dcachePort(name() + ".dcache_port", this),
113      fastmem(p->fastmem),
114      simpoint(p->simpoint_profile),
115      intervalSize(p->simpoint_interval),
116      intervalCount(0),
117      intervalDrift(0),
118      simpointStream(NULL),
119      currentBBV(0, 0),
120      currentBBVInstCount(0)
121{
122    _status = Idle;
123
124    if (simpoint) {
125        simpointStream = simout.create(p->simpoint_profile_file, false);
126    }
127}
128
129
130AtomicSimpleCPU::~AtomicSimpleCPU()
131{
132    if (tickEvent.scheduled()) {
133        deschedule(tickEvent);
134    }
135    if (simpointStream) {
136        simout.close(simpointStream);
137    }
138}
139
140unsigned int
141AtomicSimpleCPU::drain(DrainManager *dm)
142{
143    assert(!drain_manager);
144    if (switchedOut())
145        return 0;
146
147    if (!isDrained()) {
148        DPRINTF(Drain, "Requesting drain: %s\n", pcState());
149        drain_manager = dm;
150        return 1;
151    } else {
152        if (tickEvent.scheduled())
153            deschedule(tickEvent);
154
155        DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
156        return 0;
157    }
158}
159
160void
161AtomicSimpleCPU::drainResume()
162{
163    assert(!tickEvent.scheduled());
164    assert(!drain_manager);
165    if (switchedOut())
166        return;
167
168    DPRINTF(SimpleCPU, "Resume\n");
169    verifyMemoryMode();
170
171    assert(!threadContexts.empty());
172    if (threadContexts.size() > 1)
173        fatal("The atomic CPU only supports one thread.\n");
174
175    if (thread->status() == ThreadContext::Active) {
176        schedule(tickEvent, nextCycle());
177        _status = BaseSimpleCPU::Running;
178        notIdleFraction = 1;
179    } else {
180        _status = BaseSimpleCPU::Idle;
181        notIdleFraction = 0;
182    }
183
184    system->totalNumInsts = 0;
185}
186
187bool
188AtomicSimpleCPU::tryCompleteDrain()
189{
190    if (!drain_manager)
191        return false;
192
193    DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState());
194    if (!isDrained())
195        return false;
196
197    DPRINTF(Drain, "CPU done draining, processing drain event\n");
198    drain_manager->signalDrainDone();
199    drain_manager = NULL;
200
201    return true;
202}
203
204
205void
206AtomicSimpleCPU::switchOut()
207{
208    BaseSimpleCPU::switchOut();
209
210    assert(!tickEvent.scheduled());
211    assert(_status == BaseSimpleCPU::Running || _status == Idle);
212    assert(isDrained());
213}
214
215
216void
217AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
218{
219    BaseSimpleCPU::takeOverFrom(oldCPU);
220
221    // The tick event should have been descheduled by drain()
222    assert(!tickEvent.scheduled());
223
224    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
225    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
226    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
227}
228
229void
230AtomicSimpleCPU::verifyMemoryMode() const
231{
232    if (!system->isAtomicMode()) {
233        fatal("The atomic CPU requires the memory system to be in "
234              "'atomic' mode.\n");
235    }
236}
237
238void
239AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
240{
241    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
242
243    assert(thread_num == 0);
244    assert(thread);
245
246    assert(_status == Idle);
247    assert(!tickEvent.scheduled());
248
249    notIdleFraction = 1;
250    numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
251
252    //Make sure ticks are still on multiples of cycles
253    schedule(tickEvent, clockEdge(delay));
254    _status = BaseSimpleCPU::Running;
255}
256
257
258void
259AtomicSimpleCPU::suspendContext(ThreadID thread_num)
260{
261    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
262
263    assert(thread_num == 0);
264    assert(thread);
265
266    if (_status == Idle)
267        return;
268
269    assert(_status == BaseSimpleCPU::Running);
270
271    // tick event may not be scheduled if this gets called from inside
272    // an instruction's execution, e.g. "quiesce"
273    if (tickEvent.scheduled())
274        deschedule(tickEvent);
275
276    notIdleFraction = 0;
277    _status = Idle;
278}
279
280
281Tick
282AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
283{
284    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
285            pkt->cmdString());
286
287    // if snoop invalidates, release any associated locks
288    if (pkt->isInvalidate()) {
289        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
290                pkt->getAddr());
291        TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
292    }
293
294    return 0;
295}
296
297void
298AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
299{
300    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
301            pkt->cmdString());
302
303    // if snoop invalidates, release any associated locks
304    if (pkt->isInvalidate()) {
305        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
306                pkt->getAddr());
307        TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
308    }
309}
310
311Fault
312AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
313                         unsigned size, unsigned flags)
314{
315    // use the CPU's statically allocated read request and packet objects
316    Request *req = &data_read_req;
317
318    if (traceData) {
319        traceData->setAddr(addr);
320    }
321
322    //The size of the data we're trying to read.
323    int fullSize = size;
324
325    //The address of the second part of this access if it needs to be split
326    //across a cache line boundary.
327    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
328
329    if (secondAddr > addr)
330        size = secondAddr - addr;
331
332    dcache_latency = 0;
333
334    req->taskId(taskId());
335    while (1) {
336        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
337
338        // translate to physical address
339        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
340
341        // Now do the access.
342        if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
343            Packet pkt(req, MemCmd::ReadReq);
344            pkt.refineCommand();
345            pkt.dataStatic(data);
346
347            if (req->isMmappedIpr())
348                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
349            else {
350                if (fastmem && system->isMemAddr(pkt.getAddr()))
351                    system->getPhysMem().access(&pkt);
352                else
353                    dcache_latency += dcachePort.sendAtomic(&pkt);
354            }
355            dcache_access = true;
356
357            assert(!pkt.isError());
358
359            if (req->isLLSC()) {
360                TheISA::handleLockedRead(thread, req);
361            }
362        }
363
364        //If there's a fault, return it
365        if (fault != NoFault) {
366            if (req->isPrefetch()) {
367                return NoFault;
368            } else {
369                return fault;
370            }
371        }
372
373        //If we don't need to access a second cache line, stop now.
374        if (secondAddr <= addr)
375        {
376            if (req->isLocked() && fault == NoFault) {
377                assert(!locked);
378                locked = true;
379            }
380            return fault;
381        }
382
383        /*
384         * Set up for accessing the second cache line.
385         */
386
387        //Move the pointer we're reading into to the correct location.
388        data += size;
389        //Adjust the size to get the remaining bytes.
390        size = addr + fullSize - secondAddr;
391        //And access the right address.
392        addr = secondAddr;
393    }
394}
395
396
397Fault
398AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
399                          Addr addr, unsigned flags, uint64_t *res)
400{
401
402    static uint8_t zero_array[64] = {};
403
404    if (data == NULL) {
405        assert(size <= 64);
406        assert(flags & Request::CACHE_BLOCK_ZERO);
407        // This must be a cache block cleaning request
408        data = zero_array;
409    }
410
411    // use the CPU's statically allocated write request and packet objects
412    Request *req = &data_write_req;
413
414    if (traceData) {
415        traceData->setAddr(addr);
416    }
417
418    //The size of the data we're trying to read.
419    int fullSize = size;
420
421    //The address of the second part of this access if it needs to be split
422    //across a cache line boundary.
423    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
424
425    if(secondAddr > addr)
426        size = secondAddr - addr;
427
428    dcache_latency = 0;
429
430    req->taskId(taskId());
431    while(1) {
432        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
433
434        // translate to physical address
435        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
436
437        // Now do the access.
438        if (fault == NoFault) {
439            MemCmd cmd = MemCmd::WriteReq; // default
440            bool do_access = true;  // flag to suppress cache access
441
442            if (req->isLLSC()) {
443                cmd = MemCmd::StoreCondReq;
444                do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
445            } else if (req->isSwap()) {
446                cmd = MemCmd::SwapReq;
447                if (req->isCondSwap()) {
448                    assert(res);
449                    req->setExtraData(*res);
450                }
451            }
452
453            if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
454                Packet pkt = Packet(req, cmd);
455                pkt.dataStatic(data);
456
457                if (req->isMmappedIpr()) {
458                    dcache_latency +=
459                        TheISA::handleIprWrite(thread->getTC(), &pkt);
460                } else {
461                    if (fastmem && system->isMemAddr(pkt.getAddr()))
462                        system->getPhysMem().access(&pkt);
463                    else
464                        dcache_latency += dcachePort.sendAtomic(&pkt);
465                }
466                dcache_access = true;
467                assert(!pkt.isError());
468
469                if (req->isSwap()) {
470                    assert(res);
471                    memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
472                }
473            }
474
475            if (res && !req->isSwap()) {
476                *res = req->getExtraData();
477            }
478        }
479
480        //If there's a fault or we don't need to access a second cache line,
481        //stop now.
482        if (fault != NoFault || secondAddr <= addr)
483        {
484            if (req->isLocked() && fault == NoFault) {
485                assert(locked);
486                locked = false;
487            }
488            if (fault != NoFault && req->isPrefetch()) {
489                return NoFault;
490            } else {
491                return fault;
492            }
493        }
494
495        /*
496         * Set up for accessing the second cache line.
497         */
498
499        //Move the pointer we're reading into to the correct location.
500        data += size;
501        //Adjust the size to get the remaining bytes.
502        size = addr + fullSize - secondAddr;
503        //And access the right address.
504        addr = secondAddr;
505    }
506}
507
508
509void
510AtomicSimpleCPU::tick()
511{
512    DPRINTF(SimpleCPU, "Tick\n");
513
514    Tick latency = 0;
515
516    for (int i = 0; i < width || locked; ++i) {
517        numCycles++;
518
519        if (!curStaticInst || !curStaticInst->isDelayedCommit())
520            checkForInterrupts();
521
522        checkPcEventQueue();
523        // We must have just got suspended by a PC event
524        if (_status == Idle) {
525            tryCompleteDrain();
526            return;
527        }
528
529        Fault fault = NoFault;
530
531        TheISA::PCState pcState = thread->pcState();
532
533        bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
534                           !curMacroStaticInst;
535        if (needToFetch) {
536            ifetch_req.taskId(taskId());
537            setupFetchRequest(&ifetch_req);
538            fault = thread->itb->translateAtomic(&ifetch_req, tc,
539                                                 BaseTLB::Execute);
540        }
541
542        if (fault == NoFault) {
543            Tick icache_latency = 0;
544            bool icache_access = false;
545            dcache_access = false; // assume no dcache access
546
547            if (needToFetch) {
548                // This is commented out because the decoder would act like
549                // a tiny cache otherwise. It wouldn't be flushed when needed
550                // like the I cache. It should be flushed, and when that works
551                // this code should be uncommented.
552                //Fetch more instruction memory if necessary
553                //if(decoder.needMoreBytes())
554                //{
555                    icache_access = true;
556                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
557                    ifetch_pkt.dataStatic(&inst);
558
559                    if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
560                        system->getPhysMem().access(&ifetch_pkt);
561                    else
562                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
563
564                    assert(!ifetch_pkt.isError());
565
566                    // ifetch_req is initialized to read the instruction directly
567                    // into the CPU object's inst field.
568                //}
569            }
570
571            preExecute();
572
573            if (curStaticInst) {
574                fault = curStaticInst->execute(this, traceData);
575
576                // keep an instruction count
577                if (fault == NoFault)
578                    countInst();
579                else if (traceData && !DTRACE(ExecFaulting)) {
580                    delete traceData;
581                    traceData = NULL;
582                }
583
584                postExecute();
585            }
586
587            // @todo remove me after debugging with legion done
588            if (curStaticInst && (!curStaticInst->isMicroop() ||
589                        curStaticInst->isFirstMicroop()))
590                instCnt++;
591
592            // profile for SimPoints if enabled and macro inst is finished
593            if (simpoint && curStaticInst && (fault == NoFault) &&
594                    (!curStaticInst->isMicroop() ||
595                     curStaticInst->isLastMicroop())) {
596                profileSimPoint();
597            }
598
599            Tick stall_ticks = 0;
600            if (simulate_inst_stalls && icache_access)
601                stall_ticks += icache_latency;
602
603            if (simulate_data_stalls && dcache_access)
604                stall_ticks += dcache_latency;
605
606            if (stall_ticks) {
607                // the atomic cpu does its accounting in ticks, so
608                // keep counting in ticks but round to the clock
609                // period
610                latency += divCeil(stall_ticks, clockPeriod()) *
611                    clockPeriod();
612            }
613
614        }
615        if(fault != NoFault || !stayAtPC)
616            advancePC(fault);
617    }
618
619    if (tryCompleteDrain())
620        return;
621
622    // instruction takes at least one cycle
623    if (latency < clockPeriod())
624        latency = clockPeriod();
625
626    if (_status != Idle)
627        schedule(tickEvent, curTick() + latency);
628}
629
630
631void
632AtomicSimpleCPU::printAddr(Addr a)
633{
634    dcachePort.printAddr(a);
635}
636
637void
638AtomicSimpleCPU::profileSimPoint()
639{
640    if (!currentBBVInstCount)
641        currentBBV.first = thread->pcState().instAddr();
642
643    ++intervalCount;
644    ++currentBBVInstCount;
645
646    // If inst is control inst, assume end of basic block.
647    if (curStaticInst->isControl()) {
648        currentBBV.second = thread->pcState().instAddr();
649
650        auto map_itr = bbMap.find(currentBBV);
651        if (map_itr == bbMap.end()){
652            // If a new (previously unseen) basic block is found,
653            // add a new unique id, record num of insts and insert into bbMap.
654            BBInfo info;
655            info.id = bbMap.size() + 1;
656            info.insts = currentBBVInstCount;
657            info.count = currentBBVInstCount;
658            bbMap.insert(std::make_pair(currentBBV, info));
659        } else {
660            // If basic block is seen before, just increment the count by the
661            // number of insts in basic block.
662            BBInfo& info = map_itr->second;
663            info.count += currentBBVInstCount;
664        }
665        currentBBVInstCount = 0;
666
667        // Reached end of interval if the sum of the current inst count
668        // (intervalCount) and the excessive inst count from the previous
669        // interval (intervalDrift) is greater than/equal to the interval size.
670        if (intervalCount + intervalDrift >= intervalSize) {
671            // summarize interval and display BBV info
672            std::vector<pair<uint64_t, uint64_t> > counts;
673            for (auto map_itr = bbMap.begin(); map_itr != bbMap.end();
674                    ++map_itr) {
675                BBInfo& info = map_itr->second;
676                if (info.count != 0) {
677                    counts.push_back(std::make_pair(info.id, info.count));
678                    info.count = 0;
679                }
680            }
681            std::sort(counts.begin(), counts.end());
682
683            // Print output BBV info
684            *simpointStream << "T";
685            for (auto cnt_itr = counts.begin(); cnt_itr != counts.end();
686                    ++cnt_itr) {
687                *simpointStream << ":" << cnt_itr->first
688                                << ":" << cnt_itr->second << " ";
689            }
690            *simpointStream << "\n";
691
692            intervalDrift = (intervalCount + intervalDrift) - intervalSize;
693            intervalCount = 0;
694        }
695    }
696}
697
698////////////////////////////////////////////////////////////////////////
699//
700//  AtomicSimpleCPU Simulation Object
701//
702AtomicSimpleCPU *
703AtomicSimpleCPUParams::create()
704{
705    numThreads = 1;
706    if (!FullSystem && workload.size() != 1)
707        panic("only one workload allowed");
708    return new AtomicSimpleCPU(this);
709}
710