atomic.cc revision 9524
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/atomic.hh" 492623SN/A#include "cpu/exetrace.hh" 509443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 518232Snate@binkert.org#include "debug/ExecFaulting.hh" 528232Snate@binkert.org#include "debug/SimpleCPU.hh" 533348Sbinkertn@umich.edu#include "mem/packet.hh" 543348Sbinkertn@umich.edu#include "mem/packet_access.hh" 558926Sandreas.hansson@arm.com#include "mem/physical.hh" 564762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 577678Sgblack@eecs.umich.edu#include "sim/faults.hh" 582901Ssaidi@eecs.umich.edu#include "sim/system.hh" 598779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 602623SN/A 612623SN/Ausing namespace std; 622623SN/Ausing namespace TheISA; 632623SN/A 642623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 655606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 662623SN/A{ 672623SN/A} 682623SN/A 692623SN/A 702623SN/Avoid 712623SN/AAtomicSimpleCPU::TickEvent::process() 722623SN/A{ 732623SN/A cpu->tick(); 742623SN/A} 752623SN/A 762623SN/Aconst char * 775336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 782623SN/A{ 794873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 802623SN/A} 812623SN/A 822623SN/Avoid 832623SN/AAtomicSimpleCPU::init() 842623SN/A{ 852623SN/A BaseCPU::init(); 868921Sandreas.hansson@arm.com 878921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 888921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 898921Sandreas.hansson@arm.com 909433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 918779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 928779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 938779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 948779Sgblack@eecs.umich.edu // initialize CPU, including PC 958779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 968779Sgblack@eecs.umich.edu } 972623SN/A } 988706Sandreas.hansson@arm.com 995714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1005712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1015712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1025712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1032623SN/A} 1042623SN/A 1055529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1066078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1075487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1085487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1099443SAndreas.Sandberg@ARM.com drain_manager(NULL), 1109095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1119095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 1128926Sandreas.hansson@arm.com fastmem(p->fastmem) 1132623SN/A{ 1142623SN/A _status = Idle; 1152623SN/A} 1162623SN/A 1172623SN/A 1182623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1192623SN/A{ 1206775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1216775SBrad.Beckmann@amd.com deschedule(tickEvent); 1226775SBrad.Beckmann@amd.com } 1232623SN/A} 1242623SN/A 1259443SAndreas.Sandberg@ARM.comunsigned int 1269443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::drain(DrainManager *dm) 1272623SN/A{ 1289443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1299448SAndreas.Sandberg@ARM.com if (switchedOut()) 1309443SAndreas.Sandberg@ARM.com return 0; 1312623SN/A 1329443SAndreas.Sandberg@ARM.com if (!isDrained()) { 1339443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1349443SAndreas.Sandberg@ARM.com drain_manager = dm; 1359443SAndreas.Sandberg@ARM.com return 1; 1369443SAndreas.Sandberg@ARM.com } else { 1379443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1389443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1392915Sktlim@umich.edu 1409443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 1419443SAndreas.Sandberg@ARM.com return 0; 1429443SAndreas.Sandberg@ARM.com } 1439342SAndreas.Sandberg@arm.com} 1449342SAndreas.Sandberg@arm.com 1452915Sktlim@umich.eduvoid 1469342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1472915Sktlim@umich.edu{ 1489448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1499443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1509448SAndreas.Sandberg@ARM.com if (switchedOut()) 1515220Ssaidi@eecs.umich.edu return; 1525220Ssaidi@eecs.umich.edu 1534940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1549523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1553324Shsul@eecs.umich.edu 1569448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1579448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1589448SAndreas.Sandberg@ARM.com fatal("The atomic CPU only supports one thread.\n"); 1599448SAndreas.Sandberg@ARM.com 1609448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1619443SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 1629448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1639448SAndreas.Sandberg@ARM.com } else { 1649448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1659448SAndreas.Sandberg@ARM.com } 1669443SAndreas.Sandberg@ARM.com 1677897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1682623SN/A} 1692623SN/A 1709443SAndreas.Sandberg@ARM.combool 1719443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1729443SAndreas.Sandberg@ARM.com{ 1739443SAndreas.Sandberg@ARM.com if (!drain_manager) 1749443SAndreas.Sandberg@ARM.com return false; 1759443SAndreas.Sandberg@ARM.com 1769443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1779443SAndreas.Sandberg@ARM.com if (!isDrained()) 1789443SAndreas.Sandberg@ARM.com return false; 1799443SAndreas.Sandberg@ARM.com 1809443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1819443SAndreas.Sandberg@ARM.com drain_manager->signalDrainDone(); 1829443SAndreas.Sandberg@ARM.com drain_manager = NULL; 1839443SAndreas.Sandberg@ARM.com 1849443SAndreas.Sandberg@ARM.com return true; 1859443SAndreas.Sandberg@ARM.com} 1869443SAndreas.Sandberg@ARM.com 1879443SAndreas.Sandberg@ARM.com 1882623SN/Avoid 1892798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1902623SN/A{ 1919429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1929429SAndreas.Sandberg@ARM.com 1939443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1949342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1959443SAndreas.Sandberg@ARM.com assert(isDrained()); 1962623SN/A} 1972623SN/A 1982623SN/A 1992623SN/Avoid 2002623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2012623SN/A{ 2029429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2032623SN/A 2049443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2052623SN/A assert(!tickEvent.scheduled()); 2062623SN/A 2075712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2085712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2095712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2102623SN/A} 2112623SN/A 2129523SAndreas.Sandberg@ARM.comvoid 2139523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2149523SAndreas.Sandberg@ARM.com{ 2159524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2169523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2179523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2189523SAndreas.Sandberg@ARM.com } 2199523SAndreas.Sandberg@ARM.com} 2202623SN/A 2212623SN/Avoid 2229180Sandreas.hansson@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2232623SN/A{ 2244940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2254940Snate@binkert.org 2262623SN/A assert(thread_num == 0); 2272683Sktlim@umich.edu assert(thread); 2282623SN/A 2292623SN/A assert(_status == Idle); 2302623SN/A assert(!tickEvent.scheduled()); 2312623SN/A 2322623SN/A notIdleFraction++; 2339180Sandreas.hansson@arm.com numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend); 2343686Sktlim@umich.edu 2353430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2369179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2379342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2382623SN/A} 2392623SN/A 2402623SN/A 2412623SN/Avoid 2428737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2432623SN/A{ 2444940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2454940Snate@binkert.org 2462623SN/A assert(thread_num == 0); 2472683Sktlim@umich.edu assert(thread); 2482623SN/A 2496043Sgblack@eecs.umich.edu if (_status == Idle) 2506043Sgblack@eecs.umich.edu return; 2516043Sgblack@eecs.umich.edu 2529342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2532626SN/A 2542626SN/A // tick event may not be scheduled if this gets called from inside 2552626SN/A // an instruction's execution, e.g. "quiesce" 2562626SN/A if (tickEvent.scheduled()) 2575606Snate@binkert.org deschedule(tickEvent); 2582623SN/A 2592623SN/A notIdleFraction--; 2602623SN/A _status = Idle; 2612623SN/A} 2622623SN/A 2632623SN/A 2642623SN/AFault 2658444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2668444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 2672623SN/A{ 2683169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2694870Sstever@eecs.umich.edu Request *req = &data_read_req; 2702623SN/A 2712623SN/A if (traceData) { 2722623SN/A traceData->setAddr(addr); 2732623SN/A } 2742623SN/A 2754999Sgblack@eecs.umich.edu //The block size of our peer. 2766227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 2774999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 2787520Sgblack@eecs.umich.edu int fullSize = size; 2792623SN/A 2804999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 2814999Sgblack@eecs.umich.edu //across a cache line boundary. 2827520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 2834999Sgblack@eecs.umich.edu 2847520Sgblack@eecs.umich.edu if (secondAddr > addr) 2857520Sgblack@eecs.umich.edu size = secondAddr - addr; 2864999Sgblack@eecs.umich.edu 2874999Sgblack@eecs.umich.edu dcache_latency = 0; 2884999Sgblack@eecs.umich.edu 2897520Sgblack@eecs.umich.edu while (1) { 2908832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 2914999Sgblack@eecs.umich.edu 2924999Sgblack@eecs.umich.edu // translate to physical address 2936023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 2944999Sgblack@eecs.umich.edu 2954999Sgblack@eecs.umich.edu // Now do the access. 2966623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 2974999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 2988949Sandreas.hansson@arm.com req->isLLSC() ? MemCmd::LoadLockedReq : 2998949Sandreas.hansson@arm.com MemCmd::ReadReq); 3007520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3014999Sgblack@eecs.umich.edu 3028105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3034999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3044999Sgblack@eecs.umich.edu else { 3058931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3068931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3074999Sgblack@eecs.umich.edu else 3084999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3094999Sgblack@eecs.umich.edu } 3104999Sgblack@eecs.umich.edu dcache_access = true; 3115012Sgblack@eecs.umich.edu 3124999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3134999Sgblack@eecs.umich.edu 3146102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3154999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3164999Sgblack@eecs.umich.edu } 3174968Sacolyte@umich.edu } 3184986Ssaidi@eecs.umich.edu 3194999Sgblack@eecs.umich.edu //If there's a fault, return it 3206739Sgblack@eecs.umich.edu if (fault != NoFault) { 3216739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3226739Sgblack@eecs.umich.edu return NoFault; 3236739Sgblack@eecs.umich.edu } else { 3246739Sgblack@eecs.umich.edu return fault; 3256739Sgblack@eecs.umich.edu } 3266739Sgblack@eecs.umich.edu } 3276739Sgblack@eecs.umich.edu 3284999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3294999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3304999Sgblack@eecs.umich.edu { 3316078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3326078Sgblack@eecs.umich.edu assert(!locked); 3336078Sgblack@eecs.umich.edu locked = true; 3346078Sgblack@eecs.umich.edu } 3354999Sgblack@eecs.umich.edu return fault; 3364968Sacolyte@umich.edu } 3373170Sstever@eecs.umich.edu 3384999Sgblack@eecs.umich.edu /* 3394999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3404999Sgblack@eecs.umich.edu */ 3414999Sgblack@eecs.umich.edu 3424999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3437520Sgblack@eecs.umich.edu data += size; 3444999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3457520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3464999Sgblack@eecs.umich.edu //And access the right address. 3474999Sgblack@eecs.umich.edu addr = secondAddr; 3482623SN/A } 3492623SN/A} 3502623SN/A 3517520Sgblack@eecs.umich.edu 3522623SN/AFault 3538444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3548444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3552623SN/A{ 3563169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3574870Sstever@eecs.umich.edu Request *req = &data_write_req; 3582623SN/A 3592623SN/A if (traceData) { 3602623SN/A traceData->setAddr(addr); 3612623SN/A } 3622623SN/A 3634999Sgblack@eecs.umich.edu //The block size of our peer. 3646227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3654999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3667520Sgblack@eecs.umich.edu int fullSize = size; 3672623SN/A 3684999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3694999Sgblack@eecs.umich.edu //across a cache line boundary. 3707520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3714999Sgblack@eecs.umich.edu 3724999Sgblack@eecs.umich.edu if(secondAddr > addr) 3737520Sgblack@eecs.umich.edu size = secondAddr - addr; 3744999Sgblack@eecs.umich.edu 3754999Sgblack@eecs.umich.edu dcache_latency = 0; 3764999Sgblack@eecs.umich.edu 3774999Sgblack@eecs.umich.edu while(1) { 3788832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3794999Sgblack@eecs.umich.edu 3804999Sgblack@eecs.umich.edu // translate to physical address 3816023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 3824999Sgblack@eecs.umich.edu 3834999Sgblack@eecs.umich.edu // Now do the access. 3844999Sgblack@eecs.umich.edu if (fault == NoFault) { 3854999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3864999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3874999Sgblack@eecs.umich.edu 3886102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3894999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3904999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3914999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3924999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3934999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 3944999Sgblack@eecs.umich.edu assert(res); 3954999Sgblack@eecs.umich.edu req->setExtraData(*res); 3964999Sgblack@eecs.umich.edu } 3974999Sgblack@eecs.umich.edu } 3984999Sgblack@eecs.umich.edu 3996623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4008949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4017520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4024999Sgblack@eecs.umich.edu 4038105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4044999Sgblack@eecs.umich.edu dcache_latency += 4054999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4064999Sgblack@eecs.umich.edu } else { 4078931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4088931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4094999Sgblack@eecs.umich.edu else 4104999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4114999Sgblack@eecs.umich.edu } 4124999Sgblack@eecs.umich.edu dcache_access = true; 4134999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4144999Sgblack@eecs.umich.edu 4154999Sgblack@eecs.umich.edu if (req->isSwap()) { 4164999Sgblack@eecs.umich.edu assert(res); 4177520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 4184999Sgblack@eecs.umich.edu } 4194999Sgblack@eecs.umich.edu } 4204999Sgblack@eecs.umich.edu 4214999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4224999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4234878Sstever@eecs.umich.edu } 4244040Ssaidi@eecs.umich.edu } 4254040Ssaidi@eecs.umich.edu 4264999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4274999Sgblack@eecs.umich.edu //stop now. 4284999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4294999Sgblack@eecs.umich.edu { 4306078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4316078Sgblack@eecs.umich.edu assert(locked); 4326078Sgblack@eecs.umich.edu locked = false; 4336078Sgblack@eecs.umich.edu } 4346739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4356739Sgblack@eecs.umich.edu return NoFault; 4366739Sgblack@eecs.umich.edu } else { 4376739Sgblack@eecs.umich.edu return fault; 4386739Sgblack@eecs.umich.edu } 4393170Sstever@eecs.umich.edu } 4403170Sstever@eecs.umich.edu 4414999Sgblack@eecs.umich.edu /* 4424999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4434999Sgblack@eecs.umich.edu */ 4444999Sgblack@eecs.umich.edu 4454999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4467520Sgblack@eecs.umich.edu data += size; 4474999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4487520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4494999Sgblack@eecs.umich.edu //And access the right address. 4504999Sgblack@eecs.umich.edu addr = secondAddr; 4512623SN/A } 4522623SN/A} 4532623SN/A 4542623SN/A 4552623SN/Avoid 4562623SN/AAtomicSimpleCPU::tick() 4572623SN/A{ 4584940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4594940Snate@binkert.org 4605487Snate@binkert.org Tick latency = 0; 4612623SN/A 4626078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 4632623SN/A numCycles++; 4642623SN/A 4653387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4663387Sgblack@eecs.umich.edu checkForInterrupts(); 4672626SN/A 4685348Ssaidi@eecs.umich.edu checkPcEventQueue(); 4698143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 4709443SAndreas.Sandberg@ARM.com if (_status == Idle) { 4719443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 4728143SAli.Saidi@ARM.com return; 4739443SAndreas.Sandberg@ARM.com } 4745348Ssaidi@eecs.umich.edu 4755669Sgblack@eecs.umich.edu Fault fault = NoFault; 4765669Sgblack@eecs.umich.edu 4777720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4787720Sgblack@eecs.umich.edu 4797720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 4807720Sgblack@eecs.umich.edu !curMacroStaticInst; 4817720Sgblack@eecs.umich.edu if (needToFetch) { 4825894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 4836023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 4846023Snate@binkert.org BaseTLB::Execute); 4855894Sgblack@eecs.umich.edu } 4862623SN/A 4872623SN/A if (fault == NoFault) { 4884182Sgblack@eecs.umich.edu Tick icache_latency = 0; 4894182Sgblack@eecs.umich.edu bool icache_access = false; 4904182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 4912662Sstever@eecs.umich.edu 4927720Sgblack@eecs.umich.edu if (needToFetch) { 4939023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 4945694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 4955694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 4965694Sgblack@eecs.umich.edu // this code should be uncommented. 4975669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 4989023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 4995669Sgblack@eecs.umich.edu //{ 5005669Sgblack@eecs.umich.edu icache_access = true; 5018949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 5025669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5032623SN/A 5048931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5058931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5065669Sgblack@eecs.umich.edu else 5075669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5084968Sacolyte@umich.edu 5095669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5104968Sacolyte@umich.edu 5115669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5125669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5135669Sgblack@eecs.umich.edu //} 5145669Sgblack@eecs.umich.edu } 5154182Sgblack@eecs.umich.edu 5162623SN/A preExecute(); 5173814Ssaidi@eecs.umich.edu 5185001Sgblack@eecs.umich.edu if (curStaticInst) { 5194182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5204998Sgblack@eecs.umich.edu 5214998Sgblack@eecs.umich.edu // keep an instruction count 5224998Sgblack@eecs.umich.edu if (fault == NoFault) 5234998Sgblack@eecs.umich.edu countInst(); 5247655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5255001Sgblack@eecs.umich.edu delete traceData; 5265001Sgblack@eecs.umich.edu traceData = NULL; 5275001Sgblack@eecs.umich.edu } 5284998Sgblack@eecs.umich.edu 5294182Sgblack@eecs.umich.edu postExecute(); 5304182Sgblack@eecs.umich.edu } 5312623SN/A 5323814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5334539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5344539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5353814Ssaidi@eecs.umich.edu instCnt++; 5363814Ssaidi@eecs.umich.edu 5375487Snate@binkert.org Tick stall_ticks = 0; 5385487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5395487Snate@binkert.org stall_ticks += icache_latency; 5405487Snate@binkert.org 5415487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5425487Snate@binkert.org stall_ticks += dcache_latency; 5435487Snate@binkert.org 5445487Snate@binkert.org if (stall_ticks) { 5459180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 5469180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 5479180Sandreas.hansson@arm.com // period 5489180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 5499180Sandreas.hansson@arm.com clockPeriod(); 5502623SN/A } 5512623SN/A 5522623SN/A } 5534377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5544182Sgblack@eecs.umich.edu advancePC(fault); 5552623SN/A } 5562623SN/A 5579443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 5589443SAndreas.Sandberg@ARM.com return; 5599443SAndreas.Sandberg@ARM.com 5605487Snate@binkert.org // instruction takes at least one cycle 5619179Sandreas.hansson@arm.com if (latency < clockPeriod()) 5629179Sandreas.hansson@arm.com latency = clockPeriod(); 5635487Snate@binkert.org 5642626SN/A if (_status != Idle) 5657823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 5662623SN/A} 5672623SN/A 5682623SN/A 5695315Sstever@gmail.comvoid 5705315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 5715315Sstever@gmail.com{ 5725315Sstever@gmail.com dcachePort.printAddr(a); 5735315Sstever@gmail.com} 5745315Sstever@gmail.com 5755315Sstever@gmail.com 5762623SN/A//////////////////////////////////////////////////////////////////////// 5772623SN/A// 5782623SN/A// AtomicSimpleCPU Simulation Object 5792623SN/A// 5804762Snate@binkert.orgAtomicSimpleCPU * 5814762Snate@binkert.orgAtomicSimpleCPUParams::create() 5822623SN/A{ 5835529Snate@binkert.org numThreads = 1; 5848779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 5854762Snate@binkert.org panic("only one workload allowed"); 5865529Snate@binkert.org return new AtomicSimpleCPU(this); 5872623SN/A} 588