atomic.cc revision 9429
12623SN/A/* 28926Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/simple/atomic.hh" 492623SN/A#include "cpu/exetrace.hh" 508232Snate@binkert.org#include "debug/ExecFaulting.hh" 518232Snate@binkert.org#include "debug/SimpleCPU.hh" 523348Sbinkertn@umich.edu#include "mem/packet.hh" 533348Sbinkertn@umich.edu#include "mem/packet_access.hh" 548926Sandreas.hansson@arm.com#include "mem/physical.hh" 554762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 567678Sgblack@eecs.umich.edu#include "sim/faults.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 588779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 592623SN/A 602623SN/Ausing namespace std; 612623SN/Ausing namespace TheISA; 622623SN/A 632623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 645606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 652623SN/A{ 662623SN/A} 672623SN/A 682623SN/A 692623SN/Avoid 702623SN/AAtomicSimpleCPU::TickEvent::process() 712623SN/A{ 722623SN/A cpu->tick(); 732623SN/A} 742623SN/A 752623SN/Aconst char * 765336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 772623SN/A{ 784873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 792623SN/A} 802623SN/A 812623SN/Avoid 822623SN/AAtomicSimpleCPU::init() 832623SN/A{ 842623SN/A BaseCPU::init(); 858921Sandreas.hansson@arm.com 869424SAndreas.Sandberg@ARM.com if (!params()->defer_registration && 879424SAndreas.Sandberg@ARM.com system->getMemoryMode() != Enums::atomic) { 889424SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 899424SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 909424SAndreas.Sandberg@ARM.com } 919424SAndreas.Sandberg@ARM.com 928921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 938921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 948921Sandreas.hansson@arm.com 959058Satgutier@umich.edu if (FullSystem && !params()->defer_registration) { 968779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 978779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 988779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 998779Sgblack@eecs.umich.edu // initialize CPU, including PC 1008779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 1018779Sgblack@eecs.umich.edu } 1022623SN/A } 1038706Sandreas.hansson@arm.com 1045714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1055712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1065712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1075712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1082623SN/A} 1092623SN/A 1105529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1116078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1125487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1135487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1149095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1159095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 1168926Sandreas.hansson@arm.com fastmem(p->fastmem) 1172623SN/A{ 1182623SN/A _status = Idle; 1192623SN/A} 1202623SN/A 1212623SN/A 1222623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1232623SN/A{ 1246775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1256775SBrad.Beckmann@amd.com deschedule(tickEvent); 1266775SBrad.Beckmann@amd.com } 1272623SN/A} 1282623SN/A 1292623SN/Avoid 1302623SN/AAtomicSimpleCPU::serialize(ostream &os) 1312623SN/A{ 1329342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 1332915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1346078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1353145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1362623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1372623SN/A tickEvent.serialize(os); 1382623SN/A} 1392623SN/A 1402623SN/Avoid 1412623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1422623SN/A{ 1439342SAndreas.Sandberg@arm.com Drainable::State so_state; 1442915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1456078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 1463145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1472915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1482915Sktlim@umich.edu} 1492915Sktlim@umich.edu 1509342SAndreas.Sandberg@arm.comunsigned int 1519342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drain(DrainManager *drain_manager) 1529342SAndreas.Sandberg@arm.com{ 1539342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 1549342SAndreas.Sandberg@arm.com return 0; 1559342SAndreas.Sandberg@arm.com} 1569342SAndreas.Sandberg@arm.com 1572915Sktlim@umich.eduvoid 1589342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1592915Sktlim@umich.edu{ 1605220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1615220Ssaidi@eecs.umich.edu return; 1625220Ssaidi@eecs.umich.edu 1634940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1649424SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::atomic) { 1659424SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 1669424SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 1679424SAndreas.Sandberg@ARM.com } 1683324Shsul@eecs.umich.edu 1699342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 1705220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1715606Snate@binkert.org if (!tickEvent.scheduled()) 1725606Snate@binkert.org schedule(tickEvent, nextCycle()); 1732915Sktlim@umich.edu } 1747897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1752623SN/A} 1762623SN/A 1772623SN/Avoid 1782798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1792623SN/A{ 1809429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1819429SAndreas.Sandberg@ARM.com 1829342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1832798Sktlim@umich.edu _status = SwitchedOut; 1842623SN/A 1852798Sktlim@umich.edu tickEvent.squash(); 1862623SN/A} 1872623SN/A 1882623SN/A 1892623SN/Avoid 1902623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1912623SN/A{ 1929429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 1932623SN/A 1942623SN/A assert(!tickEvent.scheduled()); 1952623SN/A 1962680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1972623SN/A // running and schedule its tick event. 1986221Snate@binkert.org ThreadID size = threadContexts.size(); 1996221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 2002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2019342SAndreas.Sandberg@arm.com if (tc->status() == ThreadContext::Active && 2029342SAndreas.Sandberg@arm.com _status != BaseSimpleCPU::Running) { 2039342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2045606Snate@binkert.org schedule(tickEvent, nextCycle()); 2052623SN/A break; 2062623SN/A } 2072623SN/A } 2089342SAndreas.Sandberg@arm.com if (_status != BaseSimpleCPU::Running) { 2093512Sktlim@umich.edu _status = Idle; 2103512Sktlim@umich.edu } 2115169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2125712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2135712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2145712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2152623SN/A} 2162623SN/A 2172623SN/A 2182623SN/Avoid 2199180Sandreas.hansson@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2202623SN/A{ 2214940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2224940Snate@binkert.org 2232623SN/A assert(thread_num == 0); 2242683Sktlim@umich.edu assert(thread); 2252623SN/A 2262623SN/A assert(_status == Idle); 2272623SN/A assert(!tickEvent.scheduled()); 2282623SN/A 2292623SN/A notIdleFraction++; 2309180Sandreas.hansson@arm.com numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend); 2313686Sktlim@umich.edu 2323430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2339179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2349342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2352623SN/A} 2362623SN/A 2372623SN/A 2382623SN/Avoid 2398737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2402623SN/A{ 2414940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2424940Snate@binkert.org 2432623SN/A assert(thread_num == 0); 2442683Sktlim@umich.edu assert(thread); 2452623SN/A 2466043Sgblack@eecs.umich.edu if (_status == Idle) 2476043Sgblack@eecs.umich.edu return; 2486043Sgblack@eecs.umich.edu 2499342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2502626SN/A 2512626SN/A // tick event may not be scheduled if this gets called from inside 2522626SN/A // an instruction's execution, e.g. "quiesce" 2532626SN/A if (tickEvent.scheduled()) 2545606Snate@binkert.org deschedule(tickEvent); 2552623SN/A 2562623SN/A notIdleFraction--; 2572623SN/A _status = Idle; 2582623SN/A} 2592623SN/A 2602623SN/A 2612623SN/AFault 2628444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2638444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 2642623SN/A{ 2653169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2664870Sstever@eecs.umich.edu Request *req = &data_read_req; 2672623SN/A 2682623SN/A if (traceData) { 2692623SN/A traceData->setAddr(addr); 2702623SN/A } 2712623SN/A 2724999Sgblack@eecs.umich.edu //The block size of our peer. 2736227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 2744999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 2757520Sgblack@eecs.umich.edu int fullSize = size; 2762623SN/A 2774999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 2784999Sgblack@eecs.umich.edu //across a cache line boundary. 2797520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 2804999Sgblack@eecs.umich.edu 2817520Sgblack@eecs.umich.edu if (secondAddr > addr) 2827520Sgblack@eecs.umich.edu size = secondAddr - addr; 2834999Sgblack@eecs.umich.edu 2844999Sgblack@eecs.umich.edu dcache_latency = 0; 2854999Sgblack@eecs.umich.edu 2867520Sgblack@eecs.umich.edu while (1) { 2878832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 2884999Sgblack@eecs.umich.edu 2894999Sgblack@eecs.umich.edu // translate to physical address 2906023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 2914999Sgblack@eecs.umich.edu 2924999Sgblack@eecs.umich.edu // Now do the access. 2936623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 2944999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 2958949Sandreas.hansson@arm.com req->isLLSC() ? MemCmd::LoadLockedReq : 2968949Sandreas.hansson@arm.com MemCmd::ReadReq); 2977520Sgblack@eecs.umich.edu pkt.dataStatic(data); 2984999Sgblack@eecs.umich.edu 2998105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3004999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3014999Sgblack@eecs.umich.edu else { 3028931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3038931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3044999Sgblack@eecs.umich.edu else 3054999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3064999Sgblack@eecs.umich.edu } 3074999Sgblack@eecs.umich.edu dcache_access = true; 3085012Sgblack@eecs.umich.edu 3094999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3104999Sgblack@eecs.umich.edu 3116102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3124999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3134999Sgblack@eecs.umich.edu } 3144968Sacolyte@umich.edu } 3154986Ssaidi@eecs.umich.edu 3164999Sgblack@eecs.umich.edu //If there's a fault, return it 3176739Sgblack@eecs.umich.edu if (fault != NoFault) { 3186739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3196739Sgblack@eecs.umich.edu return NoFault; 3206739Sgblack@eecs.umich.edu } else { 3216739Sgblack@eecs.umich.edu return fault; 3226739Sgblack@eecs.umich.edu } 3236739Sgblack@eecs.umich.edu } 3246739Sgblack@eecs.umich.edu 3254999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3264999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3274999Sgblack@eecs.umich.edu { 3286078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3296078Sgblack@eecs.umich.edu assert(!locked); 3306078Sgblack@eecs.umich.edu locked = true; 3316078Sgblack@eecs.umich.edu } 3324999Sgblack@eecs.umich.edu return fault; 3334968Sacolyte@umich.edu } 3343170Sstever@eecs.umich.edu 3354999Sgblack@eecs.umich.edu /* 3364999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3374999Sgblack@eecs.umich.edu */ 3384999Sgblack@eecs.umich.edu 3394999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3407520Sgblack@eecs.umich.edu data += size; 3414999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3427520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3434999Sgblack@eecs.umich.edu //And access the right address. 3444999Sgblack@eecs.umich.edu addr = secondAddr; 3452623SN/A } 3462623SN/A} 3472623SN/A 3487520Sgblack@eecs.umich.edu 3492623SN/AFault 3508444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3518444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3522623SN/A{ 3533169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3544870Sstever@eecs.umich.edu Request *req = &data_write_req; 3552623SN/A 3562623SN/A if (traceData) { 3572623SN/A traceData->setAddr(addr); 3582623SN/A } 3592623SN/A 3604999Sgblack@eecs.umich.edu //The block size of our peer. 3616227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3624999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3637520Sgblack@eecs.umich.edu int fullSize = size; 3642623SN/A 3654999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3664999Sgblack@eecs.umich.edu //across a cache line boundary. 3677520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3684999Sgblack@eecs.umich.edu 3694999Sgblack@eecs.umich.edu if(secondAddr > addr) 3707520Sgblack@eecs.umich.edu size = secondAddr - addr; 3714999Sgblack@eecs.umich.edu 3724999Sgblack@eecs.umich.edu dcache_latency = 0; 3734999Sgblack@eecs.umich.edu 3744999Sgblack@eecs.umich.edu while(1) { 3758832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3764999Sgblack@eecs.umich.edu 3774999Sgblack@eecs.umich.edu // translate to physical address 3786023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 3794999Sgblack@eecs.umich.edu 3804999Sgblack@eecs.umich.edu // Now do the access. 3814999Sgblack@eecs.umich.edu if (fault == NoFault) { 3824999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3834999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3844999Sgblack@eecs.umich.edu 3856102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3864999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3874999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3884999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3894999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3904999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 3914999Sgblack@eecs.umich.edu assert(res); 3924999Sgblack@eecs.umich.edu req->setExtraData(*res); 3934999Sgblack@eecs.umich.edu } 3944999Sgblack@eecs.umich.edu } 3954999Sgblack@eecs.umich.edu 3966623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 3978949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 3987520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3994999Sgblack@eecs.umich.edu 4008105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4014999Sgblack@eecs.umich.edu dcache_latency += 4024999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4034999Sgblack@eecs.umich.edu } else { 4048931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4058931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4064999Sgblack@eecs.umich.edu else 4074999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4084999Sgblack@eecs.umich.edu } 4094999Sgblack@eecs.umich.edu dcache_access = true; 4104999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4114999Sgblack@eecs.umich.edu 4124999Sgblack@eecs.umich.edu if (req->isSwap()) { 4134999Sgblack@eecs.umich.edu assert(res); 4147520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 4154999Sgblack@eecs.umich.edu } 4164999Sgblack@eecs.umich.edu } 4174999Sgblack@eecs.umich.edu 4184999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4194999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4204878Sstever@eecs.umich.edu } 4214040Ssaidi@eecs.umich.edu } 4224040Ssaidi@eecs.umich.edu 4234999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4244999Sgblack@eecs.umich.edu //stop now. 4254999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4264999Sgblack@eecs.umich.edu { 4276078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4286078Sgblack@eecs.umich.edu assert(locked); 4296078Sgblack@eecs.umich.edu locked = false; 4306078Sgblack@eecs.umich.edu } 4316739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4326739Sgblack@eecs.umich.edu return NoFault; 4336739Sgblack@eecs.umich.edu } else { 4346739Sgblack@eecs.umich.edu return fault; 4356739Sgblack@eecs.umich.edu } 4363170Sstever@eecs.umich.edu } 4373170Sstever@eecs.umich.edu 4384999Sgblack@eecs.umich.edu /* 4394999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4404999Sgblack@eecs.umich.edu */ 4414999Sgblack@eecs.umich.edu 4424999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4437520Sgblack@eecs.umich.edu data += size; 4444999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4457520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4464999Sgblack@eecs.umich.edu //And access the right address. 4474999Sgblack@eecs.umich.edu addr = secondAddr; 4482623SN/A } 4492623SN/A} 4502623SN/A 4512623SN/A 4522623SN/Avoid 4532623SN/AAtomicSimpleCPU::tick() 4542623SN/A{ 4554940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4564940Snate@binkert.org 4575487Snate@binkert.org Tick latency = 0; 4582623SN/A 4596078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 4602623SN/A numCycles++; 4612623SN/A 4623387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4633387Sgblack@eecs.umich.edu checkForInterrupts(); 4642626SN/A 4655348Ssaidi@eecs.umich.edu checkPcEventQueue(); 4668143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 4678143SAli.Saidi@ARM.com if (_status == Idle) 4688143SAli.Saidi@ARM.com return; 4695348Ssaidi@eecs.umich.edu 4705669Sgblack@eecs.umich.edu Fault fault = NoFault; 4715669Sgblack@eecs.umich.edu 4727720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4737720Sgblack@eecs.umich.edu 4747720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 4757720Sgblack@eecs.umich.edu !curMacroStaticInst; 4767720Sgblack@eecs.umich.edu if (needToFetch) { 4775894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 4786023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 4796023Snate@binkert.org BaseTLB::Execute); 4805894Sgblack@eecs.umich.edu } 4812623SN/A 4822623SN/A if (fault == NoFault) { 4834182Sgblack@eecs.umich.edu Tick icache_latency = 0; 4844182Sgblack@eecs.umich.edu bool icache_access = false; 4854182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 4862662Sstever@eecs.umich.edu 4877720Sgblack@eecs.umich.edu if (needToFetch) { 4889023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 4895694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 4905694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 4915694Sgblack@eecs.umich.edu // this code should be uncommented. 4925669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 4939023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 4945669Sgblack@eecs.umich.edu //{ 4955669Sgblack@eecs.umich.edu icache_access = true; 4968949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 4975669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 4982623SN/A 4998931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5008931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5015669Sgblack@eecs.umich.edu else 5025669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5034968Sacolyte@umich.edu 5045669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5054968Sacolyte@umich.edu 5065669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5075669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5085669Sgblack@eecs.umich.edu //} 5095669Sgblack@eecs.umich.edu } 5104182Sgblack@eecs.umich.edu 5112623SN/A preExecute(); 5123814Ssaidi@eecs.umich.edu 5135001Sgblack@eecs.umich.edu if (curStaticInst) { 5144182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5154998Sgblack@eecs.umich.edu 5164998Sgblack@eecs.umich.edu // keep an instruction count 5174998Sgblack@eecs.umich.edu if (fault == NoFault) 5184998Sgblack@eecs.umich.edu countInst(); 5197655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5205001Sgblack@eecs.umich.edu delete traceData; 5215001Sgblack@eecs.umich.edu traceData = NULL; 5225001Sgblack@eecs.umich.edu } 5234998Sgblack@eecs.umich.edu 5244182Sgblack@eecs.umich.edu postExecute(); 5254182Sgblack@eecs.umich.edu } 5262623SN/A 5273814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5284539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5294539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5303814Ssaidi@eecs.umich.edu instCnt++; 5313814Ssaidi@eecs.umich.edu 5325487Snate@binkert.org Tick stall_ticks = 0; 5335487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5345487Snate@binkert.org stall_ticks += icache_latency; 5355487Snate@binkert.org 5365487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5375487Snate@binkert.org stall_ticks += dcache_latency; 5385487Snate@binkert.org 5395487Snate@binkert.org if (stall_ticks) { 5409180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 5419180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 5429180Sandreas.hansson@arm.com // period 5439180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 5449180Sandreas.hansson@arm.com clockPeriod(); 5452623SN/A } 5462623SN/A 5472623SN/A } 5484377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5494182Sgblack@eecs.umich.edu advancePC(fault); 5502623SN/A } 5512623SN/A 5525487Snate@binkert.org // instruction takes at least one cycle 5539179Sandreas.hansson@arm.com if (latency < clockPeriod()) 5549179Sandreas.hansson@arm.com latency = clockPeriod(); 5555487Snate@binkert.org 5562626SN/A if (_status != Idle) 5577823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 5582623SN/A} 5592623SN/A 5602623SN/A 5615315Sstever@gmail.comvoid 5625315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 5635315Sstever@gmail.com{ 5645315Sstever@gmail.com dcachePort.printAddr(a); 5655315Sstever@gmail.com} 5665315Sstever@gmail.com 5675315Sstever@gmail.com 5682623SN/A//////////////////////////////////////////////////////////////////////// 5692623SN/A// 5702623SN/A// AtomicSimpleCPU Simulation Object 5712623SN/A// 5724762Snate@binkert.orgAtomicSimpleCPU * 5734762Snate@binkert.orgAtomicSimpleCPUParams::create() 5742623SN/A{ 5755529Snate@binkert.org numThreads = 1; 5768779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 5774762Snate@binkert.org panic("only one workload allowed"); 5785529Snate@binkert.org return new AtomicSimpleCPU(this); 5792623SN/A} 580