atomic.cc revision 8921
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 328105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 368229Snate@binkert.org#include "cpu/simple/atomic.hh" 372623SN/A#include "cpu/exetrace.hh" 388232Snate@binkert.org#include "debug/ExecFaulting.hh" 398232Snate@binkert.org#include "debug/SimpleCPU.hh" 403348Sbinkertn@umich.edu#include "mem/packet.hh" 413348Sbinkertn@umich.edu#include "mem/packet_access.hh" 424762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 437678Sgblack@eecs.umich.edu#include "sim/faults.hh" 442901Ssaidi@eecs.umich.edu#include "sim/system.hh" 458779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 462623SN/A 472623SN/Ausing namespace std; 482623SN/Ausing namespace TheISA; 492623SN/A 502623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 515606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 522623SN/A{ 532623SN/A} 542623SN/A 552623SN/A 562623SN/Avoid 572623SN/AAtomicSimpleCPU::TickEvent::process() 582623SN/A{ 592623SN/A cpu->tick(); 602623SN/A} 612623SN/A 622623SN/Aconst char * 635336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 642623SN/A{ 654873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 662623SN/A} 672623SN/A 682856Srdreslin@umich.eduPort * 696227Snate@binkert.orgAtomicSimpleCPU::getPort(const string &if_name, int idx) 702856Srdreslin@umich.edu{ 718850Sandreas.hansson@arm.com if (if_name == "physmem_port") { 724968Sacolyte@umich.edu hasPhysMemPort = true; 734968Sacolyte@umich.edu return &physmemPort; 748850Sandreas.hansson@arm.com } else { 758850Sandreas.hansson@arm.com return BaseCPU::getPort(if_name, idx); 764968Sacolyte@umich.edu } 772856Srdreslin@umich.edu} 782623SN/A 792623SN/Avoid 802623SN/AAtomicSimpleCPU::init() 812623SN/A{ 822623SN/A BaseCPU::init(); 838921Sandreas.hansson@arm.com 848921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 858921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 868921Sandreas.hansson@arm.com 878779Sgblack@eecs.umich.edu if (FullSystem) { 888779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 898779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 908779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 918779Sgblack@eecs.umich.edu // initialize CPU, including PC 928779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 938779Sgblack@eecs.umich.edu } 942623SN/A } 958706Sandreas.hansson@arm.com 964968Sacolyte@umich.edu if (hasPhysMemPort) { 978711Sandreas.hansson@arm.com AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges(); 984968Sacolyte@umich.edu physMemAddr = *pmAddrList.begin(); 994968Sacolyte@umich.edu } 1005714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1015712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1025712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1035712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1042623SN/A} 1052623SN/A 1065529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1076078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1085487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1095487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1104968Sacolyte@umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1114968Sacolyte@umich.edu physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1122623SN/A{ 1132623SN/A _status = Idle; 1142623SN/A} 1152623SN/A 1162623SN/A 1172623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1182623SN/A{ 1196775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1206775SBrad.Beckmann@amd.com deschedule(tickEvent); 1216775SBrad.Beckmann@amd.com } 1222623SN/A} 1232623SN/A 1242623SN/Avoid 1252623SN/AAtomicSimpleCPU::serialize(ostream &os) 1262623SN/A{ 1272915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1282915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1296078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1303145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1312623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1322623SN/A tickEvent.serialize(os); 1332623SN/A} 1342623SN/A 1352623SN/Avoid 1362623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1372623SN/A{ 1382915Sktlim@umich.edu SimObject::State so_state; 1392915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1406078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 1413145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1422915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1432915Sktlim@umich.edu} 1442915Sktlim@umich.edu 1452915Sktlim@umich.eduvoid 1462915Sktlim@umich.eduAtomicSimpleCPU::resume() 1472915Sktlim@umich.edu{ 1485220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1495220Ssaidi@eecs.umich.edu return; 1505220Ssaidi@eecs.umich.edu 1514940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1525220Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 1533324Shsul@eecs.umich.edu 1545220Ssaidi@eecs.umich.edu changeState(SimObject::Running); 1555220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1565606Snate@binkert.org if (!tickEvent.scheduled()) 1575606Snate@binkert.org schedule(tickEvent, nextCycle()); 1582915Sktlim@umich.edu } 1597897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1602623SN/A} 1612623SN/A 1622623SN/Avoid 1632798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1642623SN/A{ 1655496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 1662798Sktlim@umich.edu _status = SwitchedOut; 1672623SN/A 1682798Sktlim@umich.edu tickEvent.squash(); 1692623SN/A} 1702623SN/A 1712623SN/A 1722623SN/Avoid 1732623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1742623SN/A{ 1758737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 1762623SN/A 1772623SN/A assert(!tickEvent.scheduled()); 1782623SN/A 1792680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 1802623SN/A // running and schedule its tick event. 1816221Snate@binkert.org ThreadID size = threadContexts.size(); 1826221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 1832680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 1842680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 1852623SN/A _status = Running; 1865606Snate@binkert.org schedule(tickEvent, nextCycle()); 1872623SN/A break; 1882623SN/A } 1892623SN/A } 1903512Sktlim@umich.edu if (_status != Running) { 1913512Sktlim@umich.edu _status = Idle; 1923512Sktlim@umich.edu } 1935169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 1945712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1955712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1965712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1972623SN/A} 1982623SN/A 1992623SN/A 2002623SN/Avoid 2018737Skoansin.tan@gmail.comAtomicSimpleCPU::activateContext(ThreadID thread_num, int delay) 2022623SN/A{ 2034940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2044940Snate@binkert.org 2052623SN/A assert(thread_num == 0); 2062683Sktlim@umich.edu assert(thread); 2072623SN/A 2082623SN/A assert(_status == Idle); 2092623SN/A assert(!tickEvent.scheduled()); 2102623SN/A 2112623SN/A notIdleFraction++; 2125101Ssaidi@eecs.umich.edu numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 2133686Sktlim@umich.edu 2143430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2157823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(delay))); 2162623SN/A _status = Running; 2172623SN/A} 2182623SN/A 2192623SN/A 2202623SN/Avoid 2218737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2222623SN/A{ 2234940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2244940Snate@binkert.org 2252623SN/A assert(thread_num == 0); 2262683Sktlim@umich.edu assert(thread); 2272623SN/A 2286043Sgblack@eecs.umich.edu if (_status == Idle) 2296043Sgblack@eecs.umich.edu return; 2306043Sgblack@eecs.umich.edu 2312623SN/A assert(_status == Running); 2322626SN/A 2332626SN/A // tick event may not be scheduled if this gets called from inside 2342626SN/A // an instruction's execution, e.g. "quiesce" 2352626SN/A if (tickEvent.scheduled()) 2365606Snate@binkert.org deschedule(tickEvent); 2372623SN/A 2382623SN/A notIdleFraction--; 2392623SN/A _status = Idle; 2402623SN/A} 2412623SN/A 2422623SN/A 2432623SN/AFault 2448444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2458444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 2462623SN/A{ 2473169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2484870Sstever@eecs.umich.edu Request *req = &data_read_req; 2492623SN/A 2502623SN/A if (traceData) { 2512623SN/A traceData->setAddr(addr); 2522623SN/A } 2532623SN/A 2544999Sgblack@eecs.umich.edu //The block size of our peer. 2556227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 2564999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 2577520Sgblack@eecs.umich.edu int fullSize = size; 2582623SN/A 2594999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 2604999Sgblack@eecs.umich.edu //across a cache line boundary. 2617520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 2624999Sgblack@eecs.umich.edu 2637520Sgblack@eecs.umich.edu if (secondAddr > addr) 2647520Sgblack@eecs.umich.edu size = secondAddr - addr; 2654999Sgblack@eecs.umich.edu 2664999Sgblack@eecs.umich.edu dcache_latency = 0; 2674999Sgblack@eecs.umich.edu 2687520Sgblack@eecs.umich.edu while (1) { 2698832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 2704999Sgblack@eecs.umich.edu 2714999Sgblack@eecs.umich.edu // translate to physical address 2726023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 2734999Sgblack@eecs.umich.edu 2744999Sgblack@eecs.umich.edu // Now do the access. 2756623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 2764999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 2776102Sgblack@eecs.umich.edu req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 2784999Sgblack@eecs.umich.edu Packet::Broadcast); 2797520Sgblack@eecs.umich.edu pkt.dataStatic(data); 2804999Sgblack@eecs.umich.edu 2818105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 2824999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 2834999Sgblack@eecs.umich.edu else { 2844999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 2854999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 2864999Sgblack@eecs.umich.edu else 2874999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 2884999Sgblack@eecs.umich.edu } 2894999Sgblack@eecs.umich.edu dcache_access = true; 2905012Sgblack@eecs.umich.edu 2914999Sgblack@eecs.umich.edu assert(!pkt.isError()); 2924999Sgblack@eecs.umich.edu 2936102Sgblack@eecs.umich.edu if (req->isLLSC()) { 2944999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 2954999Sgblack@eecs.umich.edu } 2964968Sacolyte@umich.edu } 2974986Ssaidi@eecs.umich.edu 2984999Sgblack@eecs.umich.edu //If there's a fault, return it 2996739Sgblack@eecs.umich.edu if (fault != NoFault) { 3006739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3016739Sgblack@eecs.umich.edu return NoFault; 3026739Sgblack@eecs.umich.edu } else { 3036739Sgblack@eecs.umich.edu return fault; 3046739Sgblack@eecs.umich.edu } 3056739Sgblack@eecs.umich.edu } 3066739Sgblack@eecs.umich.edu 3074999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3084999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3094999Sgblack@eecs.umich.edu { 3106078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3116078Sgblack@eecs.umich.edu assert(!locked); 3126078Sgblack@eecs.umich.edu locked = true; 3136078Sgblack@eecs.umich.edu } 3144999Sgblack@eecs.umich.edu return fault; 3154968Sacolyte@umich.edu } 3163170Sstever@eecs.umich.edu 3174999Sgblack@eecs.umich.edu /* 3184999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3194999Sgblack@eecs.umich.edu */ 3204999Sgblack@eecs.umich.edu 3214999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3227520Sgblack@eecs.umich.edu data += size; 3234999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3247520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3254999Sgblack@eecs.umich.edu //And access the right address. 3264999Sgblack@eecs.umich.edu addr = secondAddr; 3272623SN/A } 3282623SN/A} 3292623SN/A 3307520Sgblack@eecs.umich.edu 3312623SN/AFault 3328444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3338444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3342623SN/A{ 3353169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3364870Sstever@eecs.umich.edu Request *req = &data_write_req; 3372623SN/A 3382623SN/A if (traceData) { 3392623SN/A traceData->setAddr(addr); 3402623SN/A } 3412623SN/A 3424999Sgblack@eecs.umich.edu //The block size of our peer. 3436227Snate@binkert.org unsigned blockSize = dcachePort.peerBlockSize(); 3444999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3457520Sgblack@eecs.umich.edu int fullSize = size; 3462623SN/A 3474999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3484999Sgblack@eecs.umich.edu //across a cache line boundary. 3497520Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + size - 1, blockSize); 3504999Sgblack@eecs.umich.edu 3514999Sgblack@eecs.umich.edu if(secondAddr > addr) 3527520Sgblack@eecs.umich.edu size = secondAddr - addr; 3534999Sgblack@eecs.umich.edu 3544999Sgblack@eecs.umich.edu dcache_latency = 0; 3554999Sgblack@eecs.umich.edu 3564999Sgblack@eecs.umich.edu while(1) { 3578832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3584999Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu // translate to physical address 3606023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 3614999Sgblack@eecs.umich.edu 3624999Sgblack@eecs.umich.edu // Now do the access. 3634999Sgblack@eecs.umich.edu if (fault == NoFault) { 3644999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3654999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3664999Sgblack@eecs.umich.edu 3676102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3684999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3694999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3704999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 3714999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 3724999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 3734999Sgblack@eecs.umich.edu assert(res); 3744999Sgblack@eecs.umich.edu req->setExtraData(*res); 3754999Sgblack@eecs.umich.edu } 3764999Sgblack@eecs.umich.edu } 3774999Sgblack@eecs.umich.edu 3786623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 3794999Sgblack@eecs.umich.edu Packet pkt = Packet(req, cmd, Packet::Broadcast); 3807520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3814999Sgblack@eecs.umich.edu 3828105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 3834999Sgblack@eecs.umich.edu dcache_latency += 3844999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 3854999Sgblack@eecs.umich.edu } else { 3864999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 3874999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 3884999Sgblack@eecs.umich.edu else 3894999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3904999Sgblack@eecs.umich.edu } 3914999Sgblack@eecs.umich.edu dcache_access = true; 3924999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3934999Sgblack@eecs.umich.edu 3944999Sgblack@eecs.umich.edu if (req->isSwap()) { 3954999Sgblack@eecs.umich.edu assert(res); 3967520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 3974999Sgblack@eecs.umich.edu } 3984999Sgblack@eecs.umich.edu } 3994999Sgblack@eecs.umich.edu 4004999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4014999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4024878Sstever@eecs.umich.edu } 4034040Ssaidi@eecs.umich.edu } 4044040Ssaidi@eecs.umich.edu 4054999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4064999Sgblack@eecs.umich.edu //stop now. 4074999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4084999Sgblack@eecs.umich.edu { 4096078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4106078Sgblack@eecs.umich.edu assert(locked); 4116078Sgblack@eecs.umich.edu locked = false; 4126078Sgblack@eecs.umich.edu } 4136739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4146739Sgblack@eecs.umich.edu return NoFault; 4156739Sgblack@eecs.umich.edu } else { 4166739Sgblack@eecs.umich.edu return fault; 4176739Sgblack@eecs.umich.edu } 4183170Sstever@eecs.umich.edu } 4193170Sstever@eecs.umich.edu 4204999Sgblack@eecs.umich.edu /* 4214999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4224999Sgblack@eecs.umich.edu */ 4234999Sgblack@eecs.umich.edu 4244999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4257520Sgblack@eecs.umich.edu data += size; 4264999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4277520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4284999Sgblack@eecs.umich.edu //And access the right address. 4294999Sgblack@eecs.umich.edu addr = secondAddr; 4302623SN/A } 4312623SN/A} 4322623SN/A 4332623SN/A 4342623SN/Avoid 4352623SN/AAtomicSimpleCPU::tick() 4362623SN/A{ 4374940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4384940Snate@binkert.org 4395487Snate@binkert.org Tick latency = 0; 4402623SN/A 4416078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 4422623SN/A numCycles++; 4432623SN/A 4443387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4453387Sgblack@eecs.umich.edu checkForInterrupts(); 4462626SN/A 4475348Ssaidi@eecs.umich.edu checkPcEventQueue(); 4488143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 4498143SAli.Saidi@ARM.com if (_status == Idle) 4508143SAli.Saidi@ARM.com return; 4515348Ssaidi@eecs.umich.edu 4525669Sgblack@eecs.umich.edu Fault fault = NoFault; 4535669Sgblack@eecs.umich.edu 4547720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4557720Sgblack@eecs.umich.edu 4567720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 4577720Sgblack@eecs.umich.edu !curMacroStaticInst; 4587720Sgblack@eecs.umich.edu if (needToFetch) { 4595894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 4606023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 4616023Snate@binkert.org BaseTLB::Execute); 4625894Sgblack@eecs.umich.edu } 4632623SN/A 4642623SN/A if (fault == NoFault) { 4654182Sgblack@eecs.umich.edu Tick icache_latency = 0; 4664182Sgblack@eecs.umich.edu bool icache_access = false; 4674182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 4682662Sstever@eecs.umich.edu 4697720Sgblack@eecs.umich.edu if (needToFetch) { 4705694Sgblack@eecs.umich.edu // This is commented out because the predecoder would act like 4715694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 4725694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 4735694Sgblack@eecs.umich.edu // this code should be uncommented. 4745669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 4755669Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 4765669Sgblack@eecs.umich.edu //{ 4775669Sgblack@eecs.umich.edu icache_access = true; 4785669Sgblack@eecs.umich.edu Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 4795669Sgblack@eecs.umich.edu Packet::Broadcast); 4805669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 4812623SN/A 4825669Sgblack@eecs.umich.edu if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 4835669Sgblack@eecs.umich.edu icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 4845669Sgblack@eecs.umich.edu else 4855669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 4864968Sacolyte@umich.edu 4875669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 4884968Sacolyte@umich.edu 4895669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 4905669Sgblack@eecs.umich.edu // into the CPU object's inst field. 4915669Sgblack@eecs.umich.edu //} 4925669Sgblack@eecs.umich.edu } 4934182Sgblack@eecs.umich.edu 4942623SN/A preExecute(); 4953814Ssaidi@eecs.umich.edu 4965001Sgblack@eecs.umich.edu if (curStaticInst) { 4974182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 4984998Sgblack@eecs.umich.edu 4994998Sgblack@eecs.umich.edu // keep an instruction count 5004998Sgblack@eecs.umich.edu if (fault == NoFault) 5014998Sgblack@eecs.umich.edu countInst(); 5027655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5035001Sgblack@eecs.umich.edu delete traceData; 5045001Sgblack@eecs.umich.edu traceData = NULL; 5055001Sgblack@eecs.umich.edu } 5064998Sgblack@eecs.umich.edu 5074182Sgblack@eecs.umich.edu postExecute(); 5084182Sgblack@eecs.umich.edu } 5092623SN/A 5103814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5114539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5124539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5133814Ssaidi@eecs.umich.edu instCnt++; 5143814Ssaidi@eecs.umich.edu 5155487Snate@binkert.org Tick stall_ticks = 0; 5165487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5175487Snate@binkert.org stall_ticks += icache_latency; 5185487Snate@binkert.org 5195487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5205487Snate@binkert.org stall_ticks += dcache_latency; 5215487Snate@binkert.org 5225487Snate@binkert.org if (stall_ticks) { 5235487Snate@binkert.org Tick stall_cycles = stall_ticks / ticks(1); 5245487Snate@binkert.org Tick aligned_stall_ticks = ticks(stall_cycles); 5255487Snate@binkert.org 5265487Snate@binkert.org if (aligned_stall_ticks < stall_ticks) 5275487Snate@binkert.org aligned_stall_ticks += 1; 5285487Snate@binkert.org 5295487Snate@binkert.org latency += aligned_stall_ticks; 5302623SN/A } 5312623SN/A 5322623SN/A } 5334377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5344182Sgblack@eecs.umich.edu advancePC(fault); 5352623SN/A } 5362623SN/A 5375487Snate@binkert.org // instruction takes at least one cycle 5385487Snate@binkert.org if (latency < ticks(1)) 5395487Snate@binkert.org latency = ticks(1); 5405487Snate@binkert.org 5412626SN/A if (_status != Idle) 5427823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 5432623SN/A} 5442623SN/A 5452623SN/A 5465315Sstever@gmail.comvoid 5475315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 5485315Sstever@gmail.com{ 5495315Sstever@gmail.com dcachePort.printAddr(a); 5505315Sstever@gmail.com} 5515315Sstever@gmail.com 5525315Sstever@gmail.com 5532623SN/A//////////////////////////////////////////////////////////////////////// 5542623SN/A// 5552623SN/A// AtomicSimpleCPU Simulation Object 5562623SN/A// 5574762Snate@binkert.orgAtomicSimpleCPU * 5584762Snate@binkert.orgAtomicSimpleCPUParams::create() 5592623SN/A{ 5605529Snate@binkert.org numThreads = 1; 5618779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 5624762Snate@binkert.org panic("only one workload allowed"); 5635529Snate@binkert.org return new AtomicSimpleCPU(this); 5642623SN/A} 565