atomic.cc revision 6078
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/atomic.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 465606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 472623SN/A{ 482623SN/A} 492623SN/A 502623SN/A 512623SN/Avoid 522623SN/AAtomicSimpleCPU::TickEvent::process() 532623SN/A{ 542623SN/A cpu->tick(); 552623SN/A} 562623SN/A 572623SN/Aconst char * 585336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 592623SN/A{ 604873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 612623SN/A} 622623SN/A 632856Srdreslin@umich.eduPort * 642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 652856Srdreslin@umich.edu{ 662856Srdreslin@umich.edu if (if_name == "dcache_port") 672856Srdreslin@umich.edu return &dcachePort; 682856Srdreslin@umich.edu else if (if_name == "icache_port") 692856Srdreslin@umich.edu return &icachePort; 704968Sacolyte@umich.edu else if (if_name == "physmem_port") { 714968Sacolyte@umich.edu hasPhysMemPort = true; 724968Sacolyte@umich.edu return &physmemPort; 734968Sacolyte@umich.edu } 742856Srdreslin@umich.edu else 752856Srdreslin@umich.edu panic("No Such Port\n"); 762856Srdreslin@umich.edu} 772623SN/A 782623SN/Avoid 792623SN/AAtomicSimpleCPU::init() 802623SN/A{ 812623SN/A BaseCPU::init(); 822623SN/A#if FULL_SYSTEM 832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 852623SN/A 862623SN/A // initialize CPU, including PC 875714Shsul@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 882623SN/A } 892623SN/A#endif 904968Sacolyte@umich.edu if (hasPhysMemPort) { 914968Sacolyte@umich.edu bool snoop = false; 924968Sacolyte@umich.edu AddrRangeList pmAddrList; 934968Sacolyte@umich.edu physmemPort.getPeerAddressRanges(pmAddrList, snoop); 944968Sacolyte@umich.edu physMemAddr = *pmAddrList.begin(); 954968Sacolyte@umich.edu } 965714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 975712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 985712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 995712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1002623SN/A} 1012623SN/A 1022623SN/Abool 1033349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 1042623SN/A{ 1053184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 1062623SN/A return true; 1072623SN/A} 1082623SN/A 1092623SN/ATick 1103349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 1112623SN/A{ 1123310Srdreslin@umich.edu //Snooping a coherence request, just return 1133649Srdreslin@umich.edu return 0; 1142623SN/A} 1152623SN/A 1162623SN/Avoid 1173349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1182623SN/A{ 1193184Srdreslin@umich.edu //No internal storage to update, just return 1203184Srdreslin@umich.edu return; 1212623SN/A} 1222623SN/A 1232623SN/Avoid 1242623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1252623SN/A{ 1263647Srdreslin@umich.edu if (status == RangeChange) { 1273647Srdreslin@umich.edu if (!snoopRangeSent) { 1283647Srdreslin@umich.edu snoopRangeSent = true; 1293647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1303647Srdreslin@umich.edu } 1312626SN/A return; 1323647Srdreslin@umich.edu } 1332626SN/A 1342623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1352623SN/A} 1362623SN/A 1372657Ssaidi@eecs.umich.eduvoid 1382623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1392623SN/A{ 1402623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1412623SN/A} 1422623SN/A 1434192Sktlim@umich.eduvoid 1444192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port) 1454192Sktlim@umich.edu{ 1464192Sktlim@umich.edu Port::setPeer(port); 1474192Sktlim@umich.edu 1484192Sktlim@umich.edu#if FULL_SYSTEM 1494192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 1504192Sktlim@umich.edu // Ports) 1515497Ssaidi@eecs.umich.edu cpu->tcBase()->connectMemPorts(cpu->tcBase()); 1524192Sktlim@umich.edu#endif 1534192Sktlim@umich.edu} 1542623SN/A 1555529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1566078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1575487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1585487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1594968Sacolyte@umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1604968Sacolyte@umich.edu physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1612623SN/A{ 1622623SN/A _status = Idle; 1632623SN/A 1643647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1653647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1663647Srdreslin@umich.edu 1672623SN/A} 1682623SN/A 1692623SN/A 1702623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1712623SN/A{ 1722623SN/A} 1732623SN/A 1742623SN/Avoid 1752623SN/AAtomicSimpleCPU::serialize(ostream &os) 1762623SN/A{ 1772915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1782915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1796078Sgblack@eecs.umich.edu SERIALIZE_SCALAR(locked); 1803145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1812623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1822623SN/A tickEvent.serialize(os); 1832623SN/A} 1842623SN/A 1852623SN/Avoid 1862623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1872623SN/A{ 1882915Sktlim@umich.edu SimObject::State so_state; 1892915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1906078Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(locked); 1913145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1922915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1932915Sktlim@umich.edu} 1942915Sktlim@umich.edu 1952915Sktlim@umich.eduvoid 1962915Sktlim@umich.eduAtomicSimpleCPU::resume() 1972915Sktlim@umich.edu{ 1985220Ssaidi@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1995220Ssaidi@eecs.umich.edu return; 2005220Ssaidi@eecs.umich.edu 2014940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 2025220Ssaidi@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 2033324Shsul@eecs.umich.edu 2045220Ssaidi@eecs.umich.edu changeState(SimObject::Running); 2055220Ssaidi@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 2065606Snate@binkert.org if (!tickEvent.scheduled()) 2075606Snate@binkert.org schedule(tickEvent, nextCycle()); 2082915Sktlim@umich.edu } 2092623SN/A} 2102623SN/A 2112623SN/Avoid 2122798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2132623SN/A{ 2145496Ssaidi@eecs.umich.edu assert(_status == Running || _status == Idle); 2152798Sktlim@umich.edu _status = SwitchedOut; 2162623SN/A 2172798Sktlim@umich.edu tickEvent.squash(); 2182623SN/A} 2192623SN/A 2202623SN/A 2212623SN/Avoid 2222623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2232623SN/A{ 2244192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2252623SN/A 2262623SN/A assert(!tickEvent.scheduled()); 2272623SN/A 2282680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2292623SN/A // running and schedule its tick event. 2302680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2312680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2322680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2332623SN/A _status = Running; 2345606Snate@binkert.org schedule(tickEvent, nextCycle()); 2352623SN/A break; 2362623SN/A } 2372623SN/A } 2383512Sktlim@umich.edu if (_status != Running) { 2393512Sktlim@umich.edu _status = Idle; 2403512Sktlim@umich.edu } 2415169Ssaidi@eecs.umich.edu assert(threadContexts.size() == 1); 2425712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2435712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2445712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2492623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2502623SN/A{ 2514940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2524940Snate@binkert.org 2532623SN/A assert(thread_num == 0); 2542683Sktlim@umich.edu assert(thread); 2552623SN/A 2562623SN/A assert(_status == Idle); 2572623SN/A assert(!tickEvent.scheduled()); 2582623SN/A 2592623SN/A notIdleFraction++; 2605101Ssaidi@eecs.umich.edu numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 2613686Sktlim@umich.edu 2623430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2635606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(delay))); 2642623SN/A _status = Running; 2652623SN/A} 2662623SN/A 2672623SN/A 2682623SN/Avoid 2692623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2702623SN/A{ 2714940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2724940Snate@binkert.org 2732623SN/A assert(thread_num == 0); 2742683Sktlim@umich.edu assert(thread); 2752623SN/A 2766043Sgblack@eecs.umich.edu if (_status == Idle) 2776043Sgblack@eecs.umich.edu return; 2786043Sgblack@eecs.umich.edu 2792623SN/A assert(_status == Running); 2802626SN/A 2812626SN/A // tick event may not be scheduled if this gets called from inside 2822626SN/A // an instruction's execution, e.g. "quiesce" 2832626SN/A if (tickEvent.scheduled()) 2845606Snate@binkert.org deschedule(tickEvent); 2852623SN/A 2862623SN/A notIdleFraction--; 2872623SN/A _status = Idle; 2882623SN/A} 2892623SN/A 2902623SN/A 2912623SN/Atemplate <class T> 2922623SN/AFault 2932623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2942623SN/A{ 2953169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2964870Sstever@eecs.umich.edu Request *req = &data_read_req; 2972623SN/A 2982623SN/A if (traceData) { 2992623SN/A traceData->setAddr(addr); 3002623SN/A } 3012623SN/A 3024999Sgblack@eecs.umich.edu //The block size of our peer. 3034999Sgblack@eecs.umich.edu int blockSize = dcachePort.peerBlockSize(); 3044999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3054999Sgblack@eecs.umich.edu int dataSize = sizeof(T); 3062623SN/A 3074999Sgblack@eecs.umich.edu uint8_t * dataPtr = (uint8_t *)&data; 3082623SN/A 3094999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3104999Sgblack@eecs.umich.edu //across a cache line boundary. 3114999Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 3124999Sgblack@eecs.umich.edu 3134999Sgblack@eecs.umich.edu if(secondAddr > addr) 3144999Sgblack@eecs.umich.edu dataSize = secondAddr - addr; 3154999Sgblack@eecs.umich.edu 3164999Sgblack@eecs.umich.edu dcache_latency = 0; 3174999Sgblack@eecs.umich.edu 3184999Sgblack@eecs.umich.edu while(1) { 3194999Sgblack@eecs.umich.edu req->setVirt(0, addr, dataSize, flags, thread->readPC()); 3204999Sgblack@eecs.umich.edu 3214999Sgblack@eecs.umich.edu // translate to physical address 3226023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3234999Sgblack@eecs.umich.edu 3244999Sgblack@eecs.umich.edu // Now do the access. 3254999Sgblack@eecs.umich.edu if (fault == NoFault) { 3264999Sgblack@eecs.umich.edu Packet pkt = Packet(req, 3276076Sgblack@eecs.umich.edu req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 3284999Sgblack@eecs.umich.edu Packet::Broadcast); 3294999Sgblack@eecs.umich.edu pkt.dataStatic(dataPtr); 3304999Sgblack@eecs.umich.edu 3314999Sgblack@eecs.umich.edu if (req->isMmapedIpr()) 3324999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3334999Sgblack@eecs.umich.edu else { 3344999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 3354999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 3364999Sgblack@eecs.umich.edu else 3374999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3384999Sgblack@eecs.umich.edu } 3394999Sgblack@eecs.umich.edu dcache_access = true; 3405012Sgblack@eecs.umich.edu 3414999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3424999Sgblack@eecs.umich.edu 3436076Sgblack@eecs.umich.edu if (req->isLlsc()) { 3444999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3454999Sgblack@eecs.umich.edu } 3464968Sacolyte@umich.edu } 3474986Ssaidi@eecs.umich.edu 3484999Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 3494999Sgblack@eecs.umich.edu if (req->isUncacheable()) 3504999Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 3514762Snate@binkert.org 3524999Sgblack@eecs.umich.edu //If there's a fault, return it 3534999Sgblack@eecs.umich.edu if (fault != NoFault) 3544999Sgblack@eecs.umich.edu return fault; 3554999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3564999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3574999Sgblack@eecs.umich.edu { 3584999Sgblack@eecs.umich.edu data = gtoh(data); 3595408Sgblack@eecs.umich.edu if (traceData) { 3605408Sgblack@eecs.umich.edu traceData->setData(data); 3615408Sgblack@eecs.umich.edu } 3626078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3636078Sgblack@eecs.umich.edu assert(!locked); 3646078Sgblack@eecs.umich.edu locked = true; 3656078Sgblack@eecs.umich.edu } 3664999Sgblack@eecs.umich.edu return fault; 3674968Sacolyte@umich.edu } 3683170Sstever@eecs.umich.edu 3694999Sgblack@eecs.umich.edu /* 3704999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3714999Sgblack@eecs.umich.edu */ 3724999Sgblack@eecs.umich.edu 3734999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3744999Sgblack@eecs.umich.edu dataPtr += dataSize; 3754999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3764999Sgblack@eecs.umich.edu dataSize = addr + sizeof(T) - secondAddr; 3774999Sgblack@eecs.umich.edu //And access the right address. 3784999Sgblack@eecs.umich.edu addr = secondAddr; 3792623SN/A } 3802623SN/A} 3812623SN/A 3822623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3832623SN/A 3842623SN/Atemplate 3852623SN/AFault 3864115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3874115Ssaidi@eecs.umich.edu 3884115Ssaidi@eecs.umich.edutemplate 3894115Ssaidi@eecs.umich.eduFault 3904040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3914040Ssaidi@eecs.umich.edu 3924040Ssaidi@eecs.umich.edutemplate 3934040Ssaidi@eecs.umich.eduFault 3942623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3952623SN/A 3962623SN/Atemplate 3972623SN/AFault 3982623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3992623SN/A 4002623SN/Atemplate 4012623SN/AFault 4022623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4032623SN/A 4042623SN/Atemplate 4052623SN/AFault 4062623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4072623SN/A 4082623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4092623SN/A 4102623SN/Atemplate<> 4112623SN/AFault 4122623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 4132623SN/A{ 4142623SN/A return read(addr, *(uint64_t*)&data, flags); 4152623SN/A} 4162623SN/A 4172623SN/Atemplate<> 4182623SN/AFault 4192623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 4202623SN/A{ 4212623SN/A return read(addr, *(uint32_t*)&data, flags); 4222623SN/A} 4232623SN/A 4242623SN/A 4252623SN/Atemplate<> 4262623SN/AFault 4272623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4282623SN/A{ 4292623SN/A return read(addr, (uint32_t&)data, flags); 4302623SN/A} 4312623SN/A 4322623SN/A 4332623SN/Atemplate <class T> 4342623SN/AFault 4352623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 4362623SN/A{ 4373169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4384870Sstever@eecs.umich.edu Request *req = &data_write_req; 4392623SN/A 4402623SN/A if (traceData) { 4412623SN/A traceData->setAddr(addr); 4422623SN/A } 4432623SN/A 4444999Sgblack@eecs.umich.edu //The block size of our peer. 4454999Sgblack@eecs.umich.edu int blockSize = dcachePort.peerBlockSize(); 4464999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4474999Sgblack@eecs.umich.edu int dataSize = sizeof(T); 4482623SN/A 4494999Sgblack@eecs.umich.edu uint8_t * dataPtr = (uint8_t *)&data; 4502623SN/A 4514999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4524999Sgblack@eecs.umich.edu //across a cache line boundary. 4534999Sgblack@eecs.umich.edu Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 4544999Sgblack@eecs.umich.edu 4554999Sgblack@eecs.umich.edu if(secondAddr > addr) 4564999Sgblack@eecs.umich.edu dataSize = secondAddr - addr; 4574999Sgblack@eecs.umich.edu 4584999Sgblack@eecs.umich.edu dcache_latency = 0; 4594999Sgblack@eecs.umich.edu 4604999Sgblack@eecs.umich.edu while(1) { 4614999Sgblack@eecs.umich.edu req->setVirt(0, addr, dataSize, flags, thread->readPC()); 4624999Sgblack@eecs.umich.edu 4634999Sgblack@eecs.umich.edu // translate to physical address 4646023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4654999Sgblack@eecs.umich.edu 4664999Sgblack@eecs.umich.edu // Now do the access. 4674999Sgblack@eecs.umich.edu if (fault == NoFault) { 4684999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4694999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4704999Sgblack@eecs.umich.edu 4716076Sgblack@eecs.umich.edu if (req->isLlsc()) { 4724999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 4734999Sgblack@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 4744999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4754999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4764999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4774999Sgblack@eecs.umich.edu assert(res); 4784999Sgblack@eecs.umich.edu req->setExtraData(*res); 4794999Sgblack@eecs.umich.edu } 4804999Sgblack@eecs.umich.edu } 4814999Sgblack@eecs.umich.edu 4824999Sgblack@eecs.umich.edu if (do_access) { 4834999Sgblack@eecs.umich.edu Packet pkt = Packet(req, cmd, Packet::Broadcast); 4844999Sgblack@eecs.umich.edu pkt.dataStatic(dataPtr); 4854999Sgblack@eecs.umich.edu 4864999Sgblack@eecs.umich.edu if (req->isMmapedIpr()) { 4874999Sgblack@eecs.umich.edu dcache_latency += 4884999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4894999Sgblack@eecs.umich.edu } else { 4904999Sgblack@eecs.umich.edu //XXX This needs to be outside of the loop in order to 4914999Sgblack@eecs.umich.edu //work properly for cache line boundary crossing 4924999Sgblack@eecs.umich.edu //accesses in transendian simulations. 4934999Sgblack@eecs.umich.edu data = htog(data); 4944999Sgblack@eecs.umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 4954999Sgblack@eecs.umich.edu dcache_latency += physmemPort.sendAtomic(&pkt); 4964999Sgblack@eecs.umich.edu else 4974999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4984999Sgblack@eecs.umich.edu } 4994999Sgblack@eecs.umich.edu dcache_access = true; 5004999Sgblack@eecs.umich.edu assert(!pkt.isError()); 5014999Sgblack@eecs.umich.edu 5024999Sgblack@eecs.umich.edu if (req->isSwap()) { 5034999Sgblack@eecs.umich.edu assert(res); 5044999Sgblack@eecs.umich.edu *res = pkt.get<T>(); 5054999Sgblack@eecs.umich.edu } 5064999Sgblack@eecs.umich.edu } 5074999Sgblack@eecs.umich.edu 5084999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5094999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5104878Sstever@eecs.umich.edu } 5114040Ssaidi@eecs.umich.edu } 5124040Ssaidi@eecs.umich.edu 5134999Sgblack@eecs.umich.edu // This will need a new way to tell if it's hooked up to a cache or not. 5144999Sgblack@eecs.umich.edu if (req->isUncacheable()) 5154999Sgblack@eecs.umich.edu recordEvent("Uncached Write"); 5162631SN/A 5174999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5184999Sgblack@eecs.umich.edu //stop now. 5194999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5204999Sgblack@eecs.umich.edu { 5214999Sgblack@eecs.umich.edu // If the write needs to have a fault on the access, consider 5224999Sgblack@eecs.umich.edu // calling changeStatus() and changing it to "bad addr write" 5234999Sgblack@eecs.umich.edu // or something. 5245408Sgblack@eecs.umich.edu if (traceData) { 5256012Ssteve.reinhardt@amd.com traceData->setData(gtoh(data)); 5265408Sgblack@eecs.umich.edu } 5276078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 5286078Sgblack@eecs.umich.edu assert(locked); 5296078Sgblack@eecs.umich.edu locked = false; 5306078Sgblack@eecs.umich.edu } 5314999Sgblack@eecs.umich.edu return fault; 5323170Sstever@eecs.umich.edu } 5333170Sstever@eecs.umich.edu 5344999Sgblack@eecs.umich.edu /* 5354999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5364999Sgblack@eecs.umich.edu */ 5374999Sgblack@eecs.umich.edu 5384999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5394999Sgblack@eecs.umich.edu dataPtr += dataSize; 5404999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5414999Sgblack@eecs.umich.edu dataSize = addr + sizeof(T) - secondAddr; 5424999Sgblack@eecs.umich.edu //And access the right address. 5434999Sgblack@eecs.umich.edu addr = secondAddr; 5442623SN/A } 5452623SN/A} 5462623SN/A 5472623SN/A 5482623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 5494224Sgblack@eecs.umich.edu 5504224Sgblack@eecs.umich.edutemplate 5514224Sgblack@eecs.umich.eduFault 5524224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr, 5534224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5544224Sgblack@eecs.umich.edu 5554224Sgblack@eecs.umich.edutemplate 5564224Sgblack@eecs.umich.eduFault 5574224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr, 5584224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 5594224Sgblack@eecs.umich.edu 5602623SN/Atemplate 5612623SN/AFault 5622623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 5632623SN/A unsigned flags, uint64_t *res); 5642623SN/A 5652623SN/Atemplate 5662623SN/AFault 5672623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 5682623SN/A unsigned flags, uint64_t *res); 5692623SN/A 5702623SN/Atemplate 5712623SN/AFault 5722623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 5732623SN/A unsigned flags, uint64_t *res); 5742623SN/A 5752623SN/Atemplate 5762623SN/AFault 5772623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 5782623SN/A unsigned flags, uint64_t *res); 5792623SN/A 5802623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5812623SN/A 5822623SN/Atemplate<> 5832623SN/AFault 5842623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5852623SN/A{ 5862623SN/A return write(*(uint64_t*)&data, addr, flags, res); 5872623SN/A} 5882623SN/A 5892623SN/Atemplate<> 5902623SN/AFault 5912623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5922623SN/A{ 5932623SN/A return write(*(uint32_t*)&data, addr, flags, res); 5942623SN/A} 5952623SN/A 5962623SN/A 5972623SN/Atemplate<> 5982623SN/AFault 5992623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 6002623SN/A{ 6012623SN/A return write((uint32_t)data, addr, flags, res); 6022623SN/A} 6032623SN/A 6042623SN/A 6052623SN/Avoid 6062623SN/AAtomicSimpleCPU::tick() 6072623SN/A{ 6084940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 6094940Snate@binkert.org 6105487Snate@binkert.org Tick latency = 0; 6112623SN/A 6126078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 6132623SN/A numCycles++; 6142623SN/A 6153387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 6163387Sgblack@eecs.umich.edu checkForInterrupts(); 6172626SN/A 6185348Ssaidi@eecs.umich.edu checkPcEventQueue(); 6195348Ssaidi@eecs.umich.edu 6205669Sgblack@eecs.umich.edu Fault fault = NoFault; 6215669Sgblack@eecs.umich.edu 6225669Sgblack@eecs.umich.edu bool fromRom = isRomMicroPC(thread->readMicroPC()); 6235914Sgblack@eecs.umich.edu if (!fromRom && !curMacroStaticInst) { 6245894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 6256023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 6266023Snate@binkert.org BaseTLB::Execute); 6275894Sgblack@eecs.umich.edu } 6282623SN/A 6292623SN/A if (fault == NoFault) { 6304182Sgblack@eecs.umich.edu Tick icache_latency = 0; 6314182Sgblack@eecs.umich.edu bool icache_access = false; 6324182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 6332662Sstever@eecs.umich.edu 6345914Sgblack@eecs.umich.edu if (!fromRom && !curMacroStaticInst) { 6355694Sgblack@eecs.umich.edu // This is commented out because the predecoder would act like 6365694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 6375694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 6385694Sgblack@eecs.umich.edu // this code should be uncommented. 6395669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 6405669Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 6415669Sgblack@eecs.umich.edu //{ 6425669Sgblack@eecs.umich.edu icache_access = true; 6435669Sgblack@eecs.umich.edu Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 6445669Sgblack@eecs.umich.edu Packet::Broadcast); 6455669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6462623SN/A 6475669Sgblack@eecs.umich.edu if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 6485669Sgblack@eecs.umich.edu icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 6495669Sgblack@eecs.umich.edu else 6505669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6514968Sacolyte@umich.edu 6525669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6534968Sacolyte@umich.edu 6545669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6555669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6565669Sgblack@eecs.umich.edu //} 6575669Sgblack@eecs.umich.edu } 6584182Sgblack@eecs.umich.edu 6592623SN/A preExecute(); 6603814Ssaidi@eecs.umich.edu 6615001Sgblack@eecs.umich.edu if (curStaticInst) { 6624182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 6634998Sgblack@eecs.umich.edu 6644998Sgblack@eecs.umich.edu // keep an instruction count 6654998Sgblack@eecs.umich.edu if (fault == NoFault) 6664998Sgblack@eecs.umich.edu countInst(); 6675001Sgblack@eecs.umich.edu else if (traceData) { 6685001Sgblack@eecs.umich.edu // If there was a fault, we should trace this instruction. 6695001Sgblack@eecs.umich.edu delete traceData; 6705001Sgblack@eecs.umich.edu traceData = NULL; 6715001Sgblack@eecs.umich.edu } 6724998Sgblack@eecs.umich.edu 6734182Sgblack@eecs.umich.edu postExecute(); 6744182Sgblack@eecs.umich.edu } 6752623SN/A 6763814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6774539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6784539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6793814Ssaidi@eecs.umich.edu instCnt++; 6803814Ssaidi@eecs.umich.edu 6815487Snate@binkert.org Tick stall_ticks = 0; 6825487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6835487Snate@binkert.org stall_ticks += icache_latency; 6845487Snate@binkert.org 6855487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6865487Snate@binkert.org stall_ticks += dcache_latency; 6875487Snate@binkert.org 6885487Snate@binkert.org if (stall_ticks) { 6895487Snate@binkert.org Tick stall_cycles = stall_ticks / ticks(1); 6905487Snate@binkert.org Tick aligned_stall_ticks = ticks(stall_cycles); 6915487Snate@binkert.org 6925487Snate@binkert.org if (aligned_stall_ticks < stall_ticks) 6935487Snate@binkert.org aligned_stall_ticks += 1; 6945487Snate@binkert.org 6955487Snate@binkert.org latency += aligned_stall_ticks; 6962623SN/A } 6972623SN/A 6982623SN/A } 6994377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 7004182Sgblack@eecs.umich.edu advancePC(fault); 7012623SN/A } 7022623SN/A 7035487Snate@binkert.org // instruction takes at least one cycle 7045487Snate@binkert.org if (latency < ticks(1)) 7055487Snate@binkert.org latency = ticks(1); 7065487Snate@binkert.org 7072626SN/A if (_status != Idle) 7085606Snate@binkert.org schedule(tickEvent, curTick + latency); 7092623SN/A} 7102623SN/A 7112623SN/A 7125315Sstever@gmail.comvoid 7135315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 7145315Sstever@gmail.com{ 7155315Sstever@gmail.com dcachePort.printAddr(a); 7165315Sstever@gmail.com} 7175315Sstever@gmail.com 7185315Sstever@gmail.com 7192623SN/A//////////////////////////////////////////////////////////////////////// 7202623SN/A// 7212623SN/A// AtomicSimpleCPU Simulation Object 7222623SN/A// 7234762Snate@binkert.orgAtomicSimpleCPU * 7244762Snate@binkert.orgAtomicSimpleCPUParams::create() 7252623SN/A{ 7265529Snate@binkert.org numThreads = 1; 7275529Snate@binkert.org#if !FULL_SYSTEM 7284762Snate@binkert.org if (workload.size() != 1) 7294762Snate@binkert.org panic("only one workload allowed"); 7302623SN/A#endif 7315529Snate@binkert.org return new AtomicSimpleCPU(this); 7322623SN/A} 733