atomic.cc revision 5310
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
344040Ssaidi@eecs.umich.edu#include "base/bigint.hh"
352623SN/A#include "cpu/exetrace.hh"
362623SN/A#include "cpu/simple/atomic.hh"
373348Sbinkertn@umich.edu#include "mem/packet.hh"
383348Sbinkertn@umich.edu#include "mem/packet_access.hh"
394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh"
402901Ssaidi@eecs.umich.edu#include "sim/system.hh"
412623SN/A
422623SN/Ausing namespace std;
432623SN/Ausing namespace TheISA;
442623SN/A
452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
462623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
472623SN/A{
482623SN/A}
492623SN/A
502623SN/A
512623SN/Avoid
522623SN/AAtomicSimpleCPU::TickEvent::process()
532623SN/A{
542623SN/A    cpu->tick();
552623SN/A}
562623SN/A
572623SN/Aconst char *
582623SN/AAtomicSimpleCPU::TickEvent::description()
592623SN/A{
604873Sstever@eecs.umich.edu    return "AtomicSimpleCPU tick";
612623SN/A}
622623SN/A
632856Srdreslin@umich.eduPort *
642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
652856Srdreslin@umich.edu{
662856Srdreslin@umich.edu    if (if_name == "dcache_port")
672856Srdreslin@umich.edu        return &dcachePort;
682856Srdreslin@umich.edu    else if (if_name == "icache_port")
692856Srdreslin@umich.edu        return &icachePort;
704968Sacolyte@umich.edu    else if (if_name == "physmem_port") {
714968Sacolyte@umich.edu        hasPhysMemPort = true;
724968Sacolyte@umich.edu        return &physmemPort;
734968Sacolyte@umich.edu    }
742856Srdreslin@umich.edu    else
752856Srdreslin@umich.edu        panic("No Such Port\n");
762856Srdreslin@umich.edu}
772623SN/A
782623SN/Avoid
792623SN/AAtomicSimpleCPU::init()
802623SN/A{
812623SN/A    BaseCPU::init();
825310Ssaidi@eecs.umich.edu    cpuId = tc->readCpuId();
832623SN/A#if FULL_SYSTEM
842680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
852680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
862623SN/A
872623SN/A        // initialize CPU, including PC
885310Ssaidi@eecs.umich.edu        TheISA::initCPU(tc, cpuId);
892623SN/A    }
902623SN/A#endif
914968Sacolyte@umich.edu    if (hasPhysMemPort) {
924968Sacolyte@umich.edu        bool snoop = false;
934968Sacolyte@umich.edu        AddrRangeList pmAddrList;
944968Sacolyte@umich.edu        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
954968Sacolyte@umich.edu        physMemAddr = *pmAddrList.begin();
964968Sacolyte@umich.edu    }
975310Ssaidi@eecs.umich.edu    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
985310Ssaidi@eecs.umich.edu    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
995310Ssaidi@eecs.umich.edu    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
1002623SN/A}
1012623SN/A
1022623SN/Abool
1033349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
1042623SN/A{
1053184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
1062623SN/A    return true;
1072623SN/A}
1082623SN/A
1092623SN/ATick
1103349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
1112623SN/A{
1123310Srdreslin@umich.edu    //Snooping a coherence request, just return
1133649Srdreslin@umich.edu    return 0;
1142623SN/A}
1152623SN/A
1162623SN/Avoid
1173349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1182623SN/A{
1193184Srdreslin@umich.edu    //No internal storage to update, just return
1203184Srdreslin@umich.edu    return;
1212623SN/A}
1222623SN/A
1232623SN/Avoid
1242623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1252623SN/A{
1263647Srdreslin@umich.edu    if (status == RangeChange) {
1273647Srdreslin@umich.edu        if (!snoopRangeSent) {
1283647Srdreslin@umich.edu            snoopRangeSent = true;
1293647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1303647Srdreslin@umich.edu        }
1312626SN/A        return;
1323647Srdreslin@umich.edu    }
1332626SN/A
1342623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1352623SN/A}
1362623SN/A
1372657Ssaidi@eecs.umich.eduvoid
1382623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1392623SN/A{
1402623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1412623SN/A}
1422623SN/A
1434192Sktlim@umich.eduvoid
1444192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port)
1454192Sktlim@umich.edu{
1464192Sktlim@umich.edu    Port::setPeer(port);
1474192Sktlim@umich.edu
1484192Sktlim@umich.edu#if FULL_SYSTEM
1494192Sktlim@umich.edu    // Update the ThreadContext's memory ports (Functional/Virtual
1504192Sktlim@umich.edu    // Ports)
1514192Sktlim@umich.edu    cpu->tcBase()->connectMemPorts();
1524192Sktlim@umich.edu#endif
1534192Sktlim@umich.edu}
1542623SN/A
1552623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1562623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1572623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1584968Sacolyte@umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
1594968Sacolyte@umich.edu      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
1602623SN/A{
1612623SN/A    _status = Idle;
1622623SN/A
1633647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1643647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1653647Srdreslin@umich.edu
1662623SN/A}
1672623SN/A
1682623SN/A
1692623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1702623SN/A{
1712623SN/A}
1722623SN/A
1732623SN/Avoid
1742623SN/AAtomicSimpleCPU::serialize(ostream &os)
1752623SN/A{
1762915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1772915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1783177Shsul@eecs.umich.edu    Status _status = status();
1793177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1803145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1812623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1822623SN/A    tickEvent.serialize(os);
1832623SN/A}
1842623SN/A
1852623SN/Avoid
1862623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1872623SN/A{
1882915Sktlim@umich.edu    SimObject::State so_state;
1892915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1903177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1913145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1922915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1932915Sktlim@umich.edu}
1942915Sktlim@umich.edu
1952915Sktlim@umich.eduvoid
1962915Sktlim@umich.eduAtomicSimpleCPU::resume()
1972915Sktlim@umich.edu{
1985220Ssaidi@eecs.umich.edu    if (_status == Idle || _status == SwitchedOut)
1995220Ssaidi@eecs.umich.edu        return;
2005220Ssaidi@eecs.umich.edu
2014940Snate@binkert.org    DPRINTF(SimpleCPU, "Resume\n");
2025220Ssaidi@eecs.umich.edu    assert(system->getMemoryMode() == Enums::atomic);
2033324Shsul@eecs.umich.edu
2045220Ssaidi@eecs.umich.edu    changeState(SimObject::Running);
2055220Ssaidi@eecs.umich.edu    if (thread->status() == ThreadContext::Active) {
2065220Ssaidi@eecs.umich.edu        if (!tickEvent.scheduled()) {
2075220Ssaidi@eecs.umich.edu            tickEvent.schedule(nextCycle());
2083324Shsul@eecs.umich.edu        }
2092915Sktlim@umich.edu    }
2102623SN/A}
2112623SN/A
2122623SN/Avoid
2132798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2142623SN/A{
2152798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2162798Sktlim@umich.edu    _status = SwitchedOut;
2172623SN/A
2182798Sktlim@umich.edu    tickEvent.squash();
2192623SN/A}
2202623SN/A
2212623SN/A
2222623SN/Avoid
2232623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2242623SN/A{
2254192Sktlim@umich.edu    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
2262623SN/A
2272623SN/A    assert(!tickEvent.scheduled());
2282623SN/A
2292680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2302623SN/A    // running and schedule its tick event.
2312680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2322680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2332680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2342623SN/A            _status = Running;
2353495Sktlim@umich.edu            tickEvent.schedule(nextCycle());
2362623SN/A            break;
2372623SN/A        }
2382623SN/A    }
2393512Sktlim@umich.edu    if (_status != Running) {
2403512Sktlim@umich.edu        _status = Idle;
2413512Sktlim@umich.edu    }
2425169Ssaidi@eecs.umich.edu    assert(threadContexts.size() == 1);
2435169Ssaidi@eecs.umich.edu    cpuId = tc->readCpuId();
2445310Ssaidi@eecs.umich.edu    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
2455310Ssaidi@eecs.umich.edu    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
2465310Ssaidi@eecs.umich.edu    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
2472623SN/A}
2482623SN/A
2492623SN/A
2502623SN/Avoid
2512623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2522623SN/A{
2534940Snate@binkert.org    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
2544940Snate@binkert.org
2552623SN/A    assert(thread_num == 0);
2562683Sktlim@umich.edu    assert(thread);
2572623SN/A
2582623SN/A    assert(_status == Idle);
2592623SN/A    assert(!tickEvent.scheduled());
2602623SN/A
2612623SN/A    notIdleFraction++;
2625101Ssaidi@eecs.umich.edu    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
2633686Sktlim@umich.edu
2643430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2655100Ssaidi@eecs.umich.edu    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
2662623SN/A    _status = Running;
2672623SN/A}
2682623SN/A
2692623SN/A
2702623SN/Avoid
2712623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2722623SN/A{
2734940Snate@binkert.org    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
2744940Snate@binkert.org
2752623SN/A    assert(thread_num == 0);
2762683Sktlim@umich.edu    assert(thread);
2772623SN/A
2782623SN/A    assert(_status == Running);
2792626SN/A
2802626SN/A    // tick event may not be scheduled if this gets called from inside
2812626SN/A    // an instruction's execution, e.g. "quiesce"
2822626SN/A    if (tickEvent.scheduled())
2832626SN/A        tickEvent.deschedule();
2842623SN/A
2852623SN/A    notIdleFraction--;
2862623SN/A    _status = Idle;
2872623SN/A}
2882623SN/A
2892623SN/A
2902623SN/Atemplate <class T>
2912623SN/AFault
2922623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2932623SN/A{
2943169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2954870Sstever@eecs.umich.edu    Request *req = &data_read_req;
2962623SN/A
2972623SN/A    if (traceData) {
2982623SN/A        traceData->setAddr(addr);
2992623SN/A    }
3002623SN/A
3014999Sgblack@eecs.umich.edu    //The block size of our peer.
3024999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
3034999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
3044999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
3052623SN/A
3064999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
3072623SN/A
3084999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3094999Sgblack@eecs.umich.edu    //across a cache line boundary.
3104999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
3114999Sgblack@eecs.umich.edu
3124999Sgblack@eecs.umich.edu    if(secondAddr > addr)
3134999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
3144999Sgblack@eecs.umich.edu
3154999Sgblack@eecs.umich.edu    dcache_latency = 0;
3164999Sgblack@eecs.umich.edu
3174999Sgblack@eecs.umich.edu    while(1) {
3184999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
3194999Sgblack@eecs.umich.edu
3204999Sgblack@eecs.umich.edu        // translate to physical address
3214999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataReadReq(req);
3224999Sgblack@eecs.umich.edu
3234999Sgblack@eecs.umich.edu        // Now do the access.
3244999Sgblack@eecs.umich.edu        if (fault == NoFault) {
3254999Sgblack@eecs.umich.edu            Packet pkt = Packet(req,
3264999Sgblack@eecs.umich.edu                    req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
3274999Sgblack@eecs.umich.edu                    Packet::Broadcast);
3284999Sgblack@eecs.umich.edu            pkt.dataStatic(dataPtr);
3294999Sgblack@eecs.umich.edu
3304999Sgblack@eecs.umich.edu            if (req->isMmapedIpr())
3314999Sgblack@eecs.umich.edu                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
3324999Sgblack@eecs.umich.edu            else {
3334999Sgblack@eecs.umich.edu                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
3344999Sgblack@eecs.umich.edu                    dcache_latency += physmemPort.sendAtomic(&pkt);
3354999Sgblack@eecs.umich.edu                else
3364999Sgblack@eecs.umich.edu                    dcache_latency += dcachePort.sendAtomic(&pkt);
3374999Sgblack@eecs.umich.edu            }
3384999Sgblack@eecs.umich.edu            dcache_access = true;
3395012Sgblack@eecs.umich.edu
3404999Sgblack@eecs.umich.edu            assert(!pkt.isError());
3414999Sgblack@eecs.umich.edu
3424999Sgblack@eecs.umich.edu            if (req->isLocked()) {
3434999Sgblack@eecs.umich.edu                TheISA::handleLockedRead(thread, req);
3444999Sgblack@eecs.umich.edu            }
3454968Sacolyte@umich.edu        }
3464986Ssaidi@eecs.umich.edu
3474999Sgblack@eecs.umich.edu        // This will need a new way to tell if it has a dcache attached.
3484999Sgblack@eecs.umich.edu        if (req->isUncacheable())
3494999Sgblack@eecs.umich.edu            recordEvent("Uncached Read");
3504762Snate@binkert.org
3514999Sgblack@eecs.umich.edu        //If there's a fault, return it
3524999Sgblack@eecs.umich.edu        if (fault != NoFault)
3534999Sgblack@eecs.umich.edu            return fault;
3544999Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
3554999Sgblack@eecs.umich.edu        if (secondAddr <= addr)
3564999Sgblack@eecs.umich.edu        {
3574999Sgblack@eecs.umich.edu            data = gtoh(data);
3584999Sgblack@eecs.umich.edu            return fault;
3594968Sacolyte@umich.edu        }
3603170Sstever@eecs.umich.edu
3614999Sgblack@eecs.umich.edu        /*
3624999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
3634999Sgblack@eecs.umich.edu         */
3644999Sgblack@eecs.umich.edu
3654999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
3664999Sgblack@eecs.umich.edu        dataPtr += dataSize;
3674999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
3684999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
3694999Sgblack@eecs.umich.edu        //And access the right address.
3704999Sgblack@eecs.umich.edu        addr = secondAddr;
3712623SN/A    }
3722623SN/A}
3732623SN/A
3745177Sgblack@eecs.umich.eduFault
3755177Sgblack@eecs.umich.eduAtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
3765177Sgblack@eecs.umich.edu        int size, unsigned flags)
3775177Sgblack@eecs.umich.edu{
3785177Sgblack@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
3795177Sgblack@eecs.umich.edu    Request *req = &data_read_req;
3805177Sgblack@eecs.umich.edu
3815177Sgblack@eecs.umich.edu    if (traceData) {
3825177Sgblack@eecs.umich.edu        traceData->setAddr(vaddr);
3835177Sgblack@eecs.umich.edu    }
3845177Sgblack@eecs.umich.edu
3855177Sgblack@eecs.umich.edu    //The block size of our peer.
3865177Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
3875177Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
3885177Sgblack@eecs.umich.edu    int dataSize = size;
3895177Sgblack@eecs.umich.edu
3905177Sgblack@eecs.umich.edu    bool firstTimeThrough = true;
3915177Sgblack@eecs.umich.edu
3925177Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3935177Sgblack@eecs.umich.edu    //across a cache line boundary.
3945177Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
3955177Sgblack@eecs.umich.edu
3965177Sgblack@eecs.umich.edu    if(secondAddr > vaddr)
3975177Sgblack@eecs.umich.edu        dataSize = secondAddr - vaddr;
3985177Sgblack@eecs.umich.edu
3995177Sgblack@eecs.umich.edu    while(1) {
4005177Sgblack@eecs.umich.edu        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
4015177Sgblack@eecs.umich.edu
4025177Sgblack@eecs.umich.edu        // translate to physical address
4035177Sgblack@eecs.umich.edu        Fault fault = thread->translateDataReadReq(req);
4045177Sgblack@eecs.umich.edu
4055177Sgblack@eecs.umich.edu        //If there's a fault, return it
4065177Sgblack@eecs.umich.edu        if (fault != NoFault)
4075177Sgblack@eecs.umich.edu            return fault;
4085177Sgblack@eecs.umich.edu
4095177Sgblack@eecs.umich.edu        if (firstTimeThrough) {
4105177Sgblack@eecs.umich.edu            paddr = req->getPaddr();
4115177Sgblack@eecs.umich.edu            firstTimeThrough = false;
4125177Sgblack@eecs.umich.edu        }
4135177Sgblack@eecs.umich.edu
4145177Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
4155177Sgblack@eecs.umich.edu        if (secondAddr <= vaddr)
4165177Sgblack@eecs.umich.edu            return fault;
4175177Sgblack@eecs.umich.edu
4185177Sgblack@eecs.umich.edu        /*
4195177Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
4205177Sgblack@eecs.umich.edu         */
4215177Sgblack@eecs.umich.edu
4225177Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
4235177Sgblack@eecs.umich.edu        dataSize = vaddr + size - secondAddr;
4245177Sgblack@eecs.umich.edu        //And access the right address.
4255177Sgblack@eecs.umich.edu        vaddr = secondAddr;
4265177Sgblack@eecs.umich.edu    }
4275177Sgblack@eecs.umich.edu}
4285177Sgblack@eecs.umich.edu
4292623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
4302623SN/A
4312623SN/Atemplate
4322623SN/AFault
4334115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
4344115Ssaidi@eecs.umich.edu
4354115Ssaidi@eecs.umich.edutemplate
4364115Ssaidi@eecs.umich.eduFault
4374040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
4384040Ssaidi@eecs.umich.edu
4394040Ssaidi@eecs.umich.edutemplate
4404040Ssaidi@eecs.umich.eduFault
4412623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
4422623SN/A
4432623SN/Atemplate
4442623SN/AFault
4452623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
4462623SN/A
4472623SN/Atemplate
4482623SN/AFault
4492623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
4502623SN/A
4512623SN/Atemplate
4522623SN/AFault
4532623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
4542623SN/A
4552623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4562623SN/A
4572623SN/Atemplate<>
4582623SN/AFault
4592623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
4602623SN/A{
4612623SN/A    return read(addr, *(uint64_t*)&data, flags);
4622623SN/A}
4632623SN/A
4642623SN/Atemplate<>
4652623SN/AFault
4662623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
4672623SN/A{
4682623SN/A    return read(addr, *(uint32_t*)&data, flags);
4692623SN/A}
4702623SN/A
4712623SN/A
4722623SN/Atemplate<>
4732623SN/AFault
4742623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
4752623SN/A{
4762623SN/A    return read(addr, (uint32_t&)data, flags);
4772623SN/A}
4782623SN/A
4792623SN/A
4802623SN/Atemplate <class T>
4812623SN/AFault
4822623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
4832623SN/A{
4843169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
4854870Sstever@eecs.umich.edu    Request *req = &data_write_req;
4862623SN/A
4872623SN/A    if (traceData) {
4882623SN/A        traceData->setAddr(addr);
4892623SN/A    }
4902623SN/A
4914999Sgblack@eecs.umich.edu    //The block size of our peer.
4924999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
4934999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
4944999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
4952623SN/A
4964999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
4972623SN/A
4984999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
4994999Sgblack@eecs.umich.edu    //across a cache line boundary.
5004999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
5014999Sgblack@eecs.umich.edu
5024999Sgblack@eecs.umich.edu    if(secondAddr > addr)
5034999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
5044999Sgblack@eecs.umich.edu
5054999Sgblack@eecs.umich.edu    dcache_latency = 0;
5064999Sgblack@eecs.umich.edu
5074999Sgblack@eecs.umich.edu    while(1) {
5084999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
5094999Sgblack@eecs.umich.edu
5104999Sgblack@eecs.umich.edu        // translate to physical address
5114999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataWriteReq(req);
5124999Sgblack@eecs.umich.edu
5134999Sgblack@eecs.umich.edu        // Now do the access.
5144999Sgblack@eecs.umich.edu        if (fault == NoFault) {
5154999Sgblack@eecs.umich.edu            MemCmd cmd = MemCmd::WriteReq; // default
5164999Sgblack@eecs.umich.edu            bool do_access = true;  // flag to suppress cache access
5174999Sgblack@eecs.umich.edu
5184999Sgblack@eecs.umich.edu            if (req->isLocked()) {
5194999Sgblack@eecs.umich.edu                cmd = MemCmd::StoreCondReq;
5204999Sgblack@eecs.umich.edu                do_access = TheISA::handleLockedWrite(thread, req);
5214999Sgblack@eecs.umich.edu            } else if (req->isSwap()) {
5224999Sgblack@eecs.umich.edu                cmd = MemCmd::SwapReq;
5234999Sgblack@eecs.umich.edu                if (req->isCondSwap()) {
5244999Sgblack@eecs.umich.edu                    assert(res);
5254999Sgblack@eecs.umich.edu                    req->setExtraData(*res);
5264999Sgblack@eecs.umich.edu                }
5274999Sgblack@eecs.umich.edu            }
5284999Sgblack@eecs.umich.edu
5294999Sgblack@eecs.umich.edu            if (do_access) {
5304999Sgblack@eecs.umich.edu                Packet pkt = Packet(req, cmd, Packet::Broadcast);
5314999Sgblack@eecs.umich.edu                pkt.dataStatic(dataPtr);
5324999Sgblack@eecs.umich.edu
5334999Sgblack@eecs.umich.edu                if (req->isMmapedIpr()) {
5344999Sgblack@eecs.umich.edu                    dcache_latency +=
5354999Sgblack@eecs.umich.edu                        TheISA::handleIprWrite(thread->getTC(), &pkt);
5364999Sgblack@eecs.umich.edu                } else {
5374999Sgblack@eecs.umich.edu                    //XXX This needs to be outside of the loop in order to
5384999Sgblack@eecs.umich.edu                    //work properly for cache line boundary crossing
5394999Sgblack@eecs.umich.edu                    //accesses in transendian simulations.
5404999Sgblack@eecs.umich.edu                    data = htog(data);
5414999Sgblack@eecs.umich.edu                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
5424999Sgblack@eecs.umich.edu                        dcache_latency += physmemPort.sendAtomic(&pkt);
5434999Sgblack@eecs.umich.edu                    else
5444999Sgblack@eecs.umich.edu                        dcache_latency += dcachePort.sendAtomic(&pkt);
5454999Sgblack@eecs.umich.edu                }
5464999Sgblack@eecs.umich.edu                dcache_access = true;
5474999Sgblack@eecs.umich.edu                assert(!pkt.isError());
5484999Sgblack@eecs.umich.edu
5494999Sgblack@eecs.umich.edu                if (req->isSwap()) {
5504999Sgblack@eecs.umich.edu                    assert(res);
5514999Sgblack@eecs.umich.edu                    *res = pkt.get<T>();
5524999Sgblack@eecs.umich.edu                }
5534999Sgblack@eecs.umich.edu            }
5544999Sgblack@eecs.umich.edu
5554999Sgblack@eecs.umich.edu            if (res && !req->isSwap()) {
5564999Sgblack@eecs.umich.edu                *res = req->getExtraData();
5574878Sstever@eecs.umich.edu            }
5584040Ssaidi@eecs.umich.edu        }
5594040Ssaidi@eecs.umich.edu
5604999Sgblack@eecs.umich.edu        // This will need a new way to tell if it's hooked up to a cache or not.
5614999Sgblack@eecs.umich.edu        if (req->isUncacheable())
5624999Sgblack@eecs.umich.edu            recordEvent("Uncached Write");
5632631SN/A
5644999Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
5654999Sgblack@eecs.umich.edu        //stop now.
5664999Sgblack@eecs.umich.edu        if (fault != NoFault || secondAddr <= addr)
5674999Sgblack@eecs.umich.edu        {
5684999Sgblack@eecs.umich.edu            // If the write needs to have a fault on the access, consider
5694999Sgblack@eecs.umich.edu            // calling changeStatus() and changing it to "bad addr write"
5704999Sgblack@eecs.umich.edu            // or something.
5714999Sgblack@eecs.umich.edu            return fault;
5723170Sstever@eecs.umich.edu        }
5733170Sstever@eecs.umich.edu
5744999Sgblack@eecs.umich.edu        /*
5754999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
5764999Sgblack@eecs.umich.edu         */
5774999Sgblack@eecs.umich.edu
5784999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
5794999Sgblack@eecs.umich.edu        dataPtr += dataSize;
5804999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
5814999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
5824999Sgblack@eecs.umich.edu        //And access the right address.
5834999Sgblack@eecs.umich.edu        addr = secondAddr;
5842623SN/A    }
5852623SN/A}
5862623SN/A
5875177Sgblack@eecs.umich.eduFault
5885177Sgblack@eecs.umich.eduAtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
5895177Sgblack@eecs.umich.edu        int size, unsigned flags)
5905177Sgblack@eecs.umich.edu{
5915177Sgblack@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
5925177Sgblack@eecs.umich.edu    Request *req = &data_write_req;
5935177Sgblack@eecs.umich.edu
5945177Sgblack@eecs.umich.edu    if (traceData) {
5955177Sgblack@eecs.umich.edu        traceData->setAddr(vaddr);
5965177Sgblack@eecs.umich.edu    }
5975177Sgblack@eecs.umich.edu
5985177Sgblack@eecs.umich.edu    //The block size of our peer.
5995177Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
6005177Sgblack@eecs.umich.edu
6015177Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
6025177Sgblack@eecs.umich.edu    //across a cache line boundary.
6035177Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
6045177Sgblack@eecs.umich.edu
6055177Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
6065177Sgblack@eecs.umich.edu    int dataSize = size;
6075177Sgblack@eecs.umich.edu
6085177Sgblack@eecs.umich.edu    bool firstTimeThrough = true;
6095177Sgblack@eecs.umich.edu
6105177Sgblack@eecs.umich.edu    if(secondAddr > vaddr)
6115177Sgblack@eecs.umich.edu        dataSize = secondAddr - vaddr;
6125177Sgblack@eecs.umich.edu
6135177Sgblack@eecs.umich.edu    dcache_latency = 0;
6145177Sgblack@eecs.umich.edu
6155177Sgblack@eecs.umich.edu    while(1) {
6165278Sgblack@eecs.umich.edu        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
6175177Sgblack@eecs.umich.edu
6185177Sgblack@eecs.umich.edu        // translate to physical address
6195177Sgblack@eecs.umich.edu        Fault fault = thread->translateDataWriteReq(req);
6205177Sgblack@eecs.umich.edu
6215177Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
6225177Sgblack@eecs.umich.edu        //stop now.
6235177Sgblack@eecs.umich.edu        if (fault != NoFault)
6245177Sgblack@eecs.umich.edu            return fault;
6255177Sgblack@eecs.umich.edu
6265177Sgblack@eecs.umich.edu        if (firstTimeThrough) {
6275177Sgblack@eecs.umich.edu            paddr = req->getPaddr();
6285177Sgblack@eecs.umich.edu            firstTimeThrough = false;
6295177Sgblack@eecs.umich.edu        }
6305177Sgblack@eecs.umich.edu
6315177Sgblack@eecs.umich.edu        if (secondAddr <= vaddr)
6325177Sgblack@eecs.umich.edu            return fault;
6335177Sgblack@eecs.umich.edu
6345177Sgblack@eecs.umich.edu        /*
6355177Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
6365177Sgblack@eecs.umich.edu         */
6375177Sgblack@eecs.umich.edu
6385177Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
6395177Sgblack@eecs.umich.edu        dataSize = vaddr + size - secondAddr;
6405177Sgblack@eecs.umich.edu        //And access the right address.
6415177Sgblack@eecs.umich.edu        vaddr = secondAddr;
6425177Sgblack@eecs.umich.edu    }
6435177Sgblack@eecs.umich.edu}
6445177Sgblack@eecs.umich.edu
6452623SN/A
6462623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
6474224Sgblack@eecs.umich.edu
6484224Sgblack@eecs.umich.edutemplate
6494224Sgblack@eecs.umich.eduFault
6504224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr,
6514224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
6524224Sgblack@eecs.umich.edu
6534224Sgblack@eecs.umich.edutemplate
6544224Sgblack@eecs.umich.eduFault
6554224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr,
6564224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
6574224Sgblack@eecs.umich.edu
6582623SN/Atemplate
6592623SN/AFault
6602623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
6612623SN/A                       unsigned flags, uint64_t *res);
6622623SN/A
6632623SN/Atemplate
6642623SN/AFault
6652623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
6662623SN/A                       unsigned flags, uint64_t *res);
6672623SN/A
6682623SN/Atemplate
6692623SN/AFault
6702623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
6712623SN/A                       unsigned flags, uint64_t *res);
6722623SN/A
6732623SN/Atemplate
6742623SN/AFault
6752623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
6762623SN/A                       unsigned flags, uint64_t *res);
6772623SN/A
6782623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
6792623SN/A
6802623SN/Atemplate<>
6812623SN/AFault
6822623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
6832623SN/A{
6842623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
6852623SN/A}
6862623SN/A
6872623SN/Atemplate<>
6882623SN/AFault
6892623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
6902623SN/A{
6912623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
6922623SN/A}
6932623SN/A
6942623SN/A
6952623SN/Atemplate<>
6962623SN/AFault
6972623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
6982623SN/A{
6992623SN/A    return write((uint32_t)data, addr, flags, res);
7002623SN/A}
7012623SN/A
7022623SN/A
7032623SN/Avoid
7042623SN/AAtomicSimpleCPU::tick()
7052623SN/A{
7064940Snate@binkert.org    DPRINTF(SimpleCPU, "Tick\n");
7074940Snate@binkert.org
7085100Ssaidi@eecs.umich.edu    Tick latency = ticks(1); // instruction takes one cycle by default
7092623SN/A
7102623SN/A    for (int i = 0; i < width; ++i) {
7112623SN/A        numCycles++;
7122623SN/A
7133387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
7143387Sgblack@eecs.umich.edu            checkForInterrupts();
7152626SN/A
7164870Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(&ifetch_req);
7172623SN/A
7182623SN/A        if (fault == NoFault) {
7194182Sgblack@eecs.umich.edu            Tick icache_latency = 0;
7204182Sgblack@eecs.umich.edu            bool icache_access = false;
7214182Sgblack@eecs.umich.edu            dcache_access = false; // assume no dcache access
7222662Sstever@eecs.umich.edu
7234182Sgblack@eecs.umich.edu            //Fetch more instruction memory if necessary
7244593Sgblack@eecs.umich.edu            //if(predecoder.needMoreBytes())
7254593Sgblack@eecs.umich.edu            //{
7264182Sgblack@eecs.umich.edu                icache_access = true;
7274870Sstever@eecs.umich.edu                Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
7284870Sstever@eecs.umich.edu                                           Packet::Broadcast);
7294870Sstever@eecs.umich.edu                ifetch_pkt.dataStatic(&inst);
7302623SN/A
7314968Sacolyte@umich.edu                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
7324968Sacolyte@umich.edu                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
7334968Sacolyte@umich.edu                else
7344968Sacolyte@umich.edu                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
7354968Sacolyte@umich.edu
7364986Ssaidi@eecs.umich.edu                assert(!ifetch_pkt.isError());
7374968Sacolyte@umich.edu
7384182Sgblack@eecs.umich.edu                // ifetch_req is initialized to read the instruction directly
7394182Sgblack@eecs.umich.edu                // into the CPU object's inst field.
7404593Sgblack@eecs.umich.edu            //}
7414182Sgblack@eecs.umich.edu
7422623SN/A            preExecute();
7433814Ssaidi@eecs.umich.edu
7445001Sgblack@eecs.umich.edu            if (curStaticInst) {
7454182Sgblack@eecs.umich.edu                fault = curStaticInst->execute(this, traceData);
7464998Sgblack@eecs.umich.edu
7474998Sgblack@eecs.umich.edu                // keep an instruction count
7484998Sgblack@eecs.umich.edu                if (fault == NoFault)
7494998Sgblack@eecs.umich.edu                    countInst();
7505001Sgblack@eecs.umich.edu                else if (traceData) {
7515001Sgblack@eecs.umich.edu                    // If there was a fault, we should trace this instruction.
7525001Sgblack@eecs.umich.edu                    delete traceData;
7535001Sgblack@eecs.umich.edu                    traceData = NULL;
7545001Sgblack@eecs.umich.edu                }
7554998Sgblack@eecs.umich.edu
7564182Sgblack@eecs.umich.edu                postExecute();
7574182Sgblack@eecs.umich.edu            }
7582623SN/A
7593814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
7604539Sgblack@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroop() ||
7614539Sgblack@eecs.umich.edu                        curStaticInst->isFirstMicroop()))
7623814Ssaidi@eecs.umich.edu                instCnt++;
7633814Ssaidi@eecs.umich.edu
7642623SN/A            if (simulate_stalls) {
7654182Sgblack@eecs.umich.edu                Tick icache_stall =
7665100Ssaidi@eecs.umich.edu                    icache_access ? icache_latency - ticks(1) : 0;
7672623SN/A                Tick dcache_stall =
7685100Ssaidi@eecs.umich.edu                    dcache_access ? dcache_latency - ticks(1) : 0;
7695100Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
7705100Ssaidi@eecs.umich.edu                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
7715100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles+1);
7722803Ssaidi@eecs.umich.edu                else
7735100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles);
7742623SN/A            }
7752623SN/A
7762623SN/A        }
7774377Sgblack@eecs.umich.edu        if(fault != NoFault || !stayAtPC)
7784182Sgblack@eecs.umich.edu            advancePC(fault);
7792623SN/A    }
7802623SN/A
7812626SN/A    if (_status != Idle)
7822626SN/A        tickEvent.schedule(curTick + latency);
7832623SN/A}
7842623SN/A
7852623SN/A
7862623SN/A////////////////////////////////////////////////////////////////////////
7872623SN/A//
7882623SN/A//  AtomicSimpleCPU Simulation Object
7892623SN/A//
7904762Snate@binkert.orgAtomicSimpleCPU *
7914762Snate@binkert.orgAtomicSimpleCPUParams::create()
7922623SN/A{
7932623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
7944762Snate@binkert.org    params->name = name;
7952623SN/A    params->numberOfThreads = 1;
7962623SN/A    params->max_insts_any_thread = max_insts_any_thread;
7972623SN/A    params->max_insts_all_threads = max_insts_all_threads;
7982623SN/A    params->max_loads_any_thread = max_loads_any_thread;
7992623SN/A    params->max_loads_all_threads = max_loads_all_threads;
8003119Sktlim@umich.edu    params->progress_interval = progress_interval;
8012623SN/A    params->deferRegistration = defer_registration;
8023661Srdreslin@umich.edu    params->phase = phase;
8032623SN/A    params->clock = clock;
8042623SN/A    params->functionTrace = function_trace;
8052623SN/A    params->functionTraceStart = function_trace_start;
8062623SN/A    params->width = width;
8072623SN/A    params->simulate_stalls = simulate_stalls;
8082901Ssaidi@eecs.umich.edu    params->system = system;
8093170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
8104776Sgblack@eecs.umich.edu    params->tracer = tracer;
8112623SN/A
8122623SN/A    params->itb = itb;
8132623SN/A    params->dtb = dtb;
8144997Sgblack@eecs.umich.edu#if FULL_SYSTEM
8152623SN/A    params->profile = profile;
8163617Sbinkertn@umich.edu    params->do_quiesce = do_quiesce;
8173617Sbinkertn@umich.edu    params->do_checkpoint_insts = do_checkpoint_insts;
8183617Sbinkertn@umich.edu    params->do_statistics_insts = do_statistics_insts;
8192623SN/A#else
8204762Snate@binkert.org    if (workload.size() != 1)
8214762Snate@binkert.org        panic("only one workload allowed");
8224762Snate@binkert.org    params->process = workload[0];
8232623SN/A#endif
8242623SN/A
8252623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
8262623SN/A    return cpu;
8272623SN/A}
828