atomic.cc revision 5278
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
344040Ssaidi@eecs.umich.edu#include "base/bigint.hh"
352623SN/A#include "cpu/exetrace.hh"
362623SN/A#include "cpu/simple/atomic.hh"
373348Sbinkertn@umich.edu#include "mem/packet.hh"
383348Sbinkertn@umich.edu#include "mem/packet_access.hh"
394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh"
402901Ssaidi@eecs.umich.edu#include "sim/system.hh"
412623SN/A
422623SN/Ausing namespace std;
432623SN/Ausing namespace TheISA;
442623SN/A
452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
462623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
472623SN/A{
482623SN/A}
492623SN/A
502623SN/A
512623SN/Avoid
522623SN/AAtomicSimpleCPU::TickEvent::process()
532623SN/A{
542623SN/A    cpu->tick();
552623SN/A}
562623SN/A
572623SN/Aconst char *
582623SN/AAtomicSimpleCPU::TickEvent::description()
592623SN/A{
604873Sstever@eecs.umich.edu    return "AtomicSimpleCPU tick";
612623SN/A}
622623SN/A
632856Srdreslin@umich.eduPort *
642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
652856Srdreslin@umich.edu{
662856Srdreslin@umich.edu    if (if_name == "dcache_port")
672856Srdreslin@umich.edu        return &dcachePort;
682856Srdreslin@umich.edu    else if (if_name == "icache_port")
692856Srdreslin@umich.edu        return &icachePort;
704968Sacolyte@umich.edu    else if (if_name == "physmem_port") {
714968Sacolyte@umich.edu        hasPhysMemPort = true;
724968Sacolyte@umich.edu        return &physmemPort;
734968Sacolyte@umich.edu    }
742856Srdreslin@umich.edu    else
752856Srdreslin@umich.edu        panic("No Such Port\n");
762856Srdreslin@umich.edu}
772623SN/A
782623SN/Avoid
792623SN/AAtomicSimpleCPU::init()
802623SN/A{
812623SN/A    BaseCPU::init();
822623SN/A#if FULL_SYSTEM
832680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
842680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
852623SN/A
862623SN/A        // initialize CPU, including PC
872680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
882623SN/A    }
892623SN/A#endif
904968Sacolyte@umich.edu    if (hasPhysMemPort) {
914968Sacolyte@umich.edu        bool snoop = false;
924968Sacolyte@umich.edu        AddrRangeList pmAddrList;
934968Sacolyte@umich.edu        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
944968Sacolyte@umich.edu        physMemAddr = *pmAddrList.begin();
954968Sacolyte@umich.edu    }
962623SN/A}
972623SN/A
982623SN/Abool
993349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
1002623SN/A{
1013184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
1022623SN/A    return true;
1032623SN/A}
1042623SN/A
1052623SN/ATick
1063349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
1072623SN/A{
1083310Srdreslin@umich.edu    //Snooping a coherence request, just return
1093649Srdreslin@umich.edu    return 0;
1102623SN/A}
1112623SN/A
1122623SN/Avoid
1133349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1142623SN/A{
1153184Srdreslin@umich.edu    //No internal storage to update, just return
1163184Srdreslin@umich.edu    return;
1172623SN/A}
1182623SN/A
1192623SN/Avoid
1202623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1212623SN/A{
1223647Srdreslin@umich.edu    if (status == RangeChange) {
1233647Srdreslin@umich.edu        if (!snoopRangeSent) {
1243647Srdreslin@umich.edu            snoopRangeSent = true;
1253647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1263647Srdreslin@umich.edu        }
1272626SN/A        return;
1283647Srdreslin@umich.edu    }
1292626SN/A
1302623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1312623SN/A}
1322623SN/A
1332657Ssaidi@eecs.umich.eduvoid
1342623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1352623SN/A{
1362623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1372623SN/A}
1382623SN/A
1394192Sktlim@umich.eduvoid
1404192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port)
1414192Sktlim@umich.edu{
1424192Sktlim@umich.edu    Port::setPeer(port);
1434192Sktlim@umich.edu
1444192Sktlim@umich.edu#if FULL_SYSTEM
1454192Sktlim@umich.edu    // Update the ThreadContext's memory ports (Functional/Virtual
1464192Sktlim@umich.edu    // Ports)
1474192Sktlim@umich.edu    cpu->tcBase()->connectMemPorts();
1484192Sktlim@umich.edu#endif
1494192Sktlim@umich.edu}
1502623SN/A
1512623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1522623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1532623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1544968Sacolyte@umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
1554968Sacolyte@umich.edu      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
1562623SN/A{
1572623SN/A    _status = Idle;
1582623SN/A
1593647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1603647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1613647Srdreslin@umich.edu
1625169Ssaidi@eecs.umich.edu    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
1635169Ssaidi@eecs.umich.edu    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
1645169Ssaidi@eecs.umich.edu    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
1652623SN/A}
1662623SN/A
1672623SN/A
1682623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1692623SN/A{
1702623SN/A}
1712623SN/A
1722623SN/Avoid
1732623SN/AAtomicSimpleCPU::serialize(ostream &os)
1742623SN/A{
1752915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1762915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1773177Shsul@eecs.umich.edu    Status _status = status();
1783177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1793145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1802623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1812623SN/A    tickEvent.serialize(os);
1822623SN/A}
1832623SN/A
1842623SN/Avoid
1852623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1862623SN/A{
1872915Sktlim@umich.edu    SimObject::State so_state;
1882915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1893177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1903145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1912915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1922915Sktlim@umich.edu}
1932915Sktlim@umich.edu
1942915Sktlim@umich.eduvoid
1952915Sktlim@umich.eduAtomicSimpleCPU::resume()
1962915Sktlim@umich.edu{
1975220Ssaidi@eecs.umich.edu    if (_status == Idle || _status == SwitchedOut)
1985220Ssaidi@eecs.umich.edu        return;
1995220Ssaidi@eecs.umich.edu
2004940Snate@binkert.org    DPRINTF(SimpleCPU, "Resume\n");
2015220Ssaidi@eecs.umich.edu    assert(system->getMemoryMode() == Enums::atomic);
2023324Shsul@eecs.umich.edu
2035220Ssaidi@eecs.umich.edu    changeState(SimObject::Running);
2045220Ssaidi@eecs.umich.edu    if (thread->status() == ThreadContext::Active) {
2055220Ssaidi@eecs.umich.edu        if (!tickEvent.scheduled()) {
2065220Ssaidi@eecs.umich.edu            tickEvent.schedule(nextCycle());
2073324Shsul@eecs.umich.edu        }
2082915Sktlim@umich.edu    }
2092623SN/A}
2102623SN/A
2112623SN/Avoid
2122798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2132623SN/A{
2142798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2152798Sktlim@umich.edu    _status = SwitchedOut;
2162623SN/A
2172798Sktlim@umich.edu    tickEvent.squash();
2182623SN/A}
2192623SN/A
2202623SN/A
2212623SN/Avoid
2222623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2232623SN/A{
2244192Sktlim@umich.edu    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
2252623SN/A
2262623SN/A    assert(!tickEvent.scheduled());
2272623SN/A
2282680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2292623SN/A    // running and schedule its tick event.
2302680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2312680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2322680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2332623SN/A            _status = Running;
2343495Sktlim@umich.edu            tickEvent.schedule(nextCycle());
2352623SN/A            break;
2362623SN/A        }
2372623SN/A    }
2383512Sktlim@umich.edu    if (_status != Running) {
2393512Sktlim@umich.edu        _status = Idle;
2403512Sktlim@umich.edu    }
2415169Ssaidi@eecs.umich.edu    assert(threadContexts.size() == 1);
2425169Ssaidi@eecs.umich.edu    cpuId = tc->readCpuId();
2432623SN/A}
2442623SN/A
2452623SN/A
2462623SN/Avoid
2472623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2482623SN/A{
2494940Snate@binkert.org    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
2504940Snate@binkert.org
2512623SN/A    assert(thread_num == 0);
2522683Sktlim@umich.edu    assert(thread);
2532623SN/A
2542623SN/A    assert(_status == Idle);
2552623SN/A    assert(!tickEvent.scheduled());
2562623SN/A
2572623SN/A    notIdleFraction++;
2585101Ssaidi@eecs.umich.edu    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
2593686Sktlim@umich.edu
2603430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2615100Ssaidi@eecs.umich.edu    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
2622623SN/A    _status = Running;
2632623SN/A}
2642623SN/A
2652623SN/A
2662623SN/Avoid
2672623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2682623SN/A{
2694940Snate@binkert.org    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
2704940Snate@binkert.org
2712623SN/A    assert(thread_num == 0);
2722683Sktlim@umich.edu    assert(thread);
2732623SN/A
2742623SN/A    assert(_status == Running);
2752626SN/A
2762626SN/A    // tick event may not be scheduled if this gets called from inside
2772626SN/A    // an instruction's execution, e.g. "quiesce"
2782626SN/A    if (tickEvent.scheduled())
2792626SN/A        tickEvent.deschedule();
2802623SN/A
2812623SN/A    notIdleFraction--;
2822623SN/A    _status = Idle;
2832623SN/A}
2842623SN/A
2852623SN/A
2862623SN/Atemplate <class T>
2872623SN/AFault
2882623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2892623SN/A{
2903169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2914870Sstever@eecs.umich.edu    Request *req = &data_read_req;
2922623SN/A
2932623SN/A    if (traceData) {
2942623SN/A        traceData->setAddr(addr);
2952623SN/A    }
2962623SN/A
2974999Sgblack@eecs.umich.edu    //The block size of our peer.
2984999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
2994999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
3004999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
3012623SN/A
3024999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
3032623SN/A
3044999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3054999Sgblack@eecs.umich.edu    //across a cache line boundary.
3064999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
3074999Sgblack@eecs.umich.edu
3084999Sgblack@eecs.umich.edu    if(secondAddr > addr)
3094999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
3104999Sgblack@eecs.umich.edu
3114999Sgblack@eecs.umich.edu    dcache_latency = 0;
3124999Sgblack@eecs.umich.edu
3134999Sgblack@eecs.umich.edu    while(1) {
3144999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
3154999Sgblack@eecs.umich.edu
3164999Sgblack@eecs.umich.edu        // translate to physical address
3174999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataReadReq(req);
3184999Sgblack@eecs.umich.edu
3194999Sgblack@eecs.umich.edu        // Now do the access.
3204999Sgblack@eecs.umich.edu        if (fault == NoFault) {
3214999Sgblack@eecs.umich.edu            Packet pkt = Packet(req,
3224999Sgblack@eecs.umich.edu                    req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
3234999Sgblack@eecs.umich.edu                    Packet::Broadcast);
3244999Sgblack@eecs.umich.edu            pkt.dataStatic(dataPtr);
3254999Sgblack@eecs.umich.edu
3264999Sgblack@eecs.umich.edu            if (req->isMmapedIpr())
3274999Sgblack@eecs.umich.edu                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
3284999Sgblack@eecs.umich.edu            else {
3294999Sgblack@eecs.umich.edu                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
3304999Sgblack@eecs.umich.edu                    dcache_latency += physmemPort.sendAtomic(&pkt);
3314999Sgblack@eecs.umich.edu                else
3324999Sgblack@eecs.umich.edu                    dcache_latency += dcachePort.sendAtomic(&pkt);
3334999Sgblack@eecs.umich.edu            }
3344999Sgblack@eecs.umich.edu            dcache_access = true;
3355012Sgblack@eecs.umich.edu
3364999Sgblack@eecs.umich.edu            assert(!pkt.isError());
3374999Sgblack@eecs.umich.edu
3384999Sgblack@eecs.umich.edu            if (req->isLocked()) {
3394999Sgblack@eecs.umich.edu                TheISA::handleLockedRead(thread, req);
3404999Sgblack@eecs.umich.edu            }
3414968Sacolyte@umich.edu        }
3424986Ssaidi@eecs.umich.edu
3434999Sgblack@eecs.umich.edu        // This will need a new way to tell if it has a dcache attached.
3444999Sgblack@eecs.umich.edu        if (req->isUncacheable())
3454999Sgblack@eecs.umich.edu            recordEvent("Uncached Read");
3464762Snate@binkert.org
3474999Sgblack@eecs.umich.edu        //If there's a fault, return it
3484999Sgblack@eecs.umich.edu        if (fault != NoFault)
3494999Sgblack@eecs.umich.edu            return fault;
3504999Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
3514999Sgblack@eecs.umich.edu        if (secondAddr <= addr)
3524999Sgblack@eecs.umich.edu        {
3534999Sgblack@eecs.umich.edu            data = gtoh(data);
3544999Sgblack@eecs.umich.edu            return fault;
3554968Sacolyte@umich.edu        }
3563170Sstever@eecs.umich.edu
3574999Sgblack@eecs.umich.edu        /*
3584999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
3594999Sgblack@eecs.umich.edu         */
3604999Sgblack@eecs.umich.edu
3614999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
3624999Sgblack@eecs.umich.edu        dataPtr += dataSize;
3634999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
3644999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
3654999Sgblack@eecs.umich.edu        //And access the right address.
3664999Sgblack@eecs.umich.edu        addr = secondAddr;
3672623SN/A    }
3682623SN/A}
3692623SN/A
3705177Sgblack@eecs.umich.eduFault
3715177Sgblack@eecs.umich.eduAtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
3725177Sgblack@eecs.umich.edu        int size, unsigned flags)
3735177Sgblack@eecs.umich.edu{
3745177Sgblack@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
3755177Sgblack@eecs.umich.edu    Request *req = &data_read_req;
3765177Sgblack@eecs.umich.edu
3775177Sgblack@eecs.umich.edu    if (traceData) {
3785177Sgblack@eecs.umich.edu        traceData->setAddr(vaddr);
3795177Sgblack@eecs.umich.edu    }
3805177Sgblack@eecs.umich.edu
3815177Sgblack@eecs.umich.edu    //The block size of our peer.
3825177Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
3835177Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
3845177Sgblack@eecs.umich.edu    int dataSize = size;
3855177Sgblack@eecs.umich.edu
3865177Sgblack@eecs.umich.edu    bool firstTimeThrough = true;
3875177Sgblack@eecs.umich.edu
3885177Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3895177Sgblack@eecs.umich.edu    //across a cache line boundary.
3905177Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
3915177Sgblack@eecs.umich.edu
3925177Sgblack@eecs.umich.edu    if(secondAddr > vaddr)
3935177Sgblack@eecs.umich.edu        dataSize = secondAddr - vaddr;
3945177Sgblack@eecs.umich.edu
3955177Sgblack@eecs.umich.edu    while(1) {
3965177Sgblack@eecs.umich.edu        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
3975177Sgblack@eecs.umich.edu
3985177Sgblack@eecs.umich.edu        // translate to physical address
3995177Sgblack@eecs.umich.edu        Fault fault = thread->translateDataReadReq(req);
4005177Sgblack@eecs.umich.edu
4015177Sgblack@eecs.umich.edu        //If there's a fault, return it
4025177Sgblack@eecs.umich.edu        if (fault != NoFault)
4035177Sgblack@eecs.umich.edu            return fault;
4045177Sgblack@eecs.umich.edu
4055177Sgblack@eecs.umich.edu        if (firstTimeThrough) {
4065177Sgblack@eecs.umich.edu            paddr = req->getPaddr();
4075177Sgblack@eecs.umich.edu            firstTimeThrough = false;
4085177Sgblack@eecs.umich.edu        }
4095177Sgblack@eecs.umich.edu
4105177Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
4115177Sgblack@eecs.umich.edu        if (secondAddr <= vaddr)
4125177Sgblack@eecs.umich.edu            return fault;
4135177Sgblack@eecs.umich.edu
4145177Sgblack@eecs.umich.edu        /*
4155177Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
4165177Sgblack@eecs.umich.edu         */
4175177Sgblack@eecs.umich.edu
4185177Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
4195177Sgblack@eecs.umich.edu        dataSize = vaddr + size - secondAddr;
4205177Sgblack@eecs.umich.edu        //And access the right address.
4215177Sgblack@eecs.umich.edu        vaddr = secondAddr;
4225177Sgblack@eecs.umich.edu    }
4235177Sgblack@eecs.umich.edu}
4245177Sgblack@eecs.umich.edu
4252623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
4262623SN/A
4272623SN/Atemplate
4282623SN/AFault
4294115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
4304115Ssaidi@eecs.umich.edu
4314115Ssaidi@eecs.umich.edutemplate
4324115Ssaidi@eecs.umich.eduFault
4334040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
4344040Ssaidi@eecs.umich.edu
4354040Ssaidi@eecs.umich.edutemplate
4364040Ssaidi@eecs.umich.eduFault
4372623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
4382623SN/A
4392623SN/Atemplate
4402623SN/AFault
4412623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
4422623SN/A
4432623SN/Atemplate
4442623SN/AFault
4452623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
4462623SN/A
4472623SN/Atemplate
4482623SN/AFault
4492623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
4502623SN/A
4512623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
4522623SN/A
4532623SN/Atemplate<>
4542623SN/AFault
4552623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
4562623SN/A{
4572623SN/A    return read(addr, *(uint64_t*)&data, flags);
4582623SN/A}
4592623SN/A
4602623SN/Atemplate<>
4612623SN/AFault
4622623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
4632623SN/A{
4642623SN/A    return read(addr, *(uint32_t*)&data, flags);
4652623SN/A}
4662623SN/A
4672623SN/A
4682623SN/Atemplate<>
4692623SN/AFault
4702623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
4712623SN/A{
4722623SN/A    return read(addr, (uint32_t&)data, flags);
4732623SN/A}
4742623SN/A
4752623SN/A
4762623SN/Atemplate <class T>
4772623SN/AFault
4782623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
4792623SN/A{
4803169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
4814870Sstever@eecs.umich.edu    Request *req = &data_write_req;
4822623SN/A
4832623SN/A    if (traceData) {
4842623SN/A        traceData->setAddr(addr);
4852623SN/A    }
4862623SN/A
4874999Sgblack@eecs.umich.edu    //The block size of our peer.
4884999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
4894999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
4904999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
4912623SN/A
4924999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
4932623SN/A
4944999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
4954999Sgblack@eecs.umich.edu    //across a cache line boundary.
4964999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
4974999Sgblack@eecs.umich.edu
4984999Sgblack@eecs.umich.edu    if(secondAddr > addr)
4994999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
5004999Sgblack@eecs.umich.edu
5014999Sgblack@eecs.umich.edu    dcache_latency = 0;
5024999Sgblack@eecs.umich.edu
5034999Sgblack@eecs.umich.edu    while(1) {
5044999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
5054999Sgblack@eecs.umich.edu
5064999Sgblack@eecs.umich.edu        // translate to physical address
5074999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataWriteReq(req);
5084999Sgblack@eecs.umich.edu
5094999Sgblack@eecs.umich.edu        // Now do the access.
5104999Sgblack@eecs.umich.edu        if (fault == NoFault) {
5114999Sgblack@eecs.umich.edu            MemCmd cmd = MemCmd::WriteReq; // default
5124999Sgblack@eecs.umich.edu            bool do_access = true;  // flag to suppress cache access
5134999Sgblack@eecs.umich.edu
5144999Sgblack@eecs.umich.edu            if (req->isLocked()) {
5154999Sgblack@eecs.umich.edu                cmd = MemCmd::StoreCondReq;
5164999Sgblack@eecs.umich.edu                do_access = TheISA::handleLockedWrite(thread, req);
5174999Sgblack@eecs.umich.edu            } else if (req->isSwap()) {
5184999Sgblack@eecs.umich.edu                cmd = MemCmd::SwapReq;
5194999Sgblack@eecs.umich.edu                if (req->isCondSwap()) {
5204999Sgblack@eecs.umich.edu                    assert(res);
5214999Sgblack@eecs.umich.edu                    req->setExtraData(*res);
5224999Sgblack@eecs.umich.edu                }
5234999Sgblack@eecs.umich.edu            }
5244999Sgblack@eecs.umich.edu
5254999Sgblack@eecs.umich.edu            if (do_access) {
5264999Sgblack@eecs.umich.edu                Packet pkt = Packet(req, cmd, Packet::Broadcast);
5274999Sgblack@eecs.umich.edu                pkt.dataStatic(dataPtr);
5284999Sgblack@eecs.umich.edu
5294999Sgblack@eecs.umich.edu                if (req->isMmapedIpr()) {
5304999Sgblack@eecs.umich.edu                    dcache_latency +=
5314999Sgblack@eecs.umich.edu                        TheISA::handleIprWrite(thread->getTC(), &pkt);
5324999Sgblack@eecs.umich.edu                } else {
5334999Sgblack@eecs.umich.edu                    //XXX This needs to be outside of the loop in order to
5344999Sgblack@eecs.umich.edu                    //work properly for cache line boundary crossing
5354999Sgblack@eecs.umich.edu                    //accesses in transendian simulations.
5364999Sgblack@eecs.umich.edu                    data = htog(data);
5374999Sgblack@eecs.umich.edu                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
5384999Sgblack@eecs.umich.edu                        dcache_latency += physmemPort.sendAtomic(&pkt);
5394999Sgblack@eecs.umich.edu                    else
5404999Sgblack@eecs.umich.edu                        dcache_latency += dcachePort.sendAtomic(&pkt);
5414999Sgblack@eecs.umich.edu                }
5424999Sgblack@eecs.umich.edu                dcache_access = true;
5434999Sgblack@eecs.umich.edu                assert(!pkt.isError());
5444999Sgblack@eecs.umich.edu
5454999Sgblack@eecs.umich.edu                if (req->isSwap()) {
5464999Sgblack@eecs.umich.edu                    assert(res);
5474999Sgblack@eecs.umich.edu                    *res = pkt.get<T>();
5484999Sgblack@eecs.umich.edu                }
5494999Sgblack@eecs.umich.edu            }
5504999Sgblack@eecs.umich.edu
5514999Sgblack@eecs.umich.edu            if (res && !req->isSwap()) {
5524999Sgblack@eecs.umich.edu                *res = req->getExtraData();
5534878Sstever@eecs.umich.edu            }
5544040Ssaidi@eecs.umich.edu        }
5554040Ssaidi@eecs.umich.edu
5564999Sgblack@eecs.umich.edu        // This will need a new way to tell if it's hooked up to a cache or not.
5574999Sgblack@eecs.umich.edu        if (req->isUncacheable())
5584999Sgblack@eecs.umich.edu            recordEvent("Uncached Write");
5592631SN/A
5604999Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
5614999Sgblack@eecs.umich.edu        //stop now.
5624999Sgblack@eecs.umich.edu        if (fault != NoFault || secondAddr <= addr)
5634999Sgblack@eecs.umich.edu        {
5644999Sgblack@eecs.umich.edu            // If the write needs to have a fault on the access, consider
5654999Sgblack@eecs.umich.edu            // calling changeStatus() and changing it to "bad addr write"
5664999Sgblack@eecs.umich.edu            // or something.
5674999Sgblack@eecs.umich.edu            return fault;
5683170Sstever@eecs.umich.edu        }
5693170Sstever@eecs.umich.edu
5704999Sgblack@eecs.umich.edu        /*
5714999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
5724999Sgblack@eecs.umich.edu         */
5734999Sgblack@eecs.umich.edu
5744999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
5754999Sgblack@eecs.umich.edu        dataPtr += dataSize;
5764999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
5774999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
5784999Sgblack@eecs.umich.edu        //And access the right address.
5794999Sgblack@eecs.umich.edu        addr = secondAddr;
5802623SN/A    }
5812623SN/A}
5822623SN/A
5835177Sgblack@eecs.umich.eduFault
5845177Sgblack@eecs.umich.eduAtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
5855177Sgblack@eecs.umich.edu        int size, unsigned flags)
5865177Sgblack@eecs.umich.edu{
5875177Sgblack@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
5885177Sgblack@eecs.umich.edu    Request *req = &data_write_req;
5895177Sgblack@eecs.umich.edu
5905177Sgblack@eecs.umich.edu    if (traceData) {
5915177Sgblack@eecs.umich.edu        traceData->setAddr(vaddr);
5925177Sgblack@eecs.umich.edu    }
5935177Sgblack@eecs.umich.edu
5945177Sgblack@eecs.umich.edu    //The block size of our peer.
5955177Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
5965177Sgblack@eecs.umich.edu
5975177Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
5985177Sgblack@eecs.umich.edu    //across a cache line boundary.
5995177Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
6005177Sgblack@eecs.umich.edu
6015177Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
6025177Sgblack@eecs.umich.edu    int dataSize = size;
6035177Sgblack@eecs.umich.edu
6045177Sgblack@eecs.umich.edu    bool firstTimeThrough = true;
6055177Sgblack@eecs.umich.edu
6065177Sgblack@eecs.umich.edu    if(secondAddr > vaddr)
6075177Sgblack@eecs.umich.edu        dataSize = secondAddr - vaddr;
6085177Sgblack@eecs.umich.edu
6095177Sgblack@eecs.umich.edu    dcache_latency = 0;
6105177Sgblack@eecs.umich.edu
6115177Sgblack@eecs.umich.edu    while(1) {
6125278Sgblack@eecs.umich.edu        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
6135177Sgblack@eecs.umich.edu
6145177Sgblack@eecs.umich.edu        // translate to physical address
6155177Sgblack@eecs.umich.edu        Fault fault = thread->translateDataWriteReq(req);
6165177Sgblack@eecs.umich.edu
6175177Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
6185177Sgblack@eecs.umich.edu        //stop now.
6195177Sgblack@eecs.umich.edu        if (fault != NoFault)
6205177Sgblack@eecs.umich.edu            return fault;
6215177Sgblack@eecs.umich.edu
6225177Sgblack@eecs.umich.edu        if (firstTimeThrough) {
6235177Sgblack@eecs.umich.edu            paddr = req->getPaddr();
6245177Sgblack@eecs.umich.edu            firstTimeThrough = false;
6255177Sgblack@eecs.umich.edu        }
6265177Sgblack@eecs.umich.edu
6275177Sgblack@eecs.umich.edu        if (secondAddr <= vaddr)
6285177Sgblack@eecs.umich.edu            return fault;
6295177Sgblack@eecs.umich.edu
6305177Sgblack@eecs.umich.edu        /*
6315177Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
6325177Sgblack@eecs.umich.edu         */
6335177Sgblack@eecs.umich.edu
6345177Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
6355177Sgblack@eecs.umich.edu        dataSize = vaddr + size - secondAddr;
6365177Sgblack@eecs.umich.edu        //And access the right address.
6375177Sgblack@eecs.umich.edu        vaddr = secondAddr;
6385177Sgblack@eecs.umich.edu    }
6395177Sgblack@eecs.umich.edu}
6405177Sgblack@eecs.umich.edu
6412623SN/A
6422623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
6434224Sgblack@eecs.umich.edu
6444224Sgblack@eecs.umich.edutemplate
6454224Sgblack@eecs.umich.eduFault
6464224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr,
6474224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
6484224Sgblack@eecs.umich.edu
6494224Sgblack@eecs.umich.edutemplate
6504224Sgblack@eecs.umich.eduFault
6514224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr,
6524224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
6534224Sgblack@eecs.umich.edu
6542623SN/Atemplate
6552623SN/AFault
6562623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
6572623SN/A                       unsigned flags, uint64_t *res);
6582623SN/A
6592623SN/Atemplate
6602623SN/AFault
6612623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
6622623SN/A                       unsigned flags, uint64_t *res);
6632623SN/A
6642623SN/Atemplate
6652623SN/AFault
6662623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
6672623SN/A                       unsigned flags, uint64_t *res);
6682623SN/A
6692623SN/Atemplate
6702623SN/AFault
6712623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
6722623SN/A                       unsigned flags, uint64_t *res);
6732623SN/A
6742623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
6752623SN/A
6762623SN/Atemplate<>
6772623SN/AFault
6782623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
6792623SN/A{
6802623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
6812623SN/A}
6822623SN/A
6832623SN/Atemplate<>
6842623SN/AFault
6852623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
6862623SN/A{
6872623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
6882623SN/A}
6892623SN/A
6902623SN/A
6912623SN/Atemplate<>
6922623SN/AFault
6932623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
6942623SN/A{
6952623SN/A    return write((uint32_t)data, addr, flags, res);
6962623SN/A}
6972623SN/A
6982623SN/A
6992623SN/Avoid
7002623SN/AAtomicSimpleCPU::tick()
7012623SN/A{
7024940Snate@binkert.org    DPRINTF(SimpleCPU, "Tick\n");
7034940Snate@binkert.org
7045100Ssaidi@eecs.umich.edu    Tick latency = ticks(1); // instruction takes one cycle by default
7052623SN/A
7062623SN/A    for (int i = 0; i < width; ++i) {
7072623SN/A        numCycles++;
7082623SN/A
7093387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
7103387Sgblack@eecs.umich.edu            checkForInterrupts();
7112626SN/A
7124870Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(&ifetch_req);
7132623SN/A
7142623SN/A        if (fault == NoFault) {
7154182Sgblack@eecs.umich.edu            Tick icache_latency = 0;
7164182Sgblack@eecs.umich.edu            bool icache_access = false;
7174182Sgblack@eecs.umich.edu            dcache_access = false; // assume no dcache access
7182662Sstever@eecs.umich.edu
7194182Sgblack@eecs.umich.edu            //Fetch more instruction memory if necessary
7204593Sgblack@eecs.umich.edu            //if(predecoder.needMoreBytes())
7214593Sgblack@eecs.umich.edu            //{
7224182Sgblack@eecs.umich.edu                icache_access = true;
7234870Sstever@eecs.umich.edu                Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
7244870Sstever@eecs.umich.edu                                           Packet::Broadcast);
7254870Sstever@eecs.umich.edu                ifetch_pkt.dataStatic(&inst);
7262623SN/A
7274968Sacolyte@umich.edu                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
7284968Sacolyte@umich.edu                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
7294968Sacolyte@umich.edu                else
7304968Sacolyte@umich.edu                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
7314968Sacolyte@umich.edu
7324986Ssaidi@eecs.umich.edu                assert(!ifetch_pkt.isError());
7334968Sacolyte@umich.edu
7344182Sgblack@eecs.umich.edu                // ifetch_req is initialized to read the instruction directly
7354182Sgblack@eecs.umich.edu                // into the CPU object's inst field.
7364593Sgblack@eecs.umich.edu            //}
7374182Sgblack@eecs.umich.edu
7382623SN/A            preExecute();
7393814Ssaidi@eecs.umich.edu
7405001Sgblack@eecs.umich.edu            if (curStaticInst) {
7414182Sgblack@eecs.umich.edu                fault = curStaticInst->execute(this, traceData);
7424998Sgblack@eecs.umich.edu
7434998Sgblack@eecs.umich.edu                // keep an instruction count
7444998Sgblack@eecs.umich.edu                if (fault == NoFault)
7454998Sgblack@eecs.umich.edu                    countInst();
7465001Sgblack@eecs.umich.edu                else if (traceData) {
7475001Sgblack@eecs.umich.edu                    // If there was a fault, we should trace this instruction.
7485001Sgblack@eecs.umich.edu                    delete traceData;
7495001Sgblack@eecs.umich.edu                    traceData = NULL;
7505001Sgblack@eecs.umich.edu                }
7514998Sgblack@eecs.umich.edu
7524182Sgblack@eecs.umich.edu                postExecute();
7534182Sgblack@eecs.umich.edu            }
7542623SN/A
7553814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
7564539Sgblack@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroop() ||
7574539Sgblack@eecs.umich.edu                        curStaticInst->isFirstMicroop()))
7583814Ssaidi@eecs.umich.edu                instCnt++;
7593814Ssaidi@eecs.umich.edu
7602623SN/A            if (simulate_stalls) {
7614182Sgblack@eecs.umich.edu                Tick icache_stall =
7625100Ssaidi@eecs.umich.edu                    icache_access ? icache_latency - ticks(1) : 0;
7632623SN/A                Tick dcache_stall =
7645100Ssaidi@eecs.umich.edu                    dcache_access ? dcache_latency - ticks(1) : 0;
7655100Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
7665100Ssaidi@eecs.umich.edu                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
7675100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles+1);
7682803Ssaidi@eecs.umich.edu                else
7695100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles);
7702623SN/A            }
7712623SN/A
7722623SN/A        }
7734377Sgblack@eecs.umich.edu        if(fault != NoFault || !stayAtPC)
7744182Sgblack@eecs.umich.edu            advancePC(fault);
7752623SN/A    }
7762623SN/A
7772626SN/A    if (_status != Idle)
7782626SN/A        tickEvent.schedule(curTick + latency);
7792623SN/A}
7802623SN/A
7812623SN/A
7822623SN/A////////////////////////////////////////////////////////////////////////
7832623SN/A//
7842623SN/A//  AtomicSimpleCPU Simulation Object
7852623SN/A//
7864762Snate@binkert.orgAtomicSimpleCPU *
7874762Snate@binkert.orgAtomicSimpleCPUParams::create()
7882623SN/A{
7892623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
7904762Snate@binkert.org    params->name = name;
7912623SN/A    params->numberOfThreads = 1;
7922623SN/A    params->max_insts_any_thread = max_insts_any_thread;
7932623SN/A    params->max_insts_all_threads = max_insts_all_threads;
7942623SN/A    params->max_loads_any_thread = max_loads_any_thread;
7952623SN/A    params->max_loads_all_threads = max_loads_all_threads;
7963119Sktlim@umich.edu    params->progress_interval = progress_interval;
7972623SN/A    params->deferRegistration = defer_registration;
7983661Srdreslin@umich.edu    params->phase = phase;
7992623SN/A    params->clock = clock;
8002623SN/A    params->functionTrace = function_trace;
8012623SN/A    params->functionTraceStart = function_trace_start;
8022623SN/A    params->width = width;
8032623SN/A    params->simulate_stalls = simulate_stalls;
8042901Ssaidi@eecs.umich.edu    params->system = system;
8053170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
8064776Sgblack@eecs.umich.edu    params->tracer = tracer;
8072623SN/A
8082623SN/A    params->itb = itb;
8092623SN/A    params->dtb = dtb;
8104997Sgblack@eecs.umich.edu#if FULL_SYSTEM
8112623SN/A    params->profile = profile;
8123617Sbinkertn@umich.edu    params->do_quiesce = do_quiesce;
8133617Sbinkertn@umich.edu    params->do_checkpoint_insts = do_checkpoint_insts;
8143617Sbinkertn@umich.edu    params->do_statistics_insts = do_statistics_insts;
8152623SN/A#else
8164762Snate@binkert.org    if (workload.size() != 1)
8174762Snate@binkert.org        panic("only one workload allowed");
8184762Snate@binkert.org    params->process = workload[0];
8192623SN/A#endif
8202623SN/A
8212623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
8222623SN/A    return cpu;
8232623SN/A}
824