atomic.cc revision 5100
12623SN/A/*
22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32623SN/A * All rights reserved.
42623SN/A *
52623SN/A * Redistribution and use in source and binary forms, with or without
62623SN/A * modification, are permitted provided that the following conditions are
72623SN/A * met: redistributions of source code must retain the above copyright
82623SN/A * notice, this list of conditions and the following disclaimer;
92623SN/A * redistributions in binary form must reproduce the above copyright
102623SN/A * notice, this list of conditions and the following disclaimer in the
112623SN/A * documentation and/or other materials provided with the distribution;
122623SN/A * neither the name of the copyright holders nor the names of its
132623SN/A * contributors may be used to endorse or promote products derived from
142623SN/A * this software without specific prior written permission.
152623SN/A *
162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292623SN/A */
302623SN/A
313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh"
323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh"
332623SN/A#include "arch/utility.hh"
344040Ssaidi@eecs.umich.edu#include "base/bigint.hh"
352623SN/A#include "cpu/exetrace.hh"
362623SN/A#include "cpu/simple/atomic.hh"
373348Sbinkertn@umich.edu#include "mem/packet.hh"
383348Sbinkertn@umich.edu#include "mem/packet_access.hh"
394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh"
402901Ssaidi@eecs.umich.edu#include "sim/system.hh"
412623SN/A
422623SN/Ausing namespace std;
432623SN/Ausing namespace TheISA;
442623SN/A
452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
462623SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
472623SN/A{
482623SN/A}
492623SN/A
502623SN/A
512623SN/Avoid
522623SN/AAtomicSimpleCPU::TickEvent::process()
532623SN/A{
542623SN/A    cpu->tick();
552623SN/A}
562623SN/A
572623SN/Aconst char *
582623SN/AAtomicSimpleCPU::TickEvent::description()
592623SN/A{
604873Sstever@eecs.umich.edu    return "AtomicSimpleCPU tick";
612623SN/A}
622623SN/A
632856Srdreslin@umich.eduPort *
642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx)
652856Srdreslin@umich.edu{
662856Srdreslin@umich.edu    if (if_name == "dcache_port")
672856Srdreslin@umich.edu        return &dcachePort;
682856Srdreslin@umich.edu    else if (if_name == "icache_port")
692856Srdreslin@umich.edu        return &icachePort;
704968Sacolyte@umich.edu    else if (if_name == "physmem_port") {
714968Sacolyte@umich.edu        hasPhysMemPort = true;
724968Sacolyte@umich.edu        return &physmemPort;
734968Sacolyte@umich.edu    }
742856Srdreslin@umich.edu    else
752856Srdreslin@umich.edu        panic("No Such Port\n");
762856Srdreslin@umich.edu}
772623SN/A
782623SN/Avoid
792623SN/AAtomicSimpleCPU::init()
802623SN/A{
812623SN/A    BaseCPU::init();
822623SN/A#if FULL_SYSTEM
832680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
842680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
852623SN/A
862623SN/A        // initialize CPU, including PC
872680Sktlim@umich.edu        TheISA::initCPU(tc, tc->readCpuId());
882623SN/A    }
892623SN/A#endif
904968Sacolyte@umich.edu    if (hasPhysMemPort) {
914968Sacolyte@umich.edu        bool snoop = false;
924968Sacolyte@umich.edu        AddrRangeList pmAddrList;
934968Sacolyte@umich.edu        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
944968Sacolyte@umich.edu        physMemAddr = *pmAddrList.begin();
954968Sacolyte@umich.edu    }
962623SN/A}
972623SN/A
982623SN/Abool
993349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
1002623SN/A{
1013184Srdreslin@umich.edu    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
1022623SN/A    return true;
1032623SN/A}
1042623SN/A
1052623SN/ATick
1063349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
1072623SN/A{
1083310Srdreslin@umich.edu    //Snooping a coherence request, just return
1093649Srdreslin@umich.edu    return 0;
1102623SN/A}
1112623SN/A
1122623SN/Avoid
1133349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
1142623SN/A{
1153184Srdreslin@umich.edu    //No internal storage to update, just return
1163184Srdreslin@umich.edu    return;
1172623SN/A}
1182623SN/A
1192623SN/Avoid
1202623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
1212623SN/A{
1223647Srdreslin@umich.edu    if (status == RangeChange) {
1233647Srdreslin@umich.edu        if (!snoopRangeSent) {
1243647Srdreslin@umich.edu            snoopRangeSent = true;
1253647Srdreslin@umich.edu            sendStatusChange(Port::RangeChange);
1263647Srdreslin@umich.edu        }
1272626SN/A        return;
1283647Srdreslin@umich.edu    }
1292626SN/A
1302623SN/A    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
1312623SN/A}
1322623SN/A
1332657Ssaidi@eecs.umich.eduvoid
1342623SN/AAtomicSimpleCPU::CpuPort::recvRetry()
1352623SN/A{
1362623SN/A    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
1372623SN/A}
1382623SN/A
1394192Sktlim@umich.eduvoid
1404192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port)
1414192Sktlim@umich.edu{
1424192Sktlim@umich.edu    Port::setPeer(port);
1434192Sktlim@umich.edu
1444192Sktlim@umich.edu#if FULL_SYSTEM
1454192Sktlim@umich.edu    // Update the ThreadContext's memory ports (Functional/Virtual
1464192Sktlim@umich.edu    // Ports)
1474192Sktlim@umich.edu    cpu->tcBase()->connectMemPorts();
1484192Sktlim@umich.edu#endif
1494192Sktlim@umich.edu}
1502623SN/A
1512623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p)
1522623SN/A    : BaseSimpleCPU(p), tickEvent(this),
1532623SN/A      width(p->width), simulate_stalls(p->simulate_stalls),
1544968Sacolyte@umich.edu      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
1554968Sacolyte@umich.edu      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
1562623SN/A{
1572623SN/A    _status = Idle;
1582623SN/A
1593647Srdreslin@umich.edu    icachePort.snoopRangeSent = false;
1603647Srdreslin@umich.edu    dcachePort.snoopRangeSent = false;
1613647Srdreslin@umich.edu
1624870Sstever@eecs.umich.edu    ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
1634870Sstever@eecs.umich.edu    data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
1644870Sstever@eecs.umich.edu    data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
1652623SN/A}
1662623SN/A
1672623SN/A
1682623SN/AAtomicSimpleCPU::~AtomicSimpleCPU()
1692623SN/A{
1702623SN/A}
1712623SN/A
1722623SN/Avoid
1732623SN/AAtomicSimpleCPU::serialize(ostream &os)
1742623SN/A{
1752915Sktlim@umich.edu    SimObject::State so_state = SimObject::getState();
1762915Sktlim@umich.edu    SERIALIZE_ENUM(so_state);
1773177Shsul@eecs.umich.edu    Status _status = status();
1783177Shsul@eecs.umich.edu    SERIALIZE_ENUM(_status);
1793145Shsul@eecs.umich.edu    BaseSimpleCPU::serialize(os);
1802623SN/A    nameOut(os, csprintf("%s.tickEvent", name()));
1812623SN/A    tickEvent.serialize(os);
1822623SN/A}
1832623SN/A
1842623SN/Avoid
1852623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1862623SN/A{
1872915Sktlim@umich.edu    SimObject::State so_state;
1882915Sktlim@umich.edu    UNSERIALIZE_ENUM(so_state);
1893177Shsul@eecs.umich.edu    UNSERIALIZE_ENUM(_status);
1903145Shsul@eecs.umich.edu    BaseSimpleCPU::unserialize(cp, section);
1912915Sktlim@umich.edu    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1922915Sktlim@umich.edu}
1932915Sktlim@umich.edu
1942915Sktlim@umich.eduvoid
1952915Sktlim@umich.eduAtomicSimpleCPU::resume()
1962915Sktlim@umich.edu{
1974940Snate@binkert.org    DPRINTF(SimpleCPU, "Resume\n");
1983324Shsul@eecs.umich.edu    if (_status != SwitchedOut && _status != Idle) {
1994762Snate@binkert.org        assert(system->getMemoryMode() == Enums::atomic);
2003324Shsul@eecs.umich.edu
2013324Shsul@eecs.umich.edu        changeState(SimObject::Running);
2023324Shsul@eecs.umich.edu        if (thread->status() == ThreadContext::Active) {
2033431Sgblack@eecs.umich.edu            if (!tickEvent.scheduled()) {
2043495Sktlim@umich.edu                tickEvent.schedule(nextCycle());
2053431Sgblack@eecs.umich.edu            }
2063324Shsul@eecs.umich.edu        }
2072915Sktlim@umich.edu    }
2082623SN/A}
2092623SN/A
2102623SN/Avoid
2112798Sktlim@umich.eduAtomicSimpleCPU::switchOut()
2122623SN/A{
2132798Sktlim@umich.edu    assert(status() == Running || status() == Idle);
2142798Sktlim@umich.edu    _status = SwitchedOut;
2152623SN/A
2162798Sktlim@umich.edu    tickEvent.squash();
2172623SN/A}
2182623SN/A
2192623SN/A
2202623SN/Avoid
2212623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
2222623SN/A{
2234192Sktlim@umich.edu    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
2242623SN/A
2252623SN/A    assert(!tickEvent.scheduled());
2262623SN/A
2272680Sktlim@umich.edu    // if any of this CPU's ThreadContexts are active, mark the CPU as
2282623SN/A    // running and schedule its tick event.
2292680Sktlim@umich.edu    for (int i = 0; i < threadContexts.size(); ++i) {
2302680Sktlim@umich.edu        ThreadContext *tc = threadContexts[i];
2312680Sktlim@umich.edu        if (tc->status() == ThreadContext::Active && _status != Running) {
2322623SN/A            _status = Running;
2333495Sktlim@umich.edu            tickEvent.schedule(nextCycle());
2342623SN/A            break;
2352623SN/A        }
2362623SN/A    }
2373512Sktlim@umich.edu    if (_status != Running) {
2383512Sktlim@umich.edu        _status = Idle;
2393512Sktlim@umich.edu    }
2402623SN/A}
2412623SN/A
2422623SN/A
2432623SN/Avoid
2442623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay)
2452623SN/A{
2464940Snate@binkert.org    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
2474940Snate@binkert.org
2482623SN/A    assert(thread_num == 0);
2492683Sktlim@umich.edu    assert(thread);
2502623SN/A
2512623SN/A    assert(_status == Idle);
2522623SN/A    assert(!tickEvent.scheduled());
2532623SN/A
2542623SN/A    notIdleFraction++;
2553686Sktlim@umich.edu
2563430Sgblack@eecs.umich.edu    //Make sure ticks are still on multiples of cycles
2575100Ssaidi@eecs.umich.edu    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
2582623SN/A    _status = Running;
2592623SN/A}
2602623SN/A
2612623SN/A
2622623SN/Avoid
2632623SN/AAtomicSimpleCPU::suspendContext(int thread_num)
2642623SN/A{
2654940Snate@binkert.org    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
2664940Snate@binkert.org
2672623SN/A    assert(thread_num == 0);
2682683Sktlim@umich.edu    assert(thread);
2692623SN/A
2702623SN/A    assert(_status == Running);
2712626SN/A
2722626SN/A    // tick event may not be scheduled if this gets called from inside
2732626SN/A    // an instruction's execution, e.g. "quiesce"
2742626SN/A    if (tickEvent.scheduled())
2752626SN/A        tickEvent.deschedule();
2762623SN/A
2772623SN/A    notIdleFraction--;
2782623SN/A    _status = Idle;
2792623SN/A}
2802623SN/A
2812623SN/A
2822623SN/Atemplate <class T>
2832623SN/AFault
2842623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
2852623SN/A{
2863169Sstever@eecs.umich.edu    // use the CPU's statically allocated read request and packet objects
2874870Sstever@eecs.umich.edu    Request *req = &data_read_req;
2882623SN/A
2892623SN/A    if (traceData) {
2902623SN/A        traceData->setAddr(addr);
2912623SN/A    }
2922623SN/A
2934999Sgblack@eecs.umich.edu    //The block size of our peer.
2944999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
2954999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
2964999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
2972623SN/A
2984999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
2992623SN/A
3004999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
3014999Sgblack@eecs.umich.edu    //across a cache line boundary.
3024999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
3034999Sgblack@eecs.umich.edu
3044999Sgblack@eecs.umich.edu    if(secondAddr > addr)
3054999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
3064999Sgblack@eecs.umich.edu
3074999Sgblack@eecs.umich.edu    dcache_latency = 0;
3084999Sgblack@eecs.umich.edu
3094999Sgblack@eecs.umich.edu    while(1) {
3104999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
3114999Sgblack@eecs.umich.edu
3124999Sgblack@eecs.umich.edu        // translate to physical address
3134999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataReadReq(req);
3144999Sgblack@eecs.umich.edu
3154999Sgblack@eecs.umich.edu        // Now do the access.
3164999Sgblack@eecs.umich.edu        if (fault == NoFault) {
3174999Sgblack@eecs.umich.edu            Packet pkt = Packet(req,
3184999Sgblack@eecs.umich.edu                    req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
3194999Sgblack@eecs.umich.edu                    Packet::Broadcast);
3204999Sgblack@eecs.umich.edu            pkt.dataStatic(dataPtr);
3214999Sgblack@eecs.umich.edu
3224999Sgblack@eecs.umich.edu            if (req->isMmapedIpr())
3234999Sgblack@eecs.umich.edu                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
3244999Sgblack@eecs.umich.edu            else {
3254999Sgblack@eecs.umich.edu                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
3264999Sgblack@eecs.umich.edu                    dcache_latency += physmemPort.sendAtomic(&pkt);
3274999Sgblack@eecs.umich.edu                else
3284999Sgblack@eecs.umich.edu                    dcache_latency += dcachePort.sendAtomic(&pkt);
3294999Sgblack@eecs.umich.edu            }
3304999Sgblack@eecs.umich.edu            dcache_access = true;
3315012Sgblack@eecs.umich.edu
3324999Sgblack@eecs.umich.edu            assert(!pkt.isError());
3334999Sgblack@eecs.umich.edu
3344999Sgblack@eecs.umich.edu            if (req->isLocked()) {
3354999Sgblack@eecs.umich.edu                TheISA::handleLockedRead(thread, req);
3364999Sgblack@eecs.umich.edu            }
3374968Sacolyte@umich.edu        }
3384986Ssaidi@eecs.umich.edu
3394999Sgblack@eecs.umich.edu        // This will need a new way to tell if it has a dcache attached.
3404999Sgblack@eecs.umich.edu        if (req->isUncacheable())
3414999Sgblack@eecs.umich.edu            recordEvent("Uncached Read");
3424762Snate@binkert.org
3434999Sgblack@eecs.umich.edu        //If there's a fault, return it
3444999Sgblack@eecs.umich.edu        if (fault != NoFault)
3454999Sgblack@eecs.umich.edu            return fault;
3464999Sgblack@eecs.umich.edu        //If we don't need to access a second cache line, stop now.
3474999Sgblack@eecs.umich.edu        if (secondAddr <= addr)
3484999Sgblack@eecs.umich.edu        {
3494999Sgblack@eecs.umich.edu            data = gtoh(data);
3504999Sgblack@eecs.umich.edu            return fault;
3514968Sacolyte@umich.edu        }
3523170Sstever@eecs.umich.edu
3534999Sgblack@eecs.umich.edu        /*
3544999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
3554999Sgblack@eecs.umich.edu         */
3564999Sgblack@eecs.umich.edu
3574999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
3584999Sgblack@eecs.umich.edu        dataPtr += dataSize;
3594999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
3604999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
3614999Sgblack@eecs.umich.edu        //And access the right address.
3624999Sgblack@eecs.umich.edu        addr = secondAddr;
3632623SN/A    }
3642623SN/A}
3652623SN/A
3662623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
3672623SN/A
3682623SN/Atemplate
3692623SN/AFault
3704115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
3714115Ssaidi@eecs.umich.edu
3724115Ssaidi@eecs.umich.edutemplate
3734115Ssaidi@eecs.umich.eduFault
3744040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
3754040Ssaidi@eecs.umich.edu
3764040Ssaidi@eecs.umich.edutemplate
3774040Ssaidi@eecs.umich.eduFault
3782623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
3792623SN/A
3802623SN/Atemplate
3812623SN/AFault
3822623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
3832623SN/A
3842623SN/Atemplate
3852623SN/AFault
3862623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
3872623SN/A
3882623SN/Atemplate
3892623SN/AFault
3902623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
3912623SN/A
3922623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
3932623SN/A
3942623SN/Atemplate<>
3952623SN/AFault
3962623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
3972623SN/A{
3982623SN/A    return read(addr, *(uint64_t*)&data, flags);
3992623SN/A}
4002623SN/A
4012623SN/Atemplate<>
4022623SN/AFault
4032623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
4042623SN/A{
4052623SN/A    return read(addr, *(uint32_t*)&data, flags);
4062623SN/A}
4072623SN/A
4082623SN/A
4092623SN/Atemplate<>
4102623SN/AFault
4112623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
4122623SN/A{
4132623SN/A    return read(addr, (uint32_t&)data, flags);
4142623SN/A}
4152623SN/A
4162623SN/A
4172623SN/Atemplate <class T>
4182623SN/AFault
4192623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
4202623SN/A{
4213169Sstever@eecs.umich.edu    // use the CPU's statically allocated write request and packet objects
4224870Sstever@eecs.umich.edu    Request *req = &data_write_req;
4232623SN/A
4242623SN/A    if (traceData) {
4252623SN/A        traceData->setAddr(addr);
4262623SN/A    }
4272623SN/A
4284999Sgblack@eecs.umich.edu    //The block size of our peer.
4294999Sgblack@eecs.umich.edu    int blockSize = dcachePort.peerBlockSize();
4304999Sgblack@eecs.umich.edu    //The size of the data we're trying to read.
4314999Sgblack@eecs.umich.edu    int dataSize = sizeof(T);
4322623SN/A
4334999Sgblack@eecs.umich.edu    uint8_t * dataPtr = (uint8_t *)&data;
4342623SN/A
4354999Sgblack@eecs.umich.edu    //The address of the second part of this access if it needs to be split
4364999Sgblack@eecs.umich.edu    //across a cache line boundary.
4374999Sgblack@eecs.umich.edu    Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
4384999Sgblack@eecs.umich.edu
4394999Sgblack@eecs.umich.edu    if(secondAddr > addr)
4404999Sgblack@eecs.umich.edu        dataSize = secondAddr - addr;
4414999Sgblack@eecs.umich.edu
4424999Sgblack@eecs.umich.edu    dcache_latency = 0;
4434999Sgblack@eecs.umich.edu
4444999Sgblack@eecs.umich.edu    while(1) {
4454999Sgblack@eecs.umich.edu        req->setVirt(0, addr, dataSize, flags, thread->readPC());
4464999Sgblack@eecs.umich.edu
4474999Sgblack@eecs.umich.edu        // translate to physical address
4484999Sgblack@eecs.umich.edu        Fault fault = thread->translateDataWriteReq(req);
4494999Sgblack@eecs.umich.edu
4504999Sgblack@eecs.umich.edu        // Now do the access.
4514999Sgblack@eecs.umich.edu        if (fault == NoFault) {
4524999Sgblack@eecs.umich.edu            MemCmd cmd = MemCmd::WriteReq; // default
4534999Sgblack@eecs.umich.edu            bool do_access = true;  // flag to suppress cache access
4544999Sgblack@eecs.umich.edu
4554999Sgblack@eecs.umich.edu            if (req->isLocked()) {
4564999Sgblack@eecs.umich.edu                cmd = MemCmd::StoreCondReq;
4574999Sgblack@eecs.umich.edu                do_access = TheISA::handleLockedWrite(thread, req);
4584999Sgblack@eecs.umich.edu            } else if (req->isSwap()) {
4594999Sgblack@eecs.umich.edu                cmd = MemCmd::SwapReq;
4604999Sgblack@eecs.umich.edu                if (req->isCondSwap()) {
4614999Sgblack@eecs.umich.edu                    assert(res);
4624999Sgblack@eecs.umich.edu                    req->setExtraData(*res);
4634999Sgblack@eecs.umich.edu                }
4644999Sgblack@eecs.umich.edu            }
4654999Sgblack@eecs.umich.edu
4664999Sgblack@eecs.umich.edu            if (do_access) {
4674999Sgblack@eecs.umich.edu                Packet pkt = Packet(req, cmd, Packet::Broadcast);
4684999Sgblack@eecs.umich.edu                pkt.dataStatic(dataPtr);
4694999Sgblack@eecs.umich.edu
4704999Sgblack@eecs.umich.edu                if (req->isMmapedIpr()) {
4714999Sgblack@eecs.umich.edu                    dcache_latency +=
4724999Sgblack@eecs.umich.edu                        TheISA::handleIprWrite(thread->getTC(), &pkt);
4734999Sgblack@eecs.umich.edu                } else {
4744999Sgblack@eecs.umich.edu                    //XXX This needs to be outside of the loop in order to
4754999Sgblack@eecs.umich.edu                    //work properly for cache line boundary crossing
4764999Sgblack@eecs.umich.edu                    //accesses in transendian simulations.
4774999Sgblack@eecs.umich.edu                    data = htog(data);
4784999Sgblack@eecs.umich.edu                    if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
4794999Sgblack@eecs.umich.edu                        dcache_latency += physmemPort.sendAtomic(&pkt);
4804999Sgblack@eecs.umich.edu                    else
4814999Sgblack@eecs.umich.edu                        dcache_latency += dcachePort.sendAtomic(&pkt);
4824999Sgblack@eecs.umich.edu                }
4834999Sgblack@eecs.umich.edu                dcache_access = true;
4844999Sgblack@eecs.umich.edu                assert(!pkt.isError());
4854999Sgblack@eecs.umich.edu
4864999Sgblack@eecs.umich.edu                if (req->isSwap()) {
4874999Sgblack@eecs.umich.edu                    assert(res);
4884999Sgblack@eecs.umich.edu                    *res = pkt.get<T>();
4894999Sgblack@eecs.umich.edu                }
4904999Sgblack@eecs.umich.edu            }
4914999Sgblack@eecs.umich.edu
4924999Sgblack@eecs.umich.edu            if (res && !req->isSwap()) {
4934999Sgblack@eecs.umich.edu                *res = req->getExtraData();
4944878Sstever@eecs.umich.edu            }
4954040Ssaidi@eecs.umich.edu        }
4964040Ssaidi@eecs.umich.edu
4974999Sgblack@eecs.umich.edu        // This will need a new way to tell if it's hooked up to a cache or not.
4984999Sgblack@eecs.umich.edu        if (req->isUncacheable())
4994999Sgblack@eecs.umich.edu            recordEvent("Uncached Write");
5002631SN/A
5014999Sgblack@eecs.umich.edu        //If there's a fault or we don't need to access a second cache line,
5024999Sgblack@eecs.umich.edu        //stop now.
5034999Sgblack@eecs.umich.edu        if (fault != NoFault || secondAddr <= addr)
5044999Sgblack@eecs.umich.edu        {
5054999Sgblack@eecs.umich.edu            // If the write needs to have a fault on the access, consider
5064999Sgblack@eecs.umich.edu            // calling changeStatus() and changing it to "bad addr write"
5074999Sgblack@eecs.umich.edu            // or something.
5084999Sgblack@eecs.umich.edu            return fault;
5093170Sstever@eecs.umich.edu        }
5103170Sstever@eecs.umich.edu
5114999Sgblack@eecs.umich.edu        /*
5124999Sgblack@eecs.umich.edu         * Set up for accessing the second cache line.
5134999Sgblack@eecs.umich.edu         */
5144999Sgblack@eecs.umich.edu
5154999Sgblack@eecs.umich.edu        //Move the pointer we're reading into to the correct location.
5164999Sgblack@eecs.umich.edu        dataPtr += dataSize;
5174999Sgblack@eecs.umich.edu        //Adjust the size to get the remaining bytes.
5184999Sgblack@eecs.umich.edu        dataSize = addr + sizeof(T) - secondAddr;
5194999Sgblack@eecs.umich.edu        //And access the right address.
5204999Sgblack@eecs.umich.edu        addr = secondAddr;
5212623SN/A    }
5222623SN/A}
5232623SN/A
5242623SN/A
5252623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS
5264224Sgblack@eecs.umich.edu
5274224Sgblack@eecs.umich.edutemplate
5284224Sgblack@eecs.umich.eduFault
5294224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr,
5304224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
5314224Sgblack@eecs.umich.edu
5324224Sgblack@eecs.umich.edutemplate
5334224Sgblack@eecs.umich.eduFault
5344224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr,
5354224Sgblack@eecs.umich.edu                       unsigned flags, uint64_t *res);
5364224Sgblack@eecs.umich.edu
5372623SN/Atemplate
5382623SN/AFault
5392623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr,
5402623SN/A                       unsigned flags, uint64_t *res);
5412623SN/A
5422623SN/Atemplate
5432623SN/AFault
5442623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr,
5452623SN/A                       unsigned flags, uint64_t *res);
5462623SN/A
5472623SN/Atemplate
5482623SN/AFault
5492623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr,
5502623SN/A                       unsigned flags, uint64_t *res);
5512623SN/A
5522623SN/Atemplate
5532623SN/AFault
5542623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr,
5552623SN/A                       unsigned flags, uint64_t *res);
5562623SN/A
5572623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS
5582623SN/A
5592623SN/Atemplate<>
5602623SN/AFault
5612623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
5622623SN/A{
5632623SN/A    return write(*(uint64_t*)&data, addr, flags, res);
5642623SN/A}
5652623SN/A
5662623SN/Atemplate<>
5672623SN/AFault
5682623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
5692623SN/A{
5702623SN/A    return write(*(uint32_t*)&data, addr, flags, res);
5712623SN/A}
5722623SN/A
5732623SN/A
5742623SN/Atemplate<>
5752623SN/AFault
5762623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
5772623SN/A{
5782623SN/A    return write((uint32_t)data, addr, flags, res);
5792623SN/A}
5802623SN/A
5812623SN/A
5822623SN/Avoid
5832623SN/AAtomicSimpleCPU::tick()
5842623SN/A{
5854940Snate@binkert.org    DPRINTF(SimpleCPU, "Tick\n");
5864940Snate@binkert.org
5875100Ssaidi@eecs.umich.edu    Tick latency = ticks(1); // instruction takes one cycle by default
5882623SN/A
5892623SN/A    for (int i = 0; i < width; ++i) {
5902623SN/A        numCycles++;
5912623SN/A
5923387Sgblack@eecs.umich.edu        if (!curStaticInst || !curStaticInst->isDelayedCommit())
5933387Sgblack@eecs.umich.edu            checkForInterrupts();
5942626SN/A
5954870Sstever@eecs.umich.edu        Fault fault = setupFetchRequest(&ifetch_req);
5962623SN/A
5972623SN/A        if (fault == NoFault) {
5984182Sgblack@eecs.umich.edu            Tick icache_latency = 0;
5994182Sgblack@eecs.umich.edu            bool icache_access = false;
6004182Sgblack@eecs.umich.edu            dcache_access = false; // assume no dcache access
6012662Sstever@eecs.umich.edu
6024182Sgblack@eecs.umich.edu            //Fetch more instruction memory if necessary
6034593Sgblack@eecs.umich.edu            //if(predecoder.needMoreBytes())
6044593Sgblack@eecs.umich.edu            //{
6054182Sgblack@eecs.umich.edu                icache_access = true;
6064870Sstever@eecs.umich.edu                Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
6074870Sstever@eecs.umich.edu                                           Packet::Broadcast);
6084870Sstever@eecs.umich.edu                ifetch_pkt.dataStatic(&inst);
6092623SN/A
6104968Sacolyte@umich.edu                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
6114968Sacolyte@umich.edu                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
6124968Sacolyte@umich.edu                else
6134968Sacolyte@umich.edu                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
6144968Sacolyte@umich.edu
6154986Ssaidi@eecs.umich.edu                assert(!ifetch_pkt.isError());
6164968Sacolyte@umich.edu
6174182Sgblack@eecs.umich.edu                // ifetch_req is initialized to read the instruction directly
6184182Sgblack@eecs.umich.edu                // into the CPU object's inst field.
6194593Sgblack@eecs.umich.edu            //}
6204182Sgblack@eecs.umich.edu
6212623SN/A            preExecute();
6223814Ssaidi@eecs.umich.edu
6235001Sgblack@eecs.umich.edu            if (curStaticInst) {
6244182Sgblack@eecs.umich.edu                fault = curStaticInst->execute(this, traceData);
6254998Sgblack@eecs.umich.edu
6264998Sgblack@eecs.umich.edu                // keep an instruction count
6274998Sgblack@eecs.umich.edu                if (fault == NoFault)
6284998Sgblack@eecs.umich.edu                    countInst();
6295001Sgblack@eecs.umich.edu                else if (traceData) {
6305001Sgblack@eecs.umich.edu                    // If there was a fault, we should trace this instruction.
6315001Sgblack@eecs.umich.edu                    delete traceData;
6325001Sgblack@eecs.umich.edu                    traceData = NULL;
6335001Sgblack@eecs.umich.edu                }
6344998Sgblack@eecs.umich.edu
6354182Sgblack@eecs.umich.edu                postExecute();
6364182Sgblack@eecs.umich.edu            }
6372623SN/A
6383814Ssaidi@eecs.umich.edu            // @todo remove me after debugging with legion done
6394539Sgblack@eecs.umich.edu            if (curStaticInst && (!curStaticInst->isMicroop() ||
6404539Sgblack@eecs.umich.edu                        curStaticInst->isFirstMicroop()))
6413814Ssaidi@eecs.umich.edu                instCnt++;
6423814Ssaidi@eecs.umich.edu
6432623SN/A            if (simulate_stalls) {
6444182Sgblack@eecs.umich.edu                Tick icache_stall =
6455100Ssaidi@eecs.umich.edu                    icache_access ? icache_latency - ticks(1) : 0;
6462623SN/A                Tick dcache_stall =
6475100Ssaidi@eecs.umich.edu                    dcache_access ? dcache_latency - ticks(1) : 0;
6485100Ssaidi@eecs.umich.edu                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
6495100Ssaidi@eecs.umich.edu                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
6505100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles+1);
6512803Ssaidi@eecs.umich.edu                else
6525100Ssaidi@eecs.umich.edu                    latency += ticks(stall_cycles);
6532623SN/A            }
6542623SN/A
6552623SN/A        }
6564377Sgblack@eecs.umich.edu        if(fault != NoFault || !stayAtPC)
6574182Sgblack@eecs.umich.edu            advancePC(fault);
6582623SN/A    }
6592623SN/A
6602626SN/A    if (_status != Idle)
6612626SN/A        tickEvent.schedule(curTick + latency);
6622623SN/A}
6632623SN/A
6642623SN/A
6652623SN/A////////////////////////////////////////////////////////////////////////
6662623SN/A//
6672623SN/A//  AtomicSimpleCPU Simulation Object
6682623SN/A//
6694762Snate@binkert.orgAtomicSimpleCPU *
6704762Snate@binkert.orgAtomicSimpleCPUParams::create()
6712623SN/A{
6722623SN/A    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
6734762Snate@binkert.org    params->name = name;
6742623SN/A    params->numberOfThreads = 1;
6752623SN/A    params->max_insts_any_thread = max_insts_any_thread;
6762623SN/A    params->max_insts_all_threads = max_insts_all_threads;
6772623SN/A    params->max_loads_any_thread = max_loads_any_thread;
6782623SN/A    params->max_loads_all_threads = max_loads_all_threads;
6793119Sktlim@umich.edu    params->progress_interval = progress_interval;
6802623SN/A    params->deferRegistration = defer_registration;
6813661Srdreslin@umich.edu    params->phase = phase;
6822623SN/A    params->clock = clock;
6832623SN/A    params->functionTrace = function_trace;
6842623SN/A    params->functionTraceStart = function_trace_start;
6852623SN/A    params->width = width;
6862623SN/A    params->simulate_stalls = simulate_stalls;
6872901Ssaidi@eecs.umich.edu    params->system = system;
6883170Sstever@eecs.umich.edu    params->cpu_id = cpu_id;
6894776Sgblack@eecs.umich.edu    params->tracer = tracer;
6902623SN/A
6912623SN/A    params->itb = itb;
6922623SN/A    params->dtb = dtb;
6934997Sgblack@eecs.umich.edu#if FULL_SYSTEM
6942623SN/A    params->profile = profile;
6953617Sbinkertn@umich.edu    params->do_quiesce = do_quiesce;
6963617Sbinkertn@umich.edu    params->do_checkpoint_insts = do_checkpoint_insts;
6973617Sbinkertn@umich.edu    params->do_statistics_insts = do_statistics_insts;
6982623SN/A#else
6994762Snate@binkert.org    if (workload.size() != 1)
7004762Snate@binkert.org        panic("only one workload allowed");
7014762Snate@binkert.org    params->process = workload[0];
7022623SN/A#endif
7032623SN/A
7042623SN/A    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
7052623SN/A    return cpu;
7062623SN/A}
707