atomic.cc revision 4998
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/atomic.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 462623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 472623SN/A{ 482623SN/A} 492623SN/A 502623SN/A 512623SN/Avoid 522623SN/AAtomicSimpleCPU::TickEvent::process() 532623SN/A{ 542623SN/A cpu->tick(); 552623SN/A} 562623SN/A 572623SN/Aconst char * 582623SN/AAtomicSimpleCPU::TickEvent::description() 592623SN/A{ 604873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 612623SN/A} 622623SN/A 632856Srdreslin@umich.eduPort * 642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 652856Srdreslin@umich.edu{ 662856Srdreslin@umich.edu if (if_name == "dcache_port") 672856Srdreslin@umich.edu return &dcachePort; 682856Srdreslin@umich.edu else if (if_name == "icache_port") 692856Srdreslin@umich.edu return &icachePort; 704968Sacolyte@umich.edu else if (if_name == "physmem_port") { 714968Sacolyte@umich.edu hasPhysMemPort = true; 724968Sacolyte@umich.edu return &physmemPort; 734968Sacolyte@umich.edu } 742856Srdreslin@umich.edu else 752856Srdreslin@umich.edu panic("No Such Port\n"); 762856Srdreslin@umich.edu} 772623SN/A 782623SN/Avoid 792623SN/AAtomicSimpleCPU::init() 802623SN/A{ 812623SN/A BaseCPU::init(); 822623SN/A#if FULL_SYSTEM 832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 852623SN/A 862623SN/A // initialize CPU, including PC 872680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 882623SN/A } 892623SN/A#endif 904968Sacolyte@umich.edu if (hasPhysMemPort) { 914968Sacolyte@umich.edu bool snoop = false; 924968Sacolyte@umich.edu AddrRangeList pmAddrList; 934968Sacolyte@umich.edu physmemPort.getPeerAddressRanges(pmAddrList, snoop); 944968Sacolyte@umich.edu physMemAddr = *pmAddrList.begin(); 954968Sacolyte@umich.edu } 962623SN/A} 972623SN/A 982623SN/Abool 993349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 1002623SN/A{ 1013184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 1022623SN/A return true; 1032623SN/A} 1042623SN/A 1052623SN/ATick 1063349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 1072623SN/A{ 1083310Srdreslin@umich.edu //Snooping a coherence request, just return 1093649Srdreslin@umich.edu return 0; 1102623SN/A} 1112623SN/A 1122623SN/Avoid 1133349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1142623SN/A{ 1153184Srdreslin@umich.edu //No internal storage to update, just return 1163184Srdreslin@umich.edu return; 1172623SN/A} 1182623SN/A 1192623SN/Avoid 1202623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1212623SN/A{ 1223647Srdreslin@umich.edu if (status == RangeChange) { 1233647Srdreslin@umich.edu if (!snoopRangeSent) { 1243647Srdreslin@umich.edu snoopRangeSent = true; 1253647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1263647Srdreslin@umich.edu } 1272626SN/A return; 1283647Srdreslin@umich.edu } 1292626SN/A 1302623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1312623SN/A} 1322623SN/A 1332657Ssaidi@eecs.umich.eduvoid 1342623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1352623SN/A{ 1362623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1372623SN/A} 1382623SN/A 1394192Sktlim@umich.eduvoid 1404192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port) 1414192Sktlim@umich.edu{ 1424192Sktlim@umich.edu Port::setPeer(port); 1434192Sktlim@umich.edu 1444192Sktlim@umich.edu#if FULL_SYSTEM 1454192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 1464192Sktlim@umich.edu // Ports) 1474192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 1484192Sktlim@umich.edu#endif 1494192Sktlim@umich.edu} 1502623SN/A 1512623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1522623SN/A : BaseSimpleCPU(p), tickEvent(this), 1532623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1544968Sacolyte@umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1554968Sacolyte@umich.edu physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1562623SN/A{ 1572623SN/A _status = Idle; 1582623SN/A 1593647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1603647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1613647Srdreslin@umich.edu 1624870Sstever@eecs.umich.edu ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 1634870Sstever@eecs.umich.edu data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too 1644870Sstever@eecs.umich.edu data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too 1652623SN/A} 1662623SN/A 1672623SN/A 1682623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1692623SN/A{ 1702623SN/A} 1712623SN/A 1722623SN/Avoid 1732623SN/AAtomicSimpleCPU::serialize(ostream &os) 1742623SN/A{ 1752915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1762915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1773177Shsul@eecs.umich.edu Status _status = status(); 1783177Shsul@eecs.umich.edu SERIALIZE_ENUM(_status); 1793145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1802623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1812623SN/A tickEvent.serialize(os); 1822623SN/A} 1832623SN/A 1842623SN/Avoid 1852623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1862623SN/A{ 1872915Sktlim@umich.edu SimObject::State so_state; 1882915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1893177Shsul@eecs.umich.edu UNSERIALIZE_ENUM(_status); 1903145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1912915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1922915Sktlim@umich.edu} 1932915Sktlim@umich.edu 1942915Sktlim@umich.eduvoid 1952915Sktlim@umich.eduAtomicSimpleCPU::resume() 1962915Sktlim@umich.edu{ 1974940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1983324Shsul@eecs.umich.edu if (_status != SwitchedOut && _status != Idle) { 1994762Snate@binkert.org assert(system->getMemoryMode() == Enums::atomic); 2003324Shsul@eecs.umich.edu 2013324Shsul@eecs.umich.edu changeState(SimObject::Running); 2023324Shsul@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 2033431Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 2043495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 2053431Sgblack@eecs.umich.edu } 2063324Shsul@eecs.umich.edu } 2072915Sktlim@umich.edu } 2082623SN/A} 2092623SN/A 2102623SN/Avoid 2112798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2122623SN/A{ 2132798Sktlim@umich.edu assert(status() == Running || status() == Idle); 2142798Sktlim@umich.edu _status = SwitchedOut; 2152623SN/A 2162798Sktlim@umich.edu tickEvent.squash(); 2172623SN/A} 2182623SN/A 2192623SN/A 2202623SN/Avoid 2212623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2222623SN/A{ 2234192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2242623SN/A 2252623SN/A assert(!tickEvent.scheduled()); 2262623SN/A 2272680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2282623SN/A // running and schedule its tick event. 2292680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2302680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2312680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2322623SN/A _status = Running; 2333495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 2342623SN/A break; 2352623SN/A } 2362623SN/A } 2373512Sktlim@umich.edu if (_status != Running) { 2383512Sktlim@umich.edu _status = Idle; 2393512Sktlim@umich.edu } 2402623SN/A} 2412623SN/A 2422623SN/A 2432623SN/Avoid 2442623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2452623SN/A{ 2464940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2474940Snate@binkert.org 2482623SN/A assert(thread_num == 0); 2492683Sktlim@umich.edu assert(thread); 2502623SN/A 2512623SN/A assert(_status == Idle); 2522623SN/A assert(!tickEvent.scheduled()); 2532623SN/A 2542623SN/A notIdleFraction++; 2553686Sktlim@umich.edu 2563430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2573495Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 2582623SN/A _status = Running; 2592623SN/A} 2602623SN/A 2612623SN/A 2622623SN/Avoid 2632623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2642623SN/A{ 2654940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2664940Snate@binkert.org 2672623SN/A assert(thread_num == 0); 2682683Sktlim@umich.edu assert(thread); 2692623SN/A 2702623SN/A assert(_status == Running); 2712626SN/A 2722626SN/A // tick event may not be scheduled if this gets called from inside 2732626SN/A // an instruction's execution, e.g. "quiesce" 2742626SN/A if (tickEvent.scheduled()) 2752626SN/A tickEvent.deschedule(); 2762623SN/A 2772623SN/A notIdleFraction--; 2782623SN/A _status = Idle; 2792623SN/A} 2802623SN/A 2812623SN/A 2822623SN/Atemplate <class T> 2832623SN/AFault 2842623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2852623SN/A{ 2863169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2874870Sstever@eecs.umich.edu Request *req = &data_read_req; 2883169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2892623SN/A 2902623SN/A if (traceData) { 2912623SN/A traceData->setAddr(addr); 2922623SN/A } 2932623SN/A 2942623SN/A // translate to physical address 2953169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2962623SN/A 2972623SN/A // Now do the access. 2982623SN/A if (fault == NoFault) { 2994878Sstever@eecs.umich.edu Packet pkt = 3004878Sstever@eecs.umich.edu Packet(req, 3014878Sstever@eecs.umich.edu req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 3024878Sstever@eecs.umich.edu Packet::Broadcast); 3034870Sstever@eecs.umich.edu pkt.dataStatic(&data); 3042623SN/A 3053806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) 3064870Sstever@eecs.umich.edu dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt); 3074968Sacolyte@umich.edu else { 3084968Sacolyte@umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 3094968Sacolyte@umich.edu dcache_latency = physmemPort.sendAtomic(&pkt); 3104968Sacolyte@umich.edu else 3114968Sacolyte@umich.edu dcache_latency = dcachePort.sendAtomic(&pkt); 3124968Sacolyte@umich.edu } 3132623SN/A dcache_access = true; 3144870Sstever@eecs.umich.edu assert(!pkt.isError()); 3154762Snate@binkert.org 3164925Sstever@eecs.umich.edu data = gtoh(data); 3173170Sstever@eecs.umich.edu 3183170Sstever@eecs.umich.edu if (req->isLocked()) { 3193170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3203170Sstever@eecs.umich.edu } 3212623SN/A } 3222623SN/A 3232623SN/A // This will need a new way to tell if it has a dcache attached. 3243172Sstever@eecs.umich.edu if (req->isUncacheable()) 3252623SN/A recordEvent("Uncached Read"); 3262623SN/A 3272623SN/A return fault; 3282623SN/A} 3292623SN/A 3302623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3312623SN/A 3322623SN/Atemplate 3332623SN/AFault 3344115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3354115Ssaidi@eecs.umich.edu 3364115Ssaidi@eecs.umich.edutemplate 3374115Ssaidi@eecs.umich.eduFault 3384040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3394040Ssaidi@eecs.umich.edu 3404040Ssaidi@eecs.umich.edutemplate 3414040Ssaidi@eecs.umich.eduFault 3422623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3432623SN/A 3442623SN/Atemplate 3452623SN/AFault 3462623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3472623SN/A 3482623SN/Atemplate 3492623SN/AFault 3502623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3512623SN/A 3522623SN/Atemplate 3532623SN/AFault 3542623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3552623SN/A 3562623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3572623SN/A 3582623SN/Atemplate<> 3592623SN/AFault 3602623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3612623SN/A{ 3622623SN/A return read(addr, *(uint64_t*)&data, flags); 3632623SN/A} 3642623SN/A 3652623SN/Atemplate<> 3662623SN/AFault 3672623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3682623SN/A{ 3692623SN/A return read(addr, *(uint32_t*)&data, flags); 3702623SN/A} 3712623SN/A 3722623SN/A 3732623SN/Atemplate<> 3742623SN/AFault 3752623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3762623SN/A{ 3772623SN/A return read(addr, (uint32_t&)data, flags); 3782623SN/A} 3792623SN/A 3802623SN/A 3812623SN/Atemplate <class T> 3822623SN/AFault 3832623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3842623SN/A{ 3853169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3864870Sstever@eecs.umich.edu Request *req = &data_write_req; 3873169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3882623SN/A 3892623SN/A if (traceData) { 3902623SN/A traceData->setAddr(addr); 3912623SN/A } 3922623SN/A 3932623SN/A // translate to physical address 3943169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3952623SN/A 3962623SN/A // Now do the access. 3972623SN/A if (fault == NoFault) { 3984878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3993170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4002623SN/A 4013170Sstever@eecs.umich.edu if (req->isLocked()) { 4024878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 4033170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 4044878Sstever@eecs.umich.edu } else if (req->isSwap()) { 4054878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 4064878Sstever@eecs.umich.edu if (req->isCondSwap()) { 4074878Sstever@eecs.umich.edu assert(res); 4084878Sstever@eecs.umich.edu req->setExtraData(*res); 4094878Sstever@eecs.umich.edu } 4104040Ssaidi@eecs.umich.edu } 4114040Ssaidi@eecs.umich.edu 4123170Sstever@eecs.umich.edu if (do_access) { 4134878Sstever@eecs.umich.edu Packet pkt = Packet(req, cmd, Packet::Broadcast); 4144878Sstever@eecs.umich.edu pkt.dataStatic(&data); 4152631SN/A 4163806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4174870Sstever@eecs.umich.edu dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt); 4183806Ssaidi@eecs.umich.edu } else { 4193806Ssaidi@eecs.umich.edu data = htog(data); 4204968Sacolyte@umich.edu if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 4214968Sacolyte@umich.edu dcache_latency = physmemPort.sendAtomic(&pkt); 4224968Sacolyte@umich.edu else 4234968Sacolyte@umich.edu dcache_latency = dcachePort.sendAtomic(&pkt); 4243806Ssaidi@eecs.umich.edu } 4253170Sstever@eecs.umich.edu dcache_access = true; 4264870Sstever@eecs.umich.edu assert(!pkt.isError()); 4273170Sstever@eecs.umich.edu 4284878Sstever@eecs.umich.edu if (req->isSwap()) { 4294878Sstever@eecs.umich.edu assert(res); 4304878Sstever@eecs.umich.edu *res = pkt.get<T>(); 4314878Sstever@eecs.umich.edu } 4323170Sstever@eecs.umich.edu } 4333170Sstever@eecs.umich.edu 4344878Sstever@eecs.umich.edu if (res && !req->isSwap()) { 4354052Ssaidi@eecs.umich.edu *res = req->getExtraData(); 4362631SN/A } 4372623SN/A } 4382623SN/A 4392623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 4403172Sstever@eecs.umich.edu if (req->isUncacheable()) 4412623SN/A recordEvent("Uncached Write"); 4422623SN/A 4432623SN/A // If the write needs to have a fault on the access, consider calling 4442623SN/A // changeStatus() and changing it to "bad addr write" or something. 4452623SN/A return fault; 4462623SN/A} 4472623SN/A 4482623SN/A 4492623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4504224Sgblack@eecs.umich.edu 4514224Sgblack@eecs.umich.edutemplate 4524224Sgblack@eecs.umich.eduFault 4534224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr, 4544224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4554224Sgblack@eecs.umich.edu 4564224Sgblack@eecs.umich.edutemplate 4574224Sgblack@eecs.umich.eduFault 4584224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr, 4594224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4604224Sgblack@eecs.umich.edu 4612623SN/Atemplate 4622623SN/AFault 4632623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 4642623SN/A unsigned flags, uint64_t *res); 4652623SN/A 4662623SN/Atemplate 4672623SN/AFault 4682623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 4692623SN/A unsigned flags, uint64_t *res); 4702623SN/A 4712623SN/Atemplate 4722623SN/AFault 4732623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 4742623SN/A unsigned flags, uint64_t *res); 4752623SN/A 4762623SN/Atemplate 4772623SN/AFault 4782623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 4792623SN/A unsigned flags, uint64_t *res); 4802623SN/A 4812623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4822623SN/A 4832623SN/Atemplate<> 4842623SN/AFault 4852623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4862623SN/A{ 4872623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4882623SN/A} 4892623SN/A 4902623SN/Atemplate<> 4912623SN/AFault 4922623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4932623SN/A{ 4942623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4952623SN/A} 4962623SN/A 4972623SN/A 4982623SN/Atemplate<> 4992623SN/AFault 5002623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5012623SN/A{ 5022623SN/A return write((uint32_t)data, addr, flags, res); 5032623SN/A} 5042623SN/A 5052623SN/A 5062623SN/Avoid 5072623SN/AAtomicSimpleCPU::tick() 5082623SN/A{ 5094940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5104940Snate@binkert.org 5112623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 5122623SN/A 5132623SN/A for (int i = 0; i < width; ++i) { 5142623SN/A numCycles++; 5152623SN/A 5163387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5173387Sgblack@eecs.umich.edu checkForInterrupts(); 5182626SN/A 5194870Sstever@eecs.umich.edu Fault fault = setupFetchRequest(&ifetch_req); 5202623SN/A 5212623SN/A if (fault == NoFault) { 5224182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5234182Sgblack@eecs.umich.edu bool icache_access = false; 5244182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5252662Sstever@eecs.umich.edu 5264182Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5274593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 5284593Sgblack@eecs.umich.edu //{ 5294182Sgblack@eecs.umich.edu icache_access = true; 5304870Sstever@eecs.umich.edu Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 5314870Sstever@eecs.umich.edu Packet::Broadcast); 5324870Sstever@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5332623SN/A 5344968Sacolyte@umich.edu if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 5354968Sacolyte@umich.edu icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 5364968Sacolyte@umich.edu else 5374968Sacolyte@umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5384968Sacolyte@umich.edu 5394968Sacolyte@umich.edu 5404182Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5414182Sgblack@eecs.umich.edu // into the CPU object's inst field. 5424593Sgblack@eecs.umich.edu //} 5434182Sgblack@eecs.umich.edu 5442623SN/A preExecute(); 5453814Ssaidi@eecs.umich.edu 5464182Sgblack@eecs.umich.edu if(curStaticInst) 5474182Sgblack@eecs.umich.edu { 5484182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5494998Sgblack@eecs.umich.edu 5504998Sgblack@eecs.umich.edu // keep an instruction count 5514998Sgblack@eecs.umich.edu if (fault == NoFault) 5524998Sgblack@eecs.umich.edu countInst(); 5534998Sgblack@eecs.umich.edu 5544182Sgblack@eecs.umich.edu postExecute(); 5554182Sgblack@eecs.umich.edu } 5562623SN/A 5573814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5584539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5594539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5603814Ssaidi@eecs.umich.edu instCnt++; 5613814Ssaidi@eecs.umich.edu 5622623SN/A if (simulate_stalls) { 5634182Sgblack@eecs.umich.edu Tick icache_stall = 5644182Sgblack@eecs.umich.edu icache_access ? icache_latency - cycles(1) : 0; 5652623SN/A Tick dcache_stall = 5662662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 5672803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 5682803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 5692803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 5702803Ssaidi@eecs.umich.edu else 5712803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 5722623SN/A } 5732623SN/A 5742623SN/A } 5754377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5764182Sgblack@eecs.umich.edu advancePC(fault); 5772623SN/A } 5782623SN/A 5792626SN/A if (_status != Idle) 5802626SN/A tickEvent.schedule(curTick + latency); 5812623SN/A} 5822623SN/A 5832623SN/A 5842623SN/A//////////////////////////////////////////////////////////////////////// 5852623SN/A// 5862623SN/A// AtomicSimpleCPU Simulation Object 5872623SN/A// 5884762Snate@binkert.orgAtomicSimpleCPU * 5894762Snate@binkert.orgAtomicSimpleCPUParams::create() 5902623SN/A{ 5912623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5924762Snate@binkert.org params->name = name; 5932623SN/A params->numberOfThreads = 1; 5942623SN/A params->max_insts_any_thread = max_insts_any_thread; 5952623SN/A params->max_insts_all_threads = max_insts_all_threads; 5962623SN/A params->max_loads_any_thread = max_loads_any_thread; 5972623SN/A params->max_loads_all_threads = max_loads_all_threads; 5983119Sktlim@umich.edu params->progress_interval = progress_interval; 5992623SN/A params->deferRegistration = defer_registration; 6003661Srdreslin@umich.edu params->phase = phase; 6012623SN/A params->clock = clock; 6022623SN/A params->functionTrace = function_trace; 6032623SN/A params->functionTraceStart = function_trace_start; 6042623SN/A params->width = width; 6052623SN/A params->simulate_stalls = simulate_stalls; 6062901Ssaidi@eecs.umich.edu params->system = system; 6073170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 6084776Sgblack@eecs.umich.edu params->tracer = tracer; 6092623SN/A 6102623SN/A params->itb = itb; 6112623SN/A params->dtb = dtb; 6124997Sgblack@eecs.umich.edu#if FULL_SYSTEM 6132623SN/A params->profile = profile; 6143617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 6153617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 6163617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 6172623SN/A#else 6184762Snate@binkert.org if (workload.size() != 1) 6194762Snate@binkert.org panic("only one workload allowed"); 6204762Snate@binkert.org params->process = workload[0]; 6212623SN/A#endif 6222623SN/A 6232623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 6242623SN/A return cpu; 6252623SN/A} 626