atomic.cc revision 4940
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 323806Ssaidi@eecs.umich.edu#include "arch/mmaped_ipr.hh" 332623SN/A#include "arch/utility.hh" 344040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 352623SN/A#include "cpu/exetrace.hh" 362623SN/A#include "cpu/simple/atomic.hh" 373348Sbinkertn@umich.edu#include "mem/packet.hh" 383348Sbinkertn@umich.edu#include "mem/packet_access.hh" 394762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace std; 432623SN/Ausing namespace TheISA; 442623SN/A 452623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 462623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 472623SN/A{ 482623SN/A} 492623SN/A 502623SN/A 512623SN/Avoid 522623SN/AAtomicSimpleCPU::TickEvent::process() 532623SN/A{ 542623SN/A cpu->tick(); 552623SN/A} 562623SN/A 572623SN/Aconst char * 582623SN/AAtomicSimpleCPU::TickEvent::description() 592623SN/A{ 604873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 612623SN/A} 622623SN/A 632856Srdreslin@umich.eduPort * 642856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 652856Srdreslin@umich.edu{ 662856Srdreslin@umich.edu if (if_name == "dcache_port") 672856Srdreslin@umich.edu return &dcachePort; 682856Srdreslin@umich.edu else if (if_name == "icache_port") 692856Srdreslin@umich.edu return &icachePort; 702856Srdreslin@umich.edu else 712856Srdreslin@umich.edu panic("No Such Port\n"); 722856Srdreslin@umich.edu} 732623SN/A 742623SN/Avoid 752623SN/AAtomicSimpleCPU::init() 762623SN/A{ 772623SN/A BaseCPU::init(); 782623SN/A#if FULL_SYSTEM 792680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 802680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 812623SN/A 822623SN/A // initialize CPU, including PC 832680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 842623SN/A } 852623SN/A#endif 862623SN/A} 872623SN/A 882623SN/Abool 893349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 902623SN/A{ 913184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 922623SN/A return true; 932623SN/A} 942623SN/A 952623SN/ATick 963349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 972623SN/A{ 983310Srdreslin@umich.edu //Snooping a coherence request, just return 993649Srdreslin@umich.edu return 0; 1002623SN/A} 1012623SN/A 1022623SN/Avoid 1033349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1042623SN/A{ 1053184Srdreslin@umich.edu //No internal storage to update, just return 1063184Srdreslin@umich.edu return; 1072623SN/A} 1082623SN/A 1092623SN/Avoid 1102623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1112623SN/A{ 1123647Srdreslin@umich.edu if (status == RangeChange) { 1133647Srdreslin@umich.edu if (!snoopRangeSent) { 1143647Srdreslin@umich.edu snoopRangeSent = true; 1153647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1163647Srdreslin@umich.edu } 1172626SN/A return; 1183647Srdreslin@umich.edu } 1192626SN/A 1202623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1212623SN/A} 1222623SN/A 1232657Ssaidi@eecs.umich.eduvoid 1242623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1252623SN/A{ 1262623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1272623SN/A} 1282623SN/A 1294192Sktlim@umich.eduvoid 1304192Sktlim@umich.eduAtomicSimpleCPU::DcachePort::setPeer(Port *port) 1314192Sktlim@umich.edu{ 1324192Sktlim@umich.edu Port::setPeer(port); 1334192Sktlim@umich.edu 1344192Sktlim@umich.edu#if FULL_SYSTEM 1354192Sktlim@umich.edu // Update the ThreadContext's memory ports (Functional/Virtual 1364192Sktlim@umich.edu // Ports) 1374192Sktlim@umich.edu cpu->tcBase()->connectMemPorts(); 1384192Sktlim@umich.edu#endif 1394192Sktlim@umich.edu} 1402623SN/A 1412623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1422623SN/A : BaseSimpleCPU(p), tickEvent(this), 1432623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1442640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1452623SN/A{ 1462623SN/A _status = Idle; 1472623SN/A 1483647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1493647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1503647Srdreslin@umich.edu 1514870Sstever@eecs.umich.edu ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 1524870Sstever@eecs.umich.edu data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too 1534870Sstever@eecs.umich.edu data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too 1542623SN/A} 1552623SN/A 1562623SN/A 1572623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1582623SN/A{ 1592623SN/A} 1602623SN/A 1612623SN/Avoid 1622623SN/AAtomicSimpleCPU::serialize(ostream &os) 1632623SN/A{ 1642915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1652915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1663177Shsul@eecs.umich.edu Status _status = status(); 1673177Shsul@eecs.umich.edu SERIALIZE_ENUM(_status); 1683145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1692623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1702623SN/A tickEvent.serialize(os); 1712623SN/A} 1722623SN/A 1732623SN/Avoid 1742623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1752623SN/A{ 1762915Sktlim@umich.edu SimObject::State so_state; 1772915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1783177Shsul@eecs.umich.edu UNSERIALIZE_ENUM(_status); 1793145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1802915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1812915Sktlim@umich.edu} 1822915Sktlim@umich.edu 1832915Sktlim@umich.eduvoid 1842915Sktlim@umich.eduAtomicSimpleCPU::resume() 1852915Sktlim@umich.edu{ 1864940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1873324Shsul@eecs.umich.edu if (_status != SwitchedOut && _status != Idle) { 1884762Snate@binkert.org assert(system->getMemoryMode() == Enums::atomic); 1893324Shsul@eecs.umich.edu 1903324Shsul@eecs.umich.edu changeState(SimObject::Running); 1913324Shsul@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1923431Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 1933495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 1943431Sgblack@eecs.umich.edu } 1953324Shsul@eecs.umich.edu } 1962915Sktlim@umich.edu } 1972623SN/A} 1982623SN/A 1992623SN/Avoid 2002798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 2012623SN/A{ 2022798Sktlim@umich.edu assert(status() == Running || status() == Idle); 2032798Sktlim@umich.edu _status = SwitchedOut; 2042623SN/A 2052798Sktlim@umich.edu tickEvent.squash(); 2062623SN/A} 2072623SN/A 2082623SN/A 2092623SN/Avoid 2102623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2112623SN/A{ 2124192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2132623SN/A 2142623SN/A assert(!tickEvent.scheduled()); 2152623SN/A 2162680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2172623SN/A // running and schedule its tick event. 2182680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2192680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2202680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2212623SN/A _status = Running; 2223495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 2232623SN/A break; 2242623SN/A } 2252623SN/A } 2263512Sktlim@umich.edu if (_status != Running) { 2273512Sktlim@umich.edu _status = Idle; 2283512Sktlim@umich.edu } 2292623SN/A} 2302623SN/A 2312623SN/A 2322623SN/Avoid 2332623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2342623SN/A{ 2354940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2364940Snate@binkert.org 2372623SN/A assert(thread_num == 0); 2382683Sktlim@umich.edu assert(thread); 2392623SN/A 2402623SN/A assert(_status == Idle); 2412623SN/A assert(!tickEvent.scheduled()); 2422623SN/A 2432623SN/A notIdleFraction++; 2443686Sktlim@umich.edu 2453430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2463495Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 2472623SN/A _status = Running; 2482623SN/A} 2492623SN/A 2502623SN/A 2512623SN/Avoid 2522623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2532623SN/A{ 2544940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2554940Snate@binkert.org 2562623SN/A assert(thread_num == 0); 2572683Sktlim@umich.edu assert(thread); 2582623SN/A 2592623SN/A assert(_status == Running); 2602626SN/A 2612626SN/A // tick event may not be scheduled if this gets called from inside 2622626SN/A // an instruction's execution, e.g. "quiesce" 2632626SN/A if (tickEvent.scheduled()) 2642626SN/A tickEvent.deschedule(); 2652623SN/A 2662623SN/A notIdleFraction--; 2672623SN/A _status = Idle; 2682623SN/A} 2692623SN/A 2702623SN/A 2712623SN/Atemplate <class T> 2722623SN/AFault 2732623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2742623SN/A{ 2753169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2764870Sstever@eecs.umich.edu Request *req = &data_read_req; 2773169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2782623SN/A 2792623SN/A if (traceData) { 2802623SN/A traceData->setAddr(addr); 2812623SN/A } 2822623SN/A 2832623SN/A // translate to physical address 2843169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2852623SN/A 2862623SN/A // Now do the access. 2872623SN/A if (fault == NoFault) { 2884878Sstever@eecs.umich.edu Packet pkt = 2894878Sstever@eecs.umich.edu Packet(req, 2904878Sstever@eecs.umich.edu req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 2914878Sstever@eecs.umich.edu Packet::Broadcast); 2924870Sstever@eecs.umich.edu pkt.dataStatic(&data); 2932623SN/A 2943806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) 2954870Sstever@eecs.umich.edu dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt); 2963806Ssaidi@eecs.umich.edu else 2974870Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(&pkt); 2982623SN/A dcache_access = true; 2994870Sstever@eecs.umich.edu assert(!pkt.isError()); 3004762Snate@binkert.org 3014925Sstever@eecs.umich.edu data = gtoh(data); 3023170Sstever@eecs.umich.edu 3033170Sstever@eecs.umich.edu if (req->isLocked()) { 3043170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3053170Sstever@eecs.umich.edu } 3062623SN/A } 3072623SN/A 3082623SN/A // This will need a new way to tell if it has a dcache attached. 3093172Sstever@eecs.umich.edu if (req->isUncacheable()) 3102623SN/A recordEvent("Uncached Read"); 3112623SN/A 3122623SN/A return fault; 3132623SN/A} 3142623SN/A 3152623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3162623SN/A 3172623SN/Atemplate 3182623SN/AFault 3194115Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 3204115Ssaidi@eecs.umich.edu 3214115Ssaidi@eecs.umich.edutemplate 3224115Ssaidi@eecs.umich.eduFault 3234040Ssaidi@eecs.umich.eduAtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 3244040Ssaidi@eecs.umich.edu 3254040Ssaidi@eecs.umich.edutemplate 3264040Ssaidi@eecs.umich.eduFault 3272623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3282623SN/A 3292623SN/Atemplate 3302623SN/AFault 3312623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3322623SN/A 3332623SN/Atemplate 3342623SN/AFault 3352623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3362623SN/A 3372623SN/Atemplate 3382623SN/AFault 3392623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3402623SN/A 3412623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3422623SN/A 3432623SN/Atemplate<> 3442623SN/AFault 3452623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3462623SN/A{ 3472623SN/A return read(addr, *(uint64_t*)&data, flags); 3482623SN/A} 3492623SN/A 3502623SN/Atemplate<> 3512623SN/AFault 3522623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3532623SN/A{ 3542623SN/A return read(addr, *(uint32_t*)&data, flags); 3552623SN/A} 3562623SN/A 3572623SN/A 3582623SN/Atemplate<> 3592623SN/AFault 3602623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3612623SN/A{ 3622623SN/A return read(addr, (uint32_t&)data, flags); 3632623SN/A} 3642623SN/A 3652623SN/A 3662623SN/Atemplate <class T> 3672623SN/AFault 3682623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3692623SN/A{ 3703169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3714870Sstever@eecs.umich.edu Request *req = &data_write_req; 3723169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3732623SN/A 3742623SN/A if (traceData) { 3752623SN/A traceData->setAddr(addr); 3762623SN/A } 3772623SN/A 3782623SN/A // translate to physical address 3793169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3802623SN/A 3812623SN/A // Now do the access. 3822623SN/A if (fault == NoFault) { 3834878Sstever@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 3843170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3852623SN/A 3863170Sstever@eecs.umich.edu if (req->isLocked()) { 3874878Sstever@eecs.umich.edu cmd = MemCmd::StoreCondReq; 3883170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3894878Sstever@eecs.umich.edu } else if (req->isSwap()) { 3904878Sstever@eecs.umich.edu cmd = MemCmd::SwapReq; 3914878Sstever@eecs.umich.edu if (req->isCondSwap()) { 3924878Sstever@eecs.umich.edu assert(res); 3934878Sstever@eecs.umich.edu req->setExtraData(*res); 3944878Sstever@eecs.umich.edu } 3954040Ssaidi@eecs.umich.edu } 3964040Ssaidi@eecs.umich.edu 3973170Sstever@eecs.umich.edu if (do_access) { 3984878Sstever@eecs.umich.edu Packet pkt = Packet(req, cmd, Packet::Broadcast); 3994878Sstever@eecs.umich.edu pkt.dataStatic(&data); 4002631SN/A 4013806Ssaidi@eecs.umich.edu if (req->isMmapedIpr()) { 4024870Sstever@eecs.umich.edu dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt); 4033806Ssaidi@eecs.umich.edu } else { 4043806Ssaidi@eecs.umich.edu data = htog(data); 4054870Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(&pkt); 4063806Ssaidi@eecs.umich.edu } 4073170Sstever@eecs.umich.edu dcache_access = true; 4084870Sstever@eecs.umich.edu assert(!pkt.isError()); 4093170Sstever@eecs.umich.edu 4104878Sstever@eecs.umich.edu if (req->isSwap()) { 4114878Sstever@eecs.umich.edu assert(res); 4124878Sstever@eecs.umich.edu *res = pkt.get<T>(); 4134878Sstever@eecs.umich.edu } 4143170Sstever@eecs.umich.edu } 4153170Sstever@eecs.umich.edu 4164878Sstever@eecs.umich.edu if (res && !req->isSwap()) { 4174052Ssaidi@eecs.umich.edu *res = req->getExtraData(); 4182631SN/A } 4192623SN/A } 4202623SN/A 4212623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 4223172Sstever@eecs.umich.edu if (req->isUncacheable()) 4232623SN/A recordEvent("Uncached Write"); 4242623SN/A 4252623SN/A // If the write needs to have a fault on the access, consider calling 4262623SN/A // changeStatus() and changing it to "bad addr write" or something. 4272623SN/A return fault; 4282623SN/A} 4292623SN/A 4302623SN/A 4312623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4324224Sgblack@eecs.umich.edu 4334224Sgblack@eecs.umich.edutemplate 4344224Sgblack@eecs.umich.eduFault 4354224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin32_t data, Addr addr, 4364224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4374224Sgblack@eecs.umich.edu 4384224Sgblack@eecs.umich.edutemplate 4394224Sgblack@eecs.umich.eduFault 4404224Sgblack@eecs.umich.eduAtomicSimpleCPU::write(Twin64_t data, Addr addr, 4414224Sgblack@eecs.umich.edu unsigned flags, uint64_t *res); 4424224Sgblack@eecs.umich.edu 4432623SN/Atemplate 4442623SN/AFault 4452623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 4462623SN/A unsigned flags, uint64_t *res); 4472623SN/A 4482623SN/Atemplate 4492623SN/AFault 4502623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 4512623SN/A unsigned flags, uint64_t *res); 4522623SN/A 4532623SN/Atemplate 4542623SN/AFault 4552623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 4562623SN/A unsigned flags, uint64_t *res); 4572623SN/A 4582623SN/Atemplate 4592623SN/AFault 4602623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 4612623SN/A unsigned flags, uint64_t *res); 4622623SN/A 4632623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4642623SN/A 4652623SN/Atemplate<> 4662623SN/AFault 4672623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4682623SN/A{ 4692623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4702623SN/A} 4712623SN/A 4722623SN/Atemplate<> 4732623SN/AFault 4742623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4752623SN/A{ 4762623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4772623SN/A} 4782623SN/A 4792623SN/A 4802623SN/Atemplate<> 4812623SN/AFault 4822623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4832623SN/A{ 4842623SN/A return write((uint32_t)data, addr, flags, res); 4852623SN/A} 4862623SN/A 4872623SN/A 4882623SN/Avoid 4892623SN/AAtomicSimpleCPU::tick() 4902623SN/A{ 4914940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4924940Snate@binkert.org 4932623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4942623SN/A 4952623SN/A for (int i = 0; i < width; ++i) { 4962623SN/A numCycles++; 4972623SN/A 4983387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4993387Sgblack@eecs.umich.edu checkForInterrupts(); 5002626SN/A 5014870Sstever@eecs.umich.edu Fault fault = setupFetchRequest(&ifetch_req); 5022623SN/A 5032623SN/A if (fault == NoFault) { 5044182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5054182Sgblack@eecs.umich.edu bool icache_access = false; 5064182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5072662Sstever@eecs.umich.edu 5084182Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5094593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 5104593Sgblack@eecs.umich.edu //{ 5114182Sgblack@eecs.umich.edu icache_access = true; 5124870Sstever@eecs.umich.edu Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 5134870Sstever@eecs.umich.edu Packet::Broadcast); 5144870Sstever@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5152623SN/A 5164870Sstever@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5174182Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5184182Sgblack@eecs.umich.edu // into the CPU object's inst field. 5194593Sgblack@eecs.umich.edu //} 5204182Sgblack@eecs.umich.edu 5212623SN/A preExecute(); 5223814Ssaidi@eecs.umich.edu 5234182Sgblack@eecs.umich.edu if(curStaticInst) 5244182Sgblack@eecs.umich.edu { 5254182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5264182Sgblack@eecs.umich.edu postExecute(); 5274182Sgblack@eecs.umich.edu } 5282623SN/A 5293814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5304539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5314539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5323814Ssaidi@eecs.umich.edu instCnt++; 5333814Ssaidi@eecs.umich.edu 5342623SN/A if (simulate_stalls) { 5354182Sgblack@eecs.umich.edu Tick icache_stall = 5364182Sgblack@eecs.umich.edu icache_access ? icache_latency - cycles(1) : 0; 5372623SN/A Tick dcache_stall = 5382662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 5392803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 5402803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 5412803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 5422803Ssaidi@eecs.umich.edu else 5432803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 5442623SN/A } 5452623SN/A 5462623SN/A } 5474377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 5484182Sgblack@eecs.umich.edu advancePC(fault); 5492623SN/A } 5502623SN/A 5512626SN/A if (_status != Idle) 5522626SN/A tickEvent.schedule(curTick + latency); 5532623SN/A} 5542623SN/A 5552623SN/A 5562623SN/A//////////////////////////////////////////////////////////////////////// 5572623SN/A// 5582623SN/A// AtomicSimpleCPU Simulation Object 5592623SN/A// 5604762Snate@binkert.orgAtomicSimpleCPU * 5614762Snate@binkert.orgAtomicSimpleCPUParams::create() 5622623SN/A{ 5632623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5644762Snate@binkert.org params->name = name; 5652623SN/A params->numberOfThreads = 1; 5662623SN/A params->max_insts_any_thread = max_insts_any_thread; 5672623SN/A params->max_insts_all_threads = max_insts_all_threads; 5682623SN/A params->max_loads_any_thread = max_loads_any_thread; 5692623SN/A params->max_loads_all_threads = max_loads_all_threads; 5703119Sktlim@umich.edu params->progress_interval = progress_interval; 5712623SN/A params->deferRegistration = defer_registration; 5723661Srdreslin@umich.edu params->phase = phase; 5732623SN/A params->clock = clock; 5742623SN/A params->functionTrace = function_trace; 5752623SN/A params->functionTraceStart = function_trace_start; 5762623SN/A params->width = width; 5772623SN/A params->simulate_stalls = simulate_stalls; 5782901Ssaidi@eecs.umich.edu params->system = system; 5793170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 5804776Sgblack@eecs.umich.edu params->tracer = tracer; 5812623SN/A 5822623SN/A#if FULL_SYSTEM 5832623SN/A params->itb = itb; 5842623SN/A params->dtb = dtb; 5852623SN/A params->profile = profile; 5863617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 5873617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 5883617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 5892623SN/A#else 5904762Snate@binkert.org if (workload.size() != 1) 5914762Snate@binkert.org panic("only one workload allowed"); 5924762Snate@binkert.org params->process = workload[0]; 5932623SN/A#endif 5942623SN/A 5952623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 5962623SN/A return cpu; 5972623SN/A} 598