atomic.cc revision 3661
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/atomic.hh" 353348Sbinkertn@umich.edu#include "mem/packet.hh" 363348Sbinkertn@umich.edu#include "mem/packet_access.hh" 372623SN/A#include "sim/builder.hh" 382901Ssaidi@eecs.umich.edu#include "sim/system.hh" 392623SN/A 402623SN/Ausing namespace std; 412623SN/Ausing namespace TheISA; 422623SN/A 432623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 442623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 452623SN/A{ 462623SN/A} 472623SN/A 482623SN/A 492623SN/Avoid 502623SN/AAtomicSimpleCPU::TickEvent::process() 512623SN/A{ 522623SN/A cpu->tick(); 532623SN/A} 542623SN/A 552623SN/Aconst char * 562623SN/AAtomicSimpleCPU::TickEvent::description() 572623SN/A{ 582623SN/A return "AtomicSimpleCPU tick event"; 592623SN/A} 602623SN/A 612856Srdreslin@umich.eduPort * 622856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 632856Srdreslin@umich.edu{ 642856Srdreslin@umich.edu if (if_name == "dcache_port") 652856Srdreslin@umich.edu return &dcachePort; 662856Srdreslin@umich.edu else if (if_name == "icache_port") 672856Srdreslin@umich.edu return &icachePort; 682856Srdreslin@umich.edu else 692856Srdreslin@umich.edu panic("No Such Port\n"); 702856Srdreslin@umich.edu} 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::init() 742623SN/A{ 752623SN/A BaseCPU::init(); 762623SN/A#if FULL_SYSTEM 772680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 782680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 792623SN/A 802623SN/A // initialize CPU, including PC 812680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 822623SN/A } 832623SN/A#endif 842623SN/A} 852623SN/A 862623SN/Abool 873349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 882623SN/A{ 893184Srdreslin@umich.edu panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 902623SN/A return true; 912623SN/A} 922623SN/A 932623SN/ATick 943349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 952623SN/A{ 963310Srdreslin@umich.edu //Snooping a coherence request, just return 973649Srdreslin@umich.edu return 0; 982623SN/A} 992623SN/A 1002623SN/Avoid 1013349Sbinkertn@umich.eduAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 1022623SN/A{ 1033184Srdreslin@umich.edu //No internal storage to update, just return 1043184Srdreslin@umich.edu return; 1052623SN/A} 1062623SN/A 1072623SN/Avoid 1082623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1092623SN/A{ 1103647Srdreslin@umich.edu if (status == RangeChange) { 1113647Srdreslin@umich.edu if (!snoopRangeSent) { 1123647Srdreslin@umich.edu snoopRangeSent = true; 1133647Srdreslin@umich.edu sendStatusChange(Port::RangeChange); 1143647Srdreslin@umich.edu } 1152626SN/A return; 1163647Srdreslin@umich.edu } 1172626SN/A 1182623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1192623SN/A} 1202623SN/A 1212657Ssaidi@eecs.umich.eduvoid 1222623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1232623SN/A{ 1242623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1252623SN/A} 1262623SN/A 1272623SN/A 1282623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1292623SN/A : BaseSimpleCPU(p), tickEvent(this), 1302623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1312640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1322623SN/A{ 1332623SN/A _status = Idle; 1342623SN/A 1353647Srdreslin@umich.edu icachePort.snoopRangeSent = false; 1363647Srdreslin@umich.edu dcachePort.snoopRangeSent = false; 1373647Srdreslin@umich.edu 1382663Sstever@eecs.umich.edu ifetch_req = new Request(); 1393170Sstever@eecs.umich.edu ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 1402641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 1412623SN/A ifetch_pkt->dataStatic(&inst); 1422623SN/A 1432663Sstever@eecs.umich.edu data_read_req = new Request(); 1443170Sstever@eecs.umich.edu data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1452641Sstever@eecs.umich.edu data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 1462641Sstever@eecs.umich.edu Packet::Broadcast); 1472623SN/A data_read_pkt->dataStatic(&dataReg); 1482623SN/A 1492663Sstever@eecs.umich.edu data_write_req = new Request(); 1503170Sstever@eecs.umich.edu data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1512641Sstever@eecs.umich.edu data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 1522641Sstever@eecs.umich.edu Packet::Broadcast); 1532623SN/A} 1542623SN/A 1552623SN/A 1562623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1572623SN/A{ 1582623SN/A} 1592623SN/A 1602623SN/Avoid 1612623SN/AAtomicSimpleCPU::serialize(ostream &os) 1622623SN/A{ 1632915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1642915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1653177Shsul@eecs.umich.edu Status _status = status(); 1663177Shsul@eecs.umich.edu SERIALIZE_ENUM(_status); 1673145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1682623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1692623SN/A tickEvent.serialize(os); 1702623SN/A} 1712623SN/A 1722623SN/Avoid 1732623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1742623SN/A{ 1752915Sktlim@umich.edu SimObject::State so_state; 1762915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1773177Shsul@eecs.umich.edu UNSERIALIZE_ENUM(_status); 1783145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1792915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1802915Sktlim@umich.edu} 1812915Sktlim@umich.edu 1822915Sktlim@umich.eduvoid 1832915Sktlim@umich.eduAtomicSimpleCPU::resume() 1842915Sktlim@umich.edu{ 1853324Shsul@eecs.umich.edu if (_status != SwitchedOut && _status != Idle) { 1863201Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Atomic); 1873324Shsul@eecs.umich.edu 1883324Shsul@eecs.umich.edu changeState(SimObject::Running); 1893324Shsul@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 1903431Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 1913495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 1923431Sgblack@eecs.umich.edu } 1933324Shsul@eecs.umich.edu } 1942915Sktlim@umich.edu } 1952623SN/A} 1962623SN/A 1972623SN/Avoid 1982798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1992623SN/A{ 2002798Sktlim@umich.edu assert(status() == Running || status() == Idle); 2012798Sktlim@umich.edu _status = SwitchedOut; 2022623SN/A 2032798Sktlim@umich.edu tickEvent.squash(); 2042623SN/A} 2052623SN/A 2062623SN/A 2072623SN/Avoid 2082623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2092623SN/A{ 2102623SN/A BaseCPU::takeOverFrom(oldCPU); 2112623SN/A 2122623SN/A assert(!tickEvent.scheduled()); 2132623SN/A 2142680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2152623SN/A // running and schedule its tick event. 2162680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2172680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2182680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2192623SN/A _status = Running; 2203495Sktlim@umich.edu tickEvent.schedule(nextCycle()); 2212623SN/A break; 2222623SN/A } 2232623SN/A } 2243512Sktlim@umich.edu if (_status != Running) { 2253512Sktlim@umich.edu _status = Idle; 2263512Sktlim@umich.edu } 2272623SN/A} 2282623SN/A 2292623SN/A 2302623SN/Avoid 2312623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2322623SN/A{ 2332623SN/A assert(thread_num == 0); 2342683Sktlim@umich.edu assert(thread); 2352623SN/A 2362623SN/A assert(_status == Idle); 2372623SN/A assert(!tickEvent.scheduled()); 2382623SN/A 2392623SN/A notIdleFraction++; 2403430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2413495Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 2422623SN/A _status = Running; 2432623SN/A} 2442623SN/A 2452623SN/A 2462623SN/Avoid 2472623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2482623SN/A{ 2492623SN/A assert(thread_num == 0); 2502683Sktlim@umich.edu assert(thread); 2512623SN/A 2522623SN/A assert(_status == Running); 2532626SN/A 2542626SN/A // tick event may not be scheduled if this gets called from inside 2552626SN/A // an instruction's execution, e.g. "quiesce" 2562626SN/A if (tickEvent.scheduled()) 2572626SN/A tickEvent.deschedule(); 2582623SN/A 2592623SN/A notIdleFraction--; 2602623SN/A _status = Idle; 2612623SN/A} 2622623SN/A 2632623SN/A 2642623SN/Atemplate <class T> 2652623SN/AFault 2662623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2672623SN/A{ 2683169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2693169Sstever@eecs.umich.edu Request *req = data_read_req; 2703349Sbinkertn@umich.edu PacketPtr pkt = data_read_pkt; 2713169Sstever@eecs.umich.edu 2723169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2732623SN/A 2742623SN/A if (traceData) { 2752623SN/A traceData->setAddr(addr); 2762623SN/A } 2772623SN/A 2782623SN/A // translate to physical address 2793169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2802623SN/A 2812623SN/A // Now do the access. 2822623SN/A if (fault == NoFault) { 2833169Sstever@eecs.umich.edu pkt->reinitFromRequest(); 2842623SN/A 2853169Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 2862623SN/A dcache_access = true; 2872623SN/A 2883169Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 2893169Sstever@eecs.umich.edu data = pkt->get<T>(); 2903170Sstever@eecs.umich.edu 2913170Sstever@eecs.umich.edu if (req->isLocked()) { 2923170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, req); 2933170Sstever@eecs.umich.edu } 2942623SN/A } 2952623SN/A 2962623SN/A // This will need a new way to tell if it has a dcache attached. 2973172Sstever@eecs.umich.edu if (req->isUncacheable()) 2982623SN/A recordEvent("Uncached Read"); 2992623SN/A 3002623SN/A return fault; 3012623SN/A} 3022623SN/A 3032623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3042623SN/A 3052623SN/Atemplate 3062623SN/AFault 3072623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 3082623SN/A 3092623SN/Atemplate 3102623SN/AFault 3112623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3122623SN/A 3132623SN/Atemplate 3142623SN/AFault 3152623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3162623SN/A 3172623SN/Atemplate 3182623SN/AFault 3192623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3202623SN/A 3212623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3222623SN/A 3232623SN/Atemplate<> 3242623SN/AFault 3252623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3262623SN/A{ 3272623SN/A return read(addr, *(uint64_t*)&data, flags); 3282623SN/A} 3292623SN/A 3302623SN/Atemplate<> 3312623SN/AFault 3322623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3332623SN/A{ 3342623SN/A return read(addr, *(uint32_t*)&data, flags); 3352623SN/A} 3362623SN/A 3372623SN/A 3382623SN/Atemplate<> 3392623SN/AFault 3402623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3412623SN/A{ 3422623SN/A return read(addr, (uint32_t&)data, flags); 3432623SN/A} 3442623SN/A 3452623SN/A 3462623SN/Atemplate <class T> 3472623SN/AFault 3482623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3492623SN/A{ 3503169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3513169Sstever@eecs.umich.edu Request *req = data_write_req; 3523349Sbinkertn@umich.edu PacketPtr pkt = data_write_pkt; 3533169Sstever@eecs.umich.edu 3543169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3552623SN/A 3562623SN/A if (traceData) { 3572623SN/A traceData->setAddr(addr); 3582623SN/A } 3592623SN/A 3602623SN/A // translate to physical address 3613169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3622623SN/A 3632623SN/A // Now do the access. 3642623SN/A if (fault == NoFault) { 3653170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3662623SN/A 3673170Sstever@eecs.umich.edu if (req->isLocked()) { 3683170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3693170Sstever@eecs.umich.edu } 3702623SN/A 3713170Sstever@eecs.umich.edu if (do_access) { 3723170Sstever@eecs.umich.edu data = htog(data); 3733170Sstever@eecs.umich.edu pkt->reinitFromRequest(); 3743170Sstever@eecs.umich.edu pkt->dataStatic(&data); 3752631SN/A 3763170Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 3773170Sstever@eecs.umich.edu dcache_access = true; 3783170Sstever@eecs.umich.edu 3793170Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 3803170Sstever@eecs.umich.edu } 3813170Sstever@eecs.umich.edu 3823170Sstever@eecs.umich.edu if (req->isLocked()) { 3833170Sstever@eecs.umich.edu uint64_t scResult = req->getScResult(); 3843170Sstever@eecs.umich.edu if (scResult != 0) { 3853170Sstever@eecs.umich.edu // clear failure counter 3863170Sstever@eecs.umich.edu thread->setStCondFailures(0); 3873170Sstever@eecs.umich.edu } 3883170Sstever@eecs.umich.edu if (res) { 3893170Sstever@eecs.umich.edu *res = req->getScResult(); 3903170Sstever@eecs.umich.edu } 3912631SN/A } 3922623SN/A } 3932623SN/A 3942623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3953172Sstever@eecs.umich.edu if (req->isUncacheable()) 3962623SN/A recordEvent("Uncached Write"); 3972623SN/A 3982623SN/A // If the write needs to have a fault on the access, consider calling 3992623SN/A // changeStatus() and changing it to "bad addr write" or something. 4002623SN/A return fault; 4012623SN/A} 4022623SN/A 4032623SN/A 4042623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4052623SN/Atemplate 4062623SN/AFault 4072623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 4082623SN/A unsigned flags, uint64_t *res); 4092623SN/A 4102623SN/Atemplate 4112623SN/AFault 4122623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 4132623SN/A unsigned flags, uint64_t *res); 4142623SN/A 4152623SN/Atemplate 4162623SN/AFault 4172623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 4182623SN/A unsigned flags, uint64_t *res); 4192623SN/A 4202623SN/Atemplate 4212623SN/AFault 4222623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 4232623SN/A unsigned flags, uint64_t *res); 4242623SN/A 4252623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4262623SN/A 4272623SN/Atemplate<> 4282623SN/AFault 4292623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4302623SN/A{ 4312623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4322623SN/A} 4332623SN/A 4342623SN/Atemplate<> 4352623SN/AFault 4362623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4372623SN/A{ 4382623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4392623SN/A} 4402623SN/A 4412623SN/A 4422623SN/Atemplate<> 4432623SN/AFault 4442623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4452623SN/A{ 4462623SN/A return write((uint32_t)data, addr, flags, res); 4472623SN/A} 4482623SN/A 4492623SN/A 4502623SN/Avoid 4512623SN/AAtomicSimpleCPU::tick() 4522623SN/A{ 4532623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4542623SN/A 4552623SN/A for (int i = 0; i < width; ++i) { 4562623SN/A numCycles++; 4572623SN/A 4583387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 4593387Sgblack@eecs.umich.edu checkForInterrupts(); 4602626SN/A 4612662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4622623SN/A 4632623SN/A if (fault == NoFault) { 4642662Sstever@eecs.umich.edu ifetch_pkt->reinitFromRequest(); 4652662Sstever@eecs.umich.edu 4662662Sstever@eecs.umich.edu Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 4672623SN/A // ifetch_req is initialized to read the instruction directly 4682623SN/A // into the CPU object's inst field. 4692623SN/A 4702623SN/A dcache_access = false; // assume no dcache access 4712623SN/A preExecute(); 4722623SN/A fault = curStaticInst->execute(this, traceData); 4732623SN/A postExecute(); 4742623SN/A 4752623SN/A if (simulate_stalls) { 4762662Sstever@eecs.umich.edu Tick icache_stall = icache_latency - cycles(1); 4772623SN/A Tick dcache_stall = 4782662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 4792803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 4802803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 4812803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 4822803Ssaidi@eecs.umich.edu else 4832803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 4842623SN/A } 4852623SN/A 4862623SN/A } 4872623SN/A 4882623SN/A advancePC(fault); 4892623SN/A } 4902623SN/A 4912626SN/A if (_status != Idle) 4922626SN/A tickEvent.schedule(curTick + latency); 4932623SN/A} 4942623SN/A 4952623SN/A 4962623SN/A//////////////////////////////////////////////////////////////////////// 4972623SN/A// 4982623SN/A// AtomicSimpleCPU Simulation Object 4992623SN/A// 5002623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5012623SN/A 5022623SN/A Param<Counter> max_insts_any_thread; 5032623SN/A Param<Counter> max_insts_all_threads; 5042623SN/A Param<Counter> max_loads_any_thread; 5052623SN/A Param<Counter> max_loads_all_threads; 5063119Sktlim@umich.edu Param<Tick> progress_interval; 5072901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 5083170Sstever@eecs.umich.edu Param<int> cpu_id; 5092623SN/A 5102623SN/A#if FULL_SYSTEM 5113453Sgblack@eecs.umich.edu SimObjectParam<TheISA::ITB *> itb; 5123453Sgblack@eecs.umich.edu SimObjectParam<TheISA::DTB *> dtb; 5132623SN/A Param<Tick> profile; 5143617Sbinkertn@umich.edu 5153617Sbinkertn@umich.edu Param<bool> do_quiesce; 5163617Sbinkertn@umich.edu Param<bool> do_checkpoint_insts; 5173617Sbinkertn@umich.edu Param<bool> do_statistics_insts; 5182623SN/A#else 5192623SN/A SimObjectParam<Process *> workload; 5202623SN/A#endif // FULL_SYSTEM 5212623SN/A 5222623SN/A Param<int> clock; 5233661Srdreslin@umich.edu Param<int> phase; 5242623SN/A 5252623SN/A Param<bool> defer_registration; 5262623SN/A Param<int> width; 5272623SN/A Param<bool> function_trace; 5282623SN/A Param<Tick> function_trace_start; 5292623SN/A Param<bool> simulate_stalls; 5302623SN/A 5312623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5322623SN/A 5332623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5342623SN/A 5352623SN/A INIT_PARAM(max_insts_any_thread, 5362623SN/A "terminate when any thread reaches this inst count"), 5372623SN/A INIT_PARAM(max_insts_all_threads, 5382623SN/A "terminate when all threads have reached this inst count"), 5392623SN/A INIT_PARAM(max_loads_any_thread, 5402623SN/A "terminate when any thread reaches this load count"), 5412623SN/A INIT_PARAM(max_loads_all_threads, 5422623SN/A "terminate when all threads have reached this load count"), 5433119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 5442901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 5453170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 5462623SN/A 5472623SN/A#if FULL_SYSTEM 5482623SN/A INIT_PARAM(itb, "Instruction TLB"), 5492623SN/A INIT_PARAM(dtb, "Data TLB"), 5502623SN/A INIT_PARAM(profile, ""), 5513617Sbinkertn@umich.edu INIT_PARAM(do_quiesce, ""), 5523617Sbinkertn@umich.edu INIT_PARAM(do_checkpoint_insts, ""), 5533617Sbinkertn@umich.edu INIT_PARAM(do_statistics_insts, ""), 5542623SN/A#else 5552623SN/A INIT_PARAM(workload, "processes to run"), 5562623SN/A#endif // FULL_SYSTEM 5572623SN/A 5582623SN/A INIT_PARAM(clock, "clock speed"), 5593661Srdreslin@umich.edu INIT_PARAM_DFLT(phase, "clock phase", 0), 5602623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5612623SN/A INIT_PARAM(width, "cpu width"), 5622623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5632623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5642623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5652623SN/A 5662623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5672623SN/A 5682623SN/A 5692623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU) 5702623SN/A{ 5712623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5722623SN/A params->name = getInstanceName(); 5732623SN/A params->numberOfThreads = 1; 5742623SN/A params->max_insts_any_thread = max_insts_any_thread; 5752623SN/A params->max_insts_all_threads = max_insts_all_threads; 5762623SN/A params->max_loads_any_thread = max_loads_any_thread; 5772623SN/A params->max_loads_all_threads = max_loads_all_threads; 5783119Sktlim@umich.edu params->progress_interval = progress_interval; 5792623SN/A params->deferRegistration = defer_registration; 5803661Srdreslin@umich.edu params->phase = phase; 5812623SN/A params->clock = clock; 5822623SN/A params->functionTrace = function_trace; 5832623SN/A params->functionTraceStart = function_trace_start; 5842623SN/A params->width = width; 5852623SN/A params->simulate_stalls = simulate_stalls; 5862901Ssaidi@eecs.umich.edu params->system = system; 5873170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 5882623SN/A 5892623SN/A#if FULL_SYSTEM 5902623SN/A params->itb = itb; 5912623SN/A params->dtb = dtb; 5922623SN/A params->profile = profile; 5933617Sbinkertn@umich.edu params->do_quiesce = do_quiesce; 5943617Sbinkertn@umich.edu params->do_checkpoint_insts = do_checkpoint_insts; 5953617Sbinkertn@umich.edu params->do_statistics_insts = do_statistics_insts; 5962623SN/A#else 5972623SN/A params->process = workload; 5982623SN/A#endif 5992623SN/A 6002623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 6012623SN/A return cpu; 6022623SN/A} 6032623SN/A 6042623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 6052623SN/A 606