atomic.cc revision 3172
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 313170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 322623SN/A#include "arch/utility.hh" 332623SN/A#include "cpu/exetrace.hh" 342623SN/A#include "cpu/simple/atomic.hh" 352623SN/A#include "mem/packet_impl.hh" 362623SN/A#include "sim/builder.hh" 372901Ssaidi@eecs.umich.edu#include "sim/system.hh" 382623SN/A 392623SN/Ausing namespace std; 402623SN/Ausing namespace TheISA; 412623SN/A 422623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 432623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 442623SN/A{ 452623SN/A} 462623SN/A 472623SN/A 482623SN/Avoid 492623SN/AAtomicSimpleCPU::TickEvent::process() 502623SN/A{ 512623SN/A cpu->tick(); 522623SN/A} 532623SN/A 542623SN/Aconst char * 552623SN/AAtomicSimpleCPU::TickEvent::description() 562623SN/A{ 572623SN/A return "AtomicSimpleCPU tick event"; 582623SN/A} 592623SN/A 602856Srdreslin@umich.eduPort * 612856Srdreslin@umich.eduAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 622856Srdreslin@umich.edu{ 632856Srdreslin@umich.edu if (if_name == "dcache_port") 642856Srdreslin@umich.edu return &dcachePort; 652856Srdreslin@umich.edu else if (if_name == "icache_port") 662856Srdreslin@umich.edu return &icachePort; 672856Srdreslin@umich.edu else 682856Srdreslin@umich.edu panic("No Such Port\n"); 692856Srdreslin@umich.edu} 702623SN/A 712623SN/Avoid 722623SN/AAtomicSimpleCPU::init() 732623SN/A{ 742623SN/A //Create Memory Ports (conect them up) 752856Srdreslin@umich.edu// Port *mem_dport = mem->getPort(""); 762856Srdreslin@umich.edu// dcachePort.setPeer(mem_dport); 772856Srdreslin@umich.edu// mem_dport->setPeer(&dcachePort); 782623SN/A 792856Srdreslin@umich.edu// Port *mem_iport = mem->getPort(""); 802856Srdreslin@umich.edu// icachePort.setPeer(mem_iport); 812856Srdreslin@umich.edu// mem_iport->setPeer(&icachePort); 822623SN/A 832623SN/A BaseCPU::init(); 842623SN/A#if FULL_SYSTEM 852680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 862680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 872623SN/A 882623SN/A // initialize CPU, including PC 892680Sktlim@umich.edu TheISA::initCPU(tc, tc->readCpuId()); 902623SN/A } 912623SN/A#endif 922623SN/A} 932623SN/A 942623SN/Abool 952630SN/AAtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 962623SN/A{ 972623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 982623SN/A return true; 992623SN/A} 1002623SN/A 1012623SN/ATick 1022630SN/AAtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 1032623SN/A{ 1042623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 1052623SN/A return curTick; 1062623SN/A} 1072623SN/A 1082623SN/Avoid 1092630SN/AAtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 1102623SN/A{ 1112623SN/A panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 1122623SN/A} 1132623SN/A 1142623SN/Avoid 1152623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1162623SN/A{ 1172626SN/A if (status == RangeChange) 1182626SN/A return; 1192626SN/A 1202623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1212623SN/A} 1222623SN/A 1232657Ssaidi@eecs.umich.eduvoid 1242623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1252623SN/A{ 1262623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1272623SN/A} 1282623SN/A 1292623SN/A 1302623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1312623SN/A : BaseSimpleCPU(p), tickEvent(this), 1322623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1332640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1342623SN/A{ 1352623SN/A _status = Idle; 1362623SN/A 1372663Sstever@eecs.umich.edu ifetch_req = new Request(); 1383170Sstever@eecs.umich.edu ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 1392641Sstever@eecs.umich.edu ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 1402623SN/A ifetch_pkt->dataStatic(&inst); 1412623SN/A 1422663Sstever@eecs.umich.edu data_read_req = new Request(); 1433170Sstever@eecs.umich.edu data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1442641Sstever@eecs.umich.edu data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 1452641Sstever@eecs.umich.edu Packet::Broadcast); 1462623SN/A data_read_pkt->dataStatic(&dataReg); 1472623SN/A 1482663Sstever@eecs.umich.edu data_write_req = new Request(); 1493170Sstever@eecs.umich.edu data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 1502641Sstever@eecs.umich.edu data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 1512641Sstever@eecs.umich.edu Packet::Broadcast); 1522623SN/A} 1532623SN/A 1542623SN/A 1552623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1562623SN/A{ 1572623SN/A} 1582623SN/A 1592623SN/Avoid 1602623SN/AAtomicSimpleCPU::serialize(ostream &os) 1612623SN/A{ 1622915Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 1632915Sktlim@umich.edu SERIALIZE_ENUM(so_state); 1643145Shsul@eecs.umich.edu BaseSimpleCPU::serialize(os); 1652623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1662623SN/A tickEvent.serialize(os); 1672623SN/A} 1682623SN/A 1692623SN/Avoid 1702623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1712623SN/A{ 1722915Sktlim@umich.edu SimObject::State so_state; 1732915Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 1743145Shsul@eecs.umich.edu BaseSimpleCPU::unserialize(cp, section); 1752915Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1762915Sktlim@umich.edu} 1772915Sktlim@umich.edu 1782915Sktlim@umich.eduvoid 1792915Sktlim@umich.eduAtomicSimpleCPU::resume() 1802915Sktlim@umich.edu{ 1812926Sktlim@umich.edu assert(system->getMemoryMode() == System::Atomic); 1822926Sktlim@umich.edu changeState(SimObject::Running); 1832915Sktlim@umich.edu if (thread->status() == ThreadContext::Active) { 1842915Sktlim@umich.edu if (!tickEvent.scheduled()) 1852915Sktlim@umich.edu tickEvent.schedule(curTick); 1862915Sktlim@umich.edu } 1872623SN/A} 1882623SN/A 1892623SN/Avoid 1902798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1912623SN/A{ 1922798Sktlim@umich.edu assert(status() == Running || status() == Idle); 1932798Sktlim@umich.edu _status = SwitchedOut; 1942623SN/A 1952798Sktlim@umich.edu tickEvent.squash(); 1962623SN/A} 1972623SN/A 1982623SN/A 1992623SN/Avoid 2002623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2012623SN/A{ 2022623SN/A BaseCPU::takeOverFrom(oldCPU); 2032623SN/A 2042623SN/A assert(!tickEvent.scheduled()); 2052623SN/A 2062680Sktlim@umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2072623SN/A // running and schedule its tick event. 2082680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2092680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 2102680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2112623SN/A _status = Running; 2122623SN/A tickEvent.schedule(curTick); 2132623SN/A break; 2142623SN/A } 2152623SN/A } 2162623SN/A} 2172623SN/A 2182623SN/A 2192623SN/Avoid 2202623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2212623SN/A{ 2222623SN/A assert(thread_num == 0); 2232683Sktlim@umich.edu assert(thread); 2242623SN/A 2252623SN/A assert(_status == Idle); 2262623SN/A assert(!tickEvent.scheduled()); 2272623SN/A 2282623SN/A notIdleFraction++; 2292623SN/A tickEvent.schedule(curTick + cycles(delay)); 2302623SN/A _status = Running; 2312623SN/A} 2322623SN/A 2332623SN/A 2342623SN/Avoid 2352623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2362623SN/A{ 2372623SN/A assert(thread_num == 0); 2382683Sktlim@umich.edu assert(thread); 2392623SN/A 2402623SN/A assert(_status == Running); 2412626SN/A 2422626SN/A // tick event may not be scheduled if this gets called from inside 2432626SN/A // an instruction's execution, e.g. "quiesce" 2442626SN/A if (tickEvent.scheduled()) 2452626SN/A tickEvent.deschedule(); 2462623SN/A 2472623SN/A notIdleFraction--; 2482623SN/A _status = Idle; 2492623SN/A} 2502623SN/A 2512623SN/A 2522623SN/Atemplate <class T> 2532623SN/AFault 2542623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2552623SN/A{ 2563169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 2573169Sstever@eecs.umich.edu Request *req = data_read_req; 2583169Sstever@eecs.umich.edu Packet *pkt = data_read_pkt; 2593169Sstever@eecs.umich.edu 2603169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2612623SN/A 2622623SN/A if (traceData) { 2632623SN/A traceData->setAddr(addr); 2642623SN/A } 2652623SN/A 2662623SN/A // translate to physical address 2673169Sstever@eecs.umich.edu Fault fault = thread->translateDataReadReq(req); 2682623SN/A 2692623SN/A // Now do the access. 2702623SN/A if (fault == NoFault) { 2713169Sstever@eecs.umich.edu pkt->reinitFromRequest(); 2722623SN/A 2733169Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 2742623SN/A dcache_access = true; 2752623SN/A 2763169Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 2773169Sstever@eecs.umich.edu data = pkt->get<T>(); 2783170Sstever@eecs.umich.edu 2793170Sstever@eecs.umich.edu if (req->isLocked()) { 2803170Sstever@eecs.umich.edu TheISA::handleLockedRead(thread, req); 2813170Sstever@eecs.umich.edu } 2822623SN/A } 2832623SN/A 2842623SN/A // This will need a new way to tell if it has a dcache attached. 2853172Sstever@eecs.umich.edu if (req->isUncacheable()) 2862623SN/A recordEvent("Uncached Read"); 2872623SN/A 2882623SN/A return fault; 2892623SN/A} 2902623SN/A 2912623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2922623SN/A 2932623SN/Atemplate 2942623SN/AFault 2952623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2962623SN/A 2972623SN/Atemplate 2982623SN/AFault 2992623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 3002623SN/A 3012623SN/Atemplate 3022623SN/AFault 3032623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 3042623SN/A 3052623SN/Atemplate 3062623SN/AFault 3072623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 3082623SN/A 3092623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3102623SN/A 3112623SN/Atemplate<> 3122623SN/AFault 3132623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3142623SN/A{ 3152623SN/A return read(addr, *(uint64_t*)&data, flags); 3162623SN/A} 3172623SN/A 3182623SN/Atemplate<> 3192623SN/AFault 3202623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3212623SN/A{ 3222623SN/A return read(addr, *(uint32_t*)&data, flags); 3232623SN/A} 3242623SN/A 3252623SN/A 3262623SN/Atemplate<> 3272623SN/AFault 3282623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3292623SN/A{ 3302623SN/A return read(addr, (uint32_t&)data, flags); 3312623SN/A} 3322623SN/A 3332623SN/A 3342623SN/Atemplate <class T> 3352623SN/AFault 3362623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3372623SN/A{ 3383169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3393169Sstever@eecs.umich.edu Request *req = data_write_req; 3403169Sstever@eecs.umich.edu Packet *pkt = data_write_pkt; 3413169Sstever@eecs.umich.edu 3423169Sstever@eecs.umich.edu req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 3432623SN/A 3442623SN/A if (traceData) { 3452623SN/A traceData->setAddr(addr); 3462623SN/A } 3472623SN/A 3482623SN/A // translate to physical address 3493169Sstever@eecs.umich.edu Fault fault = thread->translateDataWriteReq(req); 3502623SN/A 3512623SN/A // Now do the access. 3522623SN/A if (fault == NoFault) { 3533170Sstever@eecs.umich.edu bool do_access = true; // flag to suppress cache access 3542623SN/A 3553170Sstever@eecs.umich.edu if (req->isLocked()) { 3563170Sstever@eecs.umich.edu do_access = TheISA::handleLockedWrite(thread, req); 3573170Sstever@eecs.umich.edu } 3582623SN/A 3593170Sstever@eecs.umich.edu if (do_access) { 3603170Sstever@eecs.umich.edu data = htog(data); 3613170Sstever@eecs.umich.edu pkt->reinitFromRequest(); 3623170Sstever@eecs.umich.edu pkt->dataStatic(&data); 3632631SN/A 3643170Sstever@eecs.umich.edu dcache_latency = dcachePort.sendAtomic(pkt); 3653170Sstever@eecs.umich.edu dcache_access = true; 3663170Sstever@eecs.umich.edu 3673170Sstever@eecs.umich.edu assert(pkt->result == Packet::Success); 3683170Sstever@eecs.umich.edu } 3693170Sstever@eecs.umich.edu 3703170Sstever@eecs.umich.edu if (req->isLocked()) { 3713170Sstever@eecs.umich.edu uint64_t scResult = req->getScResult(); 3723170Sstever@eecs.umich.edu if (scResult != 0) { 3733170Sstever@eecs.umich.edu // clear failure counter 3743170Sstever@eecs.umich.edu thread->setStCondFailures(0); 3753170Sstever@eecs.umich.edu } 3763170Sstever@eecs.umich.edu if (res) { 3773170Sstever@eecs.umich.edu *res = req->getScResult(); 3783170Sstever@eecs.umich.edu } 3792631SN/A } 3802623SN/A } 3812623SN/A 3822623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3833172Sstever@eecs.umich.edu if (req->isUncacheable()) 3842623SN/A recordEvent("Uncached Write"); 3852623SN/A 3862623SN/A // If the write needs to have a fault on the access, consider calling 3872623SN/A // changeStatus() and changing it to "bad addr write" or something. 3882623SN/A return fault; 3892623SN/A} 3902623SN/A 3912623SN/A 3922623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3932623SN/Atemplate 3942623SN/AFault 3952623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 3962623SN/A unsigned flags, uint64_t *res); 3972623SN/A 3982623SN/Atemplate 3992623SN/AFault 4002623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 4012623SN/A unsigned flags, uint64_t *res); 4022623SN/A 4032623SN/Atemplate 4042623SN/AFault 4052623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 4062623SN/A unsigned flags, uint64_t *res); 4072623SN/A 4082623SN/Atemplate 4092623SN/AFault 4102623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 4112623SN/A unsigned flags, uint64_t *res); 4122623SN/A 4132623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4142623SN/A 4152623SN/Atemplate<> 4162623SN/AFault 4172623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 4182623SN/A{ 4192623SN/A return write(*(uint64_t*)&data, addr, flags, res); 4202623SN/A} 4212623SN/A 4222623SN/Atemplate<> 4232623SN/AFault 4242623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4252623SN/A{ 4262623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4272623SN/A} 4282623SN/A 4292623SN/A 4302623SN/Atemplate<> 4312623SN/AFault 4322623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4332623SN/A{ 4342623SN/A return write((uint32_t)data, addr, flags, res); 4352623SN/A} 4362623SN/A 4372623SN/A 4382623SN/Avoid 4392623SN/AAtomicSimpleCPU::tick() 4402623SN/A{ 4412623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4422623SN/A 4432623SN/A for (int i = 0; i < width; ++i) { 4442623SN/A numCycles++; 4452623SN/A 4462626SN/A checkForInterrupts(); 4472626SN/A 4482662Sstever@eecs.umich.edu Fault fault = setupFetchRequest(ifetch_req); 4492623SN/A 4502623SN/A if (fault == NoFault) { 4512662Sstever@eecs.umich.edu ifetch_pkt->reinitFromRequest(); 4522662Sstever@eecs.umich.edu 4532662Sstever@eecs.umich.edu Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 4542623SN/A // ifetch_req is initialized to read the instruction directly 4552623SN/A // into the CPU object's inst field. 4562623SN/A 4572623SN/A dcache_access = false; // assume no dcache access 4582623SN/A preExecute(); 4592623SN/A fault = curStaticInst->execute(this, traceData); 4602623SN/A postExecute(); 4612623SN/A 4622623SN/A if (simulate_stalls) { 4632662Sstever@eecs.umich.edu Tick icache_stall = icache_latency - cycles(1); 4642623SN/A Tick dcache_stall = 4652662Sstever@eecs.umich.edu dcache_access ? dcache_latency - cycles(1) : 0; 4662803Ssaidi@eecs.umich.edu Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 4672803Ssaidi@eecs.umich.edu if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 4682803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles+1); 4692803Ssaidi@eecs.umich.edu else 4702803Ssaidi@eecs.umich.edu latency += cycles(stall_cycles); 4712623SN/A } 4722623SN/A 4732623SN/A } 4742623SN/A 4752623SN/A advancePC(fault); 4762623SN/A } 4772623SN/A 4782626SN/A if (_status != Idle) 4792626SN/A tickEvent.schedule(curTick + latency); 4802623SN/A} 4812623SN/A 4822623SN/A 4832623SN/A//////////////////////////////////////////////////////////////////////// 4842623SN/A// 4852623SN/A// AtomicSimpleCPU Simulation Object 4862623SN/A// 4872623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4882623SN/A 4892623SN/A Param<Counter> max_insts_any_thread; 4902623SN/A Param<Counter> max_insts_all_threads; 4912623SN/A Param<Counter> max_loads_any_thread; 4922623SN/A Param<Counter> max_loads_all_threads; 4933119Sktlim@umich.edu Param<Tick> progress_interval; 4942623SN/A SimObjectParam<MemObject *> mem; 4952901Ssaidi@eecs.umich.edu SimObjectParam<System *> system; 4963170Sstever@eecs.umich.edu Param<int> cpu_id; 4972623SN/A 4982623SN/A#if FULL_SYSTEM 4992623SN/A SimObjectParam<AlphaITB *> itb; 5002623SN/A SimObjectParam<AlphaDTB *> dtb; 5012623SN/A Param<Tick> profile; 5022623SN/A#else 5032623SN/A SimObjectParam<Process *> workload; 5042623SN/A#endif // FULL_SYSTEM 5052623SN/A 5062623SN/A Param<int> clock; 5072623SN/A 5082623SN/A Param<bool> defer_registration; 5092623SN/A Param<int> width; 5102623SN/A Param<bool> function_trace; 5112623SN/A Param<Tick> function_trace_start; 5122623SN/A Param<bool> simulate_stalls; 5132623SN/A 5142623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5152623SN/A 5162623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5172623SN/A 5182623SN/A INIT_PARAM(max_insts_any_thread, 5192623SN/A "terminate when any thread reaches this inst count"), 5202623SN/A INIT_PARAM(max_insts_all_threads, 5212623SN/A "terminate when all threads have reached this inst count"), 5222623SN/A INIT_PARAM(max_loads_any_thread, 5232623SN/A "terminate when any thread reaches this load count"), 5242623SN/A INIT_PARAM(max_loads_all_threads, 5252623SN/A "terminate when all threads have reached this load count"), 5263119Sktlim@umich.edu INIT_PARAM(progress_interval, "Progress interval"), 5272623SN/A INIT_PARAM(mem, "memory"), 5282901Ssaidi@eecs.umich.edu INIT_PARAM(system, "system object"), 5293170Sstever@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 5302623SN/A 5312623SN/A#if FULL_SYSTEM 5322623SN/A INIT_PARAM(itb, "Instruction TLB"), 5332623SN/A INIT_PARAM(dtb, "Data TLB"), 5342623SN/A INIT_PARAM(profile, ""), 5352623SN/A#else 5362623SN/A INIT_PARAM(workload, "processes to run"), 5372623SN/A#endif // FULL_SYSTEM 5382623SN/A 5392623SN/A INIT_PARAM(clock, "clock speed"), 5402623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5412623SN/A INIT_PARAM(width, "cpu width"), 5422623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5432623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5442623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5452623SN/A 5462623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5472623SN/A 5482623SN/A 5492623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU) 5502623SN/A{ 5512623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5522623SN/A params->name = getInstanceName(); 5532623SN/A params->numberOfThreads = 1; 5542623SN/A params->max_insts_any_thread = max_insts_any_thread; 5552623SN/A params->max_insts_all_threads = max_insts_all_threads; 5562623SN/A params->max_loads_any_thread = max_loads_any_thread; 5572623SN/A params->max_loads_all_threads = max_loads_all_threads; 5583119Sktlim@umich.edu params->progress_interval = progress_interval; 5592623SN/A params->deferRegistration = defer_registration; 5602623SN/A params->clock = clock; 5612623SN/A params->functionTrace = function_trace; 5622623SN/A params->functionTraceStart = function_trace_start; 5632623SN/A params->width = width; 5642623SN/A params->simulate_stalls = simulate_stalls; 5652623SN/A params->mem = mem; 5662901Ssaidi@eecs.umich.edu params->system = system; 5673170Sstever@eecs.umich.edu params->cpu_id = cpu_id; 5682623SN/A 5692623SN/A#if FULL_SYSTEM 5702623SN/A params->itb = itb; 5712623SN/A params->dtb = dtb; 5722623SN/A params->profile = profile; 5732623SN/A#else 5742623SN/A params->process = workload; 5752623SN/A#endif 5762623SN/A 5772623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 5782623SN/A return cpu; 5792623SN/A} 5802623SN/A 5812623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 5822623SN/A 583