atomic.cc revision 2640
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A */ 282623SN/A 292623SN/A#include "arch/utility.hh" 302623SN/A#include "cpu/exetrace.hh" 312623SN/A#include "cpu/simple/atomic.hh" 322623SN/A#include "mem/packet_impl.hh" 332623SN/A#include "sim/builder.hh" 342623SN/A 352623SN/Ausing namespace std; 362623SN/Ausing namespace TheISA; 372623SN/A 382623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 392623SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 402623SN/A{ 412623SN/A} 422623SN/A 432623SN/A 442623SN/Avoid 452623SN/AAtomicSimpleCPU::TickEvent::process() 462623SN/A{ 472623SN/A cpu->tick(); 482623SN/A} 492623SN/A 502623SN/Aconst char * 512623SN/AAtomicSimpleCPU::TickEvent::description() 522623SN/A{ 532623SN/A return "AtomicSimpleCPU tick event"; 542623SN/A} 552623SN/A 562623SN/A 572623SN/Avoid 582623SN/AAtomicSimpleCPU::init() 592623SN/A{ 602623SN/A //Create Memory Ports (conect them up) 612623SN/A Port *mem_dport = mem->getPort(""); 622623SN/A dcachePort.setPeer(mem_dport); 632623SN/A mem_dport->setPeer(&dcachePort); 642623SN/A 652623SN/A Port *mem_iport = mem->getPort(""); 662623SN/A icachePort.setPeer(mem_iport); 672623SN/A mem_iport->setPeer(&icachePort); 682623SN/A 692623SN/A BaseCPU::init(); 702623SN/A#if FULL_SYSTEM 712623SN/A for (int i = 0; i < execContexts.size(); ++i) { 722623SN/A ExecContext *xc = execContexts[i]; 732623SN/A 742623SN/A // initialize CPU, including PC 752623SN/A TheISA::initCPU(xc, xc->readCpuId()); 762623SN/A } 772623SN/A#endif 782623SN/A} 792623SN/A 802623SN/Abool 812630SN/AAtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 822623SN/A{ 832623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 842623SN/A return true; 852623SN/A} 862623SN/A 872623SN/ATick 882630SN/AAtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 892623SN/A{ 902623SN/A panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 912623SN/A return curTick; 922623SN/A} 932623SN/A 942623SN/Avoid 952630SN/AAtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 962623SN/A{ 972623SN/A panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 982623SN/A} 992623SN/A 1002623SN/Avoid 1012623SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1022623SN/A{ 1032626SN/A if (status == RangeChange) 1042626SN/A return; 1052626SN/A 1062623SN/A panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 1072623SN/A} 1082623SN/A 1092623SN/APacket * 1102623SN/AAtomicSimpleCPU::CpuPort::recvRetry() 1112623SN/A{ 1122623SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1132623SN/A return NULL; 1142623SN/A} 1152623SN/A 1162623SN/A 1172623SN/AAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1182623SN/A : BaseSimpleCPU(p), tickEvent(this), 1192623SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1202640Sstever@eecs.umich.edu icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 1212623SN/A{ 1222623SN/A _status = Idle; 1232623SN/A 1242623SN/A ifetch_req = new Request(true); 1252623SN/A ifetch_req->setAsid(0); 1262623SN/A // @todo fix me and get the real cpu iD!!! 1272623SN/A ifetch_req->setCpuNum(0); 1282623SN/A ifetch_req->setSize(sizeof(MachInst)); 1292623SN/A ifetch_pkt = new Packet; 1302623SN/A ifetch_pkt->cmd = Read; 1312623SN/A ifetch_pkt->dataStatic(&inst); 1322623SN/A ifetch_pkt->req = ifetch_req; 1332623SN/A ifetch_pkt->size = sizeof(MachInst); 1342623SN/A ifetch_pkt->dest = Packet::Broadcast; 1352623SN/A 1362623SN/A data_read_req = new Request(true); 1372623SN/A // @todo fix me and get the real cpu iD!!! 1382623SN/A data_read_req->setCpuNum(0); 1392623SN/A data_read_req->setAsid(0); 1402623SN/A data_read_pkt = new Packet; 1412623SN/A data_read_pkt->cmd = Read; 1422623SN/A data_read_pkt->dataStatic(&dataReg); 1432623SN/A data_read_pkt->req = data_read_req; 1442623SN/A data_read_pkt->dest = Packet::Broadcast; 1452623SN/A 1462623SN/A data_write_req = new Request(true); 1472623SN/A // @todo fix me and get the real cpu iD!!! 1482623SN/A data_write_req->setCpuNum(0); 1492623SN/A data_write_req->setAsid(0); 1502623SN/A data_write_pkt = new Packet; 1512623SN/A data_write_pkt->cmd = Write; 1522623SN/A data_write_pkt->req = data_write_req; 1532623SN/A data_write_pkt->dest = Packet::Broadcast; 1542623SN/A} 1552623SN/A 1562623SN/A 1572623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1582623SN/A{ 1592623SN/A} 1602623SN/A 1612623SN/Avoid 1622623SN/AAtomicSimpleCPU::serialize(ostream &os) 1632623SN/A{ 1642623SN/A BaseSimpleCPU::serialize(os); 1652623SN/A SERIALIZE_ENUM(_status); 1662623SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1672623SN/A tickEvent.serialize(os); 1682623SN/A} 1692623SN/A 1702623SN/Avoid 1712623SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1722623SN/A{ 1732623SN/A BaseSimpleCPU::unserialize(cp, section); 1742623SN/A UNSERIALIZE_ENUM(_status); 1752623SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1762623SN/A} 1772623SN/A 1782623SN/Avoid 1792623SN/AAtomicSimpleCPU::switchOut(Sampler *s) 1802623SN/A{ 1812623SN/A sampler = s; 1822623SN/A if (status() == Running) { 1832623SN/A _status = SwitchedOut; 1842623SN/A 1852623SN/A tickEvent.squash(); 1862623SN/A } 1872623SN/A sampler->signalSwitched(); 1882623SN/A} 1892623SN/A 1902623SN/A 1912623SN/Avoid 1922623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1932623SN/A{ 1942623SN/A BaseCPU::takeOverFrom(oldCPU); 1952623SN/A 1962623SN/A assert(!tickEvent.scheduled()); 1972623SN/A 1982623SN/A // if any of this CPU's ExecContexts are active, mark the CPU as 1992623SN/A // running and schedule its tick event. 2002623SN/A for (int i = 0; i < execContexts.size(); ++i) { 2012623SN/A ExecContext *xc = execContexts[i]; 2022623SN/A if (xc->status() == ExecContext::Active && _status != Running) { 2032623SN/A _status = Running; 2042623SN/A tickEvent.schedule(curTick); 2052623SN/A break; 2062623SN/A } 2072623SN/A } 2082623SN/A} 2092623SN/A 2102623SN/A 2112623SN/Avoid 2122623SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 2132623SN/A{ 2142623SN/A assert(thread_num == 0); 2152623SN/A assert(cpuXC); 2162623SN/A 2172623SN/A assert(_status == Idle); 2182623SN/A assert(!tickEvent.scheduled()); 2192623SN/A 2202623SN/A notIdleFraction++; 2212623SN/A tickEvent.schedule(curTick + cycles(delay)); 2222623SN/A _status = Running; 2232623SN/A} 2242623SN/A 2252623SN/A 2262623SN/Avoid 2272623SN/AAtomicSimpleCPU::suspendContext(int thread_num) 2282623SN/A{ 2292623SN/A assert(thread_num == 0); 2302623SN/A assert(cpuXC); 2312623SN/A 2322623SN/A assert(_status == Running); 2332626SN/A 2342626SN/A // tick event may not be scheduled if this gets called from inside 2352626SN/A // an instruction's execution, e.g. "quiesce" 2362626SN/A if (tickEvent.scheduled()) 2372626SN/A tickEvent.deschedule(); 2382623SN/A 2392623SN/A notIdleFraction--; 2402623SN/A _status = Idle; 2412623SN/A} 2422623SN/A 2432623SN/A 2442623SN/Atemplate <class T> 2452623SN/AFault 2462623SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2472623SN/A{ 2482623SN/A data_read_req->setVaddr(addr); 2492623SN/A data_read_req->setSize(sizeof(T)); 2502623SN/A data_read_req->setFlags(flags); 2512623SN/A data_read_req->setTime(curTick); 2522623SN/A 2532623SN/A if (traceData) { 2542623SN/A traceData->setAddr(addr); 2552623SN/A } 2562623SN/A 2572623SN/A // translate to physical address 2582623SN/A Fault fault = cpuXC->translateDataReadReq(data_read_req); 2592623SN/A 2602623SN/A // Now do the access. 2612623SN/A if (fault == NoFault) { 2622623SN/A data_read_pkt->reset(); 2632623SN/A data_read_pkt->addr = data_read_req->getPaddr(); 2642623SN/A data_read_pkt->size = sizeof(T); 2652623SN/A 2662630SN/A dcache_complete = dcachePort.sendAtomic(data_read_pkt); 2672623SN/A dcache_access = true; 2682623SN/A 2692623SN/A assert(data_read_pkt->result == Success); 2702623SN/A data = data_read_pkt->get<T>(); 2712623SN/A 2722623SN/A } 2732623SN/A 2742623SN/A // This will need a new way to tell if it has a dcache attached. 2752623SN/A if (data_read_req->getFlags() & UNCACHEABLE) 2762623SN/A recordEvent("Uncached Read"); 2772623SN/A 2782623SN/A return fault; 2792623SN/A} 2802623SN/A 2812623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 2822623SN/A 2832623SN/Atemplate 2842623SN/AFault 2852623SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 2862623SN/A 2872623SN/Atemplate 2882623SN/AFault 2892623SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 2902623SN/A 2912623SN/Atemplate 2922623SN/AFault 2932623SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 2942623SN/A 2952623SN/Atemplate 2962623SN/AFault 2972623SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 2982623SN/A 2992623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3002623SN/A 3012623SN/Atemplate<> 3022623SN/AFault 3032623SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 3042623SN/A{ 3052623SN/A return read(addr, *(uint64_t*)&data, flags); 3062623SN/A} 3072623SN/A 3082623SN/Atemplate<> 3092623SN/AFault 3102623SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3112623SN/A{ 3122623SN/A return read(addr, *(uint32_t*)&data, flags); 3132623SN/A} 3142623SN/A 3152623SN/A 3162623SN/Atemplate<> 3172623SN/AFault 3182623SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3192623SN/A{ 3202623SN/A return read(addr, (uint32_t&)data, flags); 3212623SN/A} 3222623SN/A 3232623SN/A 3242623SN/Atemplate <class T> 3252623SN/AFault 3262623SN/AAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 3272623SN/A{ 3282623SN/A data_write_req->setVaddr(addr); 3292623SN/A data_write_req->setTime(curTick); 3302623SN/A data_write_req->setSize(sizeof(T)); 3312623SN/A data_write_req->setFlags(flags); 3322623SN/A 3332623SN/A if (traceData) { 3342623SN/A traceData->setAddr(addr); 3352623SN/A } 3362623SN/A 3372623SN/A // translate to physical address 3382623SN/A Fault fault = cpuXC->translateDataWriteReq(data_write_req); 3392623SN/A 3402623SN/A // Now do the access. 3412623SN/A if (fault == NoFault) { 3422623SN/A data_write_pkt->reset(); 3432623SN/A data = htog(data); 3442623SN/A data_write_pkt->dataStatic(&data); 3452623SN/A data_write_pkt->addr = data_write_req->getPaddr(); 3462623SN/A data_write_pkt->size = sizeof(T); 3472623SN/A 3482630SN/A dcache_complete = dcachePort.sendAtomic(data_write_pkt); 3492623SN/A dcache_access = true; 3502623SN/A 3512623SN/A assert(data_write_pkt->result == Success); 3522631SN/A 3532631SN/A if (res && data_write_req->getFlags() & LOCKED) { 3542631SN/A *res = data_write_req->getScResult(); 3552631SN/A } 3562623SN/A } 3572623SN/A 3582623SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3592623SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3602623SN/A recordEvent("Uncached Write"); 3612623SN/A 3622623SN/A // If the write needs to have a fault on the access, consider calling 3632623SN/A // changeStatus() and changing it to "bad addr write" or something. 3642623SN/A return fault; 3652623SN/A} 3662623SN/A 3672623SN/A 3682623SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 3692623SN/Atemplate 3702623SN/AFault 3712623SN/AAtomicSimpleCPU::write(uint64_t data, Addr addr, 3722623SN/A unsigned flags, uint64_t *res); 3732623SN/A 3742623SN/Atemplate 3752623SN/AFault 3762623SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 3772623SN/A unsigned flags, uint64_t *res); 3782623SN/A 3792623SN/Atemplate 3802623SN/AFault 3812623SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 3822623SN/A unsigned flags, uint64_t *res); 3832623SN/A 3842623SN/Atemplate 3852623SN/AFault 3862623SN/AAtomicSimpleCPU::write(uint8_t data, Addr addr, 3872623SN/A unsigned flags, uint64_t *res); 3882623SN/A 3892623SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 3902623SN/A 3912623SN/Atemplate<> 3922623SN/AFault 3932623SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3942623SN/A{ 3952623SN/A return write(*(uint64_t*)&data, addr, flags, res); 3962623SN/A} 3972623SN/A 3982623SN/Atemplate<> 3992623SN/AFault 4002623SN/AAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 4012623SN/A{ 4022623SN/A return write(*(uint32_t*)&data, addr, flags, res); 4032623SN/A} 4042623SN/A 4052623SN/A 4062623SN/Atemplate<> 4072623SN/AFault 4082623SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4092623SN/A{ 4102623SN/A return write((uint32_t)data, addr, flags, res); 4112623SN/A} 4122623SN/A 4132623SN/A 4142623SN/Avoid 4152623SN/AAtomicSimpleCPU::tick() 4162623SN/A{ 4172623SN/A Tick latency = cycles(1); // instruction takes one cycle by default 4182623SN/A 4192623SN/A for (int i = 0; i < width; ++i) { 4202623SN/A numCycles++; 4212623SN/A 4222626SN/A checkForInterrupts(); 4232626SN/A 4242623SN/A ifetch_req->resetMin(); 4252623SN/A ifetch_pkt->reset(); 4262623SN/A Fault fault = setupFetchPacket(ifetch_pkt); 4272623SN/A 4282623SN/A if (fault == NoFault) { 4292630SN/A Tick icache_complete = icachePort.sendAtomic(ifetch_pkt); 4302623SN/A // ifetch_req is initialized to read the instruction directly 4312623SN/A // into the CPU object's inst field. 4322623SN/A 4332623SN/A dcache_access = false; // assume no dcache access 4342623SN/A preExecute(); 4352623SN/A fault = curStaticInst->execute(this, traceData); 4362623SN/A postExecute(); 4372623SN/A 4382623SN/A if (traceData) { 4392623SN/A traceData->finalize(); 4402623SN/A } 4412623SN/A 4422623SN/A if (simulate_stalls) { 4432623SN/A // This calculation assumes that the icache and dcache 4442623SN/A // access latencies are always a multiple of the CPU's 4452623SN/A // cycle time. If not, the next tick event may get 4462623SN/A // scheduled at a non-integer multiple of the CPU 4472623SN/A // cycle time. 4482623SN/A Tick icache_stall = icache_complete - curTick - cycles(1); 4492623SN/A Tick dcache_stall = 4502623SN/A dcache_access ? dcache_complete - curTick - cycles(1) : 0; 4512623SN/A latency += icache_stall + dcache_stall; 4522623SN/A } 4532623SN/A 4542623SN/A } 4552623SN/A 4562623SN/A advancePC(fault); 4572623SN/A } 4582623SN/A 4592626SN/A if (_status != Idle) 4602626SN/A tickEvent.schedule(curTick + latency); 4612623SN/A} 4622623SN/A 4632623SN/A 4642623SN/A//////////////////////////////////////////////////////////////////////// 4652623SN/A// 4662623SN/A// AtomicSimpleCPU Simulation Object 4672623SN/A// 4682623SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4692623SN/A 4702623SN/A Param<Counter> max_insts_any_thread; 4712623SN/A Param<Counter> max_insts_all_threads; 4722623SN/A Param<Counter> max_loads_any_thread; 4732623SN/A Param<Counter> max_loads_all_threads; 4742623SN/A SimObjectParam<MemObject *> mem; 4752623SN/A 4762623SN/A#if FULL_SYSTEM 4772623SN/A SimObjectParam<AlphaITB *> itb; 4782623SN/A SimObjectParam<AlphaDTB *> dtb; 4792623SN/A SimObjectParam<System *> system; 4802623SN/A Param<int> cpu_id; 4812623SN/A Param<Tick> profile; 4822623SN/A#else 4832623SN/A SimObjectParam<Process *> workload; 4842623SN/A#endif // FULL_SYSTEM 4852623SN/A 4862623SN/A Param<int> clock; 4872623SN/A 4882623SN/A Param<bool> defer_registration; 4892623SN/A Param<int> width; 4902623SN/A Param<bool> function_trace; 4912623SN/A Param<Tick> function_trace_start; 4922623SN/A Param<bool> simulate_stalls; 4932623SN/A 4942623SN/AEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4952623SN/A 4962623SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4972623SN/A 4982623SN/A INIT_PARAM(max_insts_any_thread, 4992623SN/A "terminate when any thread reaches this inst count"), 5002623SN/A INIT_PARAM(max_insts_all_threads, 5012623SN/A "terminate when all threads have reached this inst count"), 5022623SN/A INIT_PARAM(max_loads_any_thread, 5032623SN/A "terminate when any thread reaches this load count"), 5042623SN/A INIT_PARAM(max_loads_all_threads, 5052623SN/A "terminate when all threads have reached this load count"), 5062623SN/A INIT_PARAM(mem, "memory"), 5072623SN/A 5082623SN/A#if FULL_SYSTEM 5092623SN/A INIT_PARAM(itb, "Instruction TLB"), 5102623SN/A INIT_PARAM(dtb, "Data TLB"), 5112623SN/A INIT_PARAM(system, "system object"), 5122623SN/A INIT_PARAM(cpu_id, "processor ID"), 5132623SN/A INIT_PARAM(profile, ""), 5142623SN/A#else 5152623SN/A INIT_PARAM(workload, "processes to run"), 5162623SN/A#endif // FULL_SYSTEM 5172623SN/A 5182623SN/A INIT_PARAM(clock, "clock speed"), 5192623SN/A INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 5202623SN/A INIT_PARAM(width, "cpu width"), 5212623SN/A INIT_PARAM(function_trace, "Enable function trace"), 5222623SN/A INIT_PARAM(function_trace_start, "Cycle to start function trace"), 5232623SN/A INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 5242623SN/A 5252623SN/AEND_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 5262623SN/A 5272623SN/A 5282623SN/ACREATE_SIM_OBJECT(AtomicSimpleCPU) 5292623SN/A{ 5302623SN/A AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 5312623SN/A params->name = getInstanceName(); 5322623SN/A params->numberOfThreads = 1; 5332623SN/A params->max_insts_any_thread = max_insts_any_thread; 5342623SN/A params->max_insts_all_threads = max_insts_all_threads; 5352623SN/A params->max_loads_any_thread = max_loads_any_thread; 5362623SN/A params->max_loads_all_threads = max_loads_all_threads; 5372623SN/A params->deferRegistration = defer_registration; 5382623SN/A params->clock = clock; 5392623SN/A params->functionTrace = function_trace; 5402623SN/A params->functionTraceStart = function_trace_start; 5412623SN/A params->width = width; 5422623SN/A params->simulate_stalls = simulate_stalls; 5432623SN/A params->mem = mem; 5442623SN/A 5452623SN/A#if FULL_SYSTEM 5462623SN/A params->itb = itb; 5472623SN/A params->dtb = dtb; 5482623SN/A params->system = system; 5492623SN/A params->cpu_id = cpu_id; 5502623SN/A params->profile = profile; 5512623SN/A#else 5522623SN/A params->process = workload; 5532623SN/A#endif 5542623SN/A 5552623SN/A AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 5562623SN/A return cpu; 5572623SN/A} 5582623SN/A 5592623SN/AREGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 5602623SN/A 561