atomic.cc revision 2623
17513SN/A/* 27513SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 37513SN/A * All rights reserved. 410036SN/A * 58835SN/A * Redistribution and use in source and binary forms, with or without 610036SN/A * modification, are permitted provided that the following conditions are 77935SN/A * met: redistributions of source code must retain the above copyright 87935SN/A * notice, this list of conditions and the following disclaimer; 97935SN/A * redistributions in binary form must reproduce the above copyright 107513SN/A * notice, this list of conditions and the following disclaimer in the 117513SN/A * documentation and/or other materials provided with the distribution; 127513SN/A * neither the name of the copyright holders nor the names of its 1310315SN/A * contributors may be used to endorse or promote products derived from 148835SN/A * this software without specific prior written permission. 159885SN/A * 169885SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711570SCurtis.Dunham@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810036SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911312Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208835SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218835SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238835SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410038SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259481SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269481SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278721SN/A */ 2811066Snilay@cs.wisc.edu 2911219Snilay@cs.wisc.edu#include "arch/utility.hh" 308721SN/A#include "cpu/exetrace.hh" 3111570SCurtis.Dunham@arm.com#include "cpu/simple/atomic.hh" 3211570SCurtis.Dunham@arm.com#include "mem/packet_impl.hh" 3311570SCurtis.Dunham@arm.com#include "sim/builder.hh" 3411570SCurtis.Dunham@arm.com 358835SN/Ausing namespace std; 368835SN/Ausing namespace TheISA; 3711440SCurtis.Dunham@arm.com 3811440SCurtis.Dunham@arm.comAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 397935SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 407935SN/A{ 417935SN/A} 427935SN/A 437935SN/A 447935SN/Avoid 457935SN/AAtomicSimpleCPU::TickEvent::process() 468893SN/A{ 477513SN/A cpu->tick(); 489885SN/A} 499885SN/A 509885SN/Aconst char * 5110315SN/AAtomicSimpleCPU::TickEvent::description() 5210036SN/A{ 5310315SN/A return "AtomicSimpleCPU tick event"; 549885SN/A} 559885SN/A 567513SN/A 577513SN/Avoid 5810038SN/AAtomicSimpleCPU::init() 5910315SN/A{ 607513SN/A //Create Memory Ports (conect them up) 619885SN/A Port *mem_dport = mem->getPort(""); 627513SN/A dcachePort.setPeer(mem_dport); 6311570SCurtis.Dunham@arm.com mem_dport->setPeer(&dcachePort); 647513SN/A 658835SN/A Port *mem_iport = mem->getPort(""); 667513SN/A icachePort.setPeer(mem_iport); 6710038SN/A mem_iport->setPeer(&icachePort); 687513SN/A 6910036SN/A BaseCPU::init(); 707513SN/A#if FULL_SYSTEM 717513SN/A for (int i = 0; i < execContexts.size(); ++i) { 728835SN/A ExecContext *xc = execContexts[i]; 739481SN/A 7410038SN/A // initialize CPU, including PC 757513SN/A TheISA::initCPU(xc, xc->readCpuId()); 767513SN/A } 777513SN/A#endif 787513SN/A} 797513SN/A 807513SN/Abool 8111570SCurtis.Dunham@arm.comAtomicSimpleCPU::CpuPort::recvTiming(Packet &pkt) 8211570SCurtis.Dunham@arm.com{ 8311570SCurtis.Dunham@arm.com panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 8411570SCurtis.Dunham@arm.com return true; 858835SN/A} 867513SN/A 879885SN/ATick 8810315SN/AAtomicSimpleCPU::CpuPort::recvAtomic(Packet &pkt) 899481SN/A{ 9011960Sgabeblack@google.com panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 917513SN/A return curTick; 927513SN/A} 937513SN/A 947513SN/Avoid 957513SN/AAtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt) 967513SN/A{ 977513SN/A panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 9811066Snilay@cs.wisc.edu} 999885SN/A 10011960Sgabeblack@google.comvoid 1017513SN/AAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1029885SN/A{ 10311219Snilay@cs.wisc.edu panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 10411960Sgabeblack@google.com} 10511570SCurtis.Dunham@arm.com 10611066Snilay@cs.wisc.eduPacket * 10710036SN/AAtomicSimpleCPU::CpuPort::recvRetry() 10811066Snilay@cs.wisc.edu{ 1097513SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1109481SN/A return NULL; 11111570SCurtis.Dunham@arm.com} 11211570SCurtis.Dunham@arm.com 11311570SCurtis.Dunham@arm.com 11411570SCurtis.Dunham@arm.comAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 1157513SN/A : BaseSimpleCPU(p), tickEvent(this), 1168835SN/A width(p->width), simulate_stalls(p->simulate_stalls), 1179481SN/A icachePort(this), dcachePort(this) 11810036SN/A{ 1197513SN/A _status = Idle; 1208835SN/A 12111960Sgabeblack@google.com ifetch_req = new Request(true); 1229885SN/A ifetch_req->setAsid(0); 1239481SN/A // @todo fix me and get the real cpu iD!!! 1247513SN/A ifetch_req->setCpuNum(0); 12511219Snilay@cs.wisc.edu ifetch_req->setSize(sizeof(MachInst)); 1267513SN/A ifetch_pkt = new Packet; 1278893SN/A ifetch_pkt->cmd = Read; 1287513SN/A ifetch_pkt->dataStatic(&inst); 1299885SN/A ifetch_pkt->req = ifetch_req; 1309885SN/A ifetch_pkt->size = sizeof(MachInst); 1319885SN/A ifetch_pkt->dest = Packet::Broadcast; 1329885SN/A 1339885SN/A data_read_req = new Request(true); 13411960Sgabeblack@google.com // @todo fix me and get the real cpu iD!!! 13511570SCurtis.Dunham@arm.com data_read_req->setCpuNum(0); 13610036SN/A data_read_req->setAsid(0); 13711570SCurtis.Dunham@arm.com data_read_pkt = new Packet; 13811570SCurtis.Dunham@arm.com data_read_pkt->cmd = Read; 13911570SCurtis.Dunham@arm.com data_read_pkt->dataStatic(&dataReg); 14011570SCurtis.Dunham@arm.com data_read_pkt->req = data_read_req; 14110036SN/A data_read_pkt->dest = Packet::Broadcast; 1429885SN/A 14311960Sgabeblack@google.com data_write_req = new Request(true); 1449885SN/A // @todo fix me and get the real cpu iD!!! 14510038SN/A data_write_req->setCpuNum(0); 14610038SN/A data_write_req->setAsid(0); 14710038SN/A data_write_pkt = new Packet; 14810038SN/A data_write_pkt->cmd = Write; 14910038SN/A data_write_pkt->req = data_write_req; 15011066Snilay@cs.wisc.edu data_write_pkt->dest = Packet::Broadcast; 15110038SN/A} 15210038SN/A 15310038SN/A 15410038SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 15510038SN/A{ 15610038SN/A} 15710038SN/A 15810038SN/Avoid 15910038SN/AAtomicSimpleCPU::serialize(ostream &os) 16010038SN/A{ 16110038SN/A BaseSimpleCPU::serialize(os); 16210038SN/A SERIALIZE_ENUM(_status); 16310038SN/A nameOut(os, csprintf("%s.tickEvent", name())); 16411570SCurtis.Dunham@arm.com tickEvent.serialize(os); 16510038SN/A} 16610038SN/A 16710038SN/Avoid 16811570SCurtis.Dunham@arm.comAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 16911570SCurtis.Dunham@arm.com{ 17011570SCurtis.Dunham@arm.com BaseSimpleCPU::unserialize(cp, section); 17111570SCurtis.Dunham@arm.com UNSERIALIZE_ENUM(_status); 17210038SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 17310038SN/A} 1747513SN/A 1757513SN/Avoid 1768835SN/AAtomicSimpleCPU::switchOut(Sampler *s) 17710036SN/A{ 17810038SN/A sampler = s; 1797513SN/A if (status() == Running) { 1808835SN/A _status = SwitchedOut; 1818835SN/A 1828835SN/A tickEvent.squash(); 1838835SN/A } 1849885SN/A sampler->signalSwitched(); 18511570SCurtis.Dunham@arm.com} 18610036SN/A 18710038SN/A 1889265SN/Avoid 18911570SCurtis.Dunham@arm.comAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 19011570SCurtis.Dunham@arm.com{ 19111570SCurtis.Dunham@arm.com BaseCPU::takeOverFrom(oldCPU); 19211570SCurtis.Dunham@arm.com 1938835SN/A assert(!tickEvent.scheduled()); 1948893SN/A 1957513SN/A // if any of this CPU's ExecContexts are active, mark the CPU as 1967513SN/A // running and schedule its tick event. 19711066Snilay@cs.wisc.edu for (int i = 0; i < execContexts.size(); ++i) { 1989885SN/A ExecContext *xc = execContexts[i]; 19911960Sgabeblack@google.com if (xc->status() == ExecContext::Active && _status != Running) { 2007513SN/A _status = Running; 2019885SN/A tickEvent.schedule(curTick); 20211219Snilay@cs.wisc.edu break; 20311960Sgabeblack@google.com } 20411570SCurtis.Dunham@arm.com } 20511066Snilay@cs.wisc.edu} 20610036SN/A 20711066Snilay@cs.wisc.edu 2087513SN/Avoid 2099481SN/AAtomicSimpleCPU::activateContext(int thread_num, int delay) 21011570SCurtis.Dunham@arm.com{ 21111570SCurtis.Dunham@arm.com assert(thread_num == 0); 21211570SCurtis.Dunham@arm.com assert(cpuXC); 21311570SCurtis.Dunham@arm.com 2147513SN/A assert(_status == Idle); 2158835SN/A assert(!tickEvent.scheduled()); 2169481SN/A 21710036SN/A notIdleFraction++; 2187513SN/A tickEvent.schedule(curTick + cycles(delay)); 2198835SN/A _status = Running; 22011960Sgabeblack@google.com} 2219885SN/A 2229481SN/A 2237513SN/Avoid 22411219Snilay@cs.wisc.eduAtomicSimpleCPU::suspendContext(int thread_num) 2257513SN/A{ 2268893SN/A assert(thread_num == 0); 2277513SN/A assert(cpuXC); 2289885SN/A 2299885SN/A assert(_status == Running); 2309885SN/A assert(tickEvent.scheduled()); 2319885SN/A 2329885SN/A notIdleFraction--; 23311960Sgabeblack@google.com tickEvent.deschedule(); 23411570SCurtis.Dunham@arm.com _status = Idle; 23510036SN/A} 23611570SCurtis.Dunham@arm.com 23711570SCurtis.Dunham@arm.com 23811570SCurtis.Dunham@arm.comtemplate <class T> 23911570SCurtis.Dunham@arm.comFault 24010036SN/AAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 2419885SN/A{ 24211960Sgabeblack@google.com data_read_req->setVaddr(addr); 2439885SN/A data_read_req->setSize(sizeof(T)); 2448835SN/A data_read_req->setFlags(flags); 2458835SN/A data_read_req->setTime(curTick); 24610036SN/A 2478835SN/A if (traceData) { 2489481SN/A traceData->setAddr(addr); 2499481SN/A } 25011219Snilay@cs.wisc.edu 25110036SN/A // translate to physical address 2529481SN/A Fault fault = cpuXC->translateDataReadReq(data_read_req); 25310038SN/A 25410038SN/A // Now do the access. 25510038SN/A if (fault == NoFault) { 25610038SN/A data_read_pkt->reset(); 25710038SN/A data_read_pkt->addr = data_read_req->getPaddr(); 25810038SN/A data_read_pkt->size = sizeof(T); 25910038SN/A 26010038SN/A dcache_complete = dcachePort.sendAtomic(*data_read_pkt); 2619481SN/A dcache_access = true; 2629481SN/A 2639481SN/A assert(data_read_pkt->result == Success); 2649481SN/A data = data_read_pkt->get<T>(); 2659481SN/A 2669481SN/A } 26710038SN/A 2689481SN/A // This will need a new way to tell if it has a dcache attached. 2699481SN/A if (data_read_req->getFlags() & UNCACHEABLE) 27010038SN/A recordEvent("Uncached Read"); 27110038SN/A 27211066Snilay@cs.wisc.edu return fault; 27310038SN/A} 27410038SN/A 27510038SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 27610038SN/A 27710038SN/Atemplate 27810038SN/AFault 27910038SN/AAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 28011066Snilay@cs.wisc.edu 28110038SN/Atemplate 28210038SN/AFault 28310038SN/AAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 28410038SN/A 28510038SN/Atemplate 28610038SN/AFault 28710038SN/AAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 28810038SN/A 28910038SN/Atemplate 29010038SN/AFault 29110038SN/AAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 29210038SN/A 29310038SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 29411570SCurtis.Dunham@arm.com 29510038SN/Atemplate<> 29610038SN/AFault 29710038SN/AAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 29811570SCurtis.Dunham@arm.com{ 29911570SCurtis.Dunham@arm.com return read(addr, *(uint64_t*)&data, flags); 30011570SCurtis.Dunham@arm.com} 30111570SCurtis.Dunham@arm.com 30210038SN/Atemplate<> 3039481SN/AFault 3047513SN/AAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 3057513SN/A{ 3068835SN/A return read(addr, *(uint32_t*)&data, flags); 30710036SN/A} 30810038SN/A 3097513SN/A 3108835SN/Atemplate<> 3118835SN/AFault 3128835SN/AAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 3138835SN/A{ 3149885SN/A return read(addr, (uint32_t&)data, flags); 31511570SCurtis.Dunham@arm.com} 31610036SN/A 31710038SN/A 3189265SN/Atemplate <class T> 31911570SCurtis.Dunham@arm.comFault 32011570SCurtis.Dunham@arm.comAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 32111570SCurtis.Dunham@arm.com{ 32211570SCurtis.Dunham@arm.com data_write_req->setVaddr(addr); 3238835SN/A data_write_req->setTime(curTick); 3248893SN/A data_write_req->setSize(sizeof(T)); 3257513SN/A data_write_req->setFlags(flags); 3267513SN/A 32711066Snilay@cs.wisc.edu if (traceData) { 3289885SN/A traceData->setAddr(addr); 32911960Sgabeblack@google.com } 3309481SN/A 3319885SN/A // translate to physical address 33211219Snilay@cs.wisc.edu Fault fault = cpuXC->translateDataWriteReq(data_write_req); 33311960Sgabeblack@google.com 33411570SCurtis.Dunham@arm.com // Now do the access. 33511066Snilay@cs.wisc.edu if (fault == NoFault) { 33610036SN/A data_write_pkt->reset(); 33711066Snilay@cs.wisc.edu data = htog(data); 3387513SN/A data_write_pkt->dataStatic(&data); 3399481SN/A data_write_pkt->addr = data_write_req->getPaddr(); 34011570SCurtis.Dunham@arm.com data_write_pkt->size = sizeof(T); 34111570SCurtis.Dunham@arm.com 34211570SCurtis.Dunham@arm.com dcache_complete = dcachePort.sendAtomic(*data_write_pkt); 34311570SCurtis.Dunham@arm.com dcache_access = true; 3447513SN/A 3458835SN/A assert(data_write_pkt->result == Success); 3469481SN/A } 34710036SN/A 3487513SN/A if (res && (fault == NoFault)) 3498835SN/A *res = data_write_pkt->result; 35011960Sgabeblack@google.com 3519885SN/A // This will need a new way to tell if it's hooked up to a cache or not. 3529481SN/A if (data_write_req->getFlags() & UNCACHEABLE) 3537513SN/A recordEvent("Uncached Write"); 35411219Snilay@cs.wisc.edu 3558893SN/A // @todo this is a hack and only works on uniprocessor systems 3568893SN/A // some one else can implement LL/SC. 3577513SN/A if (data_write_req->getFlags() & LOCKED) 3589885SN/A *res = 1; 3599885SN/A 3609885SN/A // If the write needs to have a fault on the access, consider calling 3619885SN/A // changeStatus() and changing it to "bad addr write" or something. 3629885SN/A return fault; 36311960Sgabeblack@google.com} 36411570SCurtis.Dunham@arm.com 36510036SN/A 36611570SCurtis.Dunham@arm.com#ifndef DOXYGEN_SHOULD_SKIP_THIS 36711570SCurtis.Dunham@arm.comtemplate 36811570SCurtis.Dunham@arm.comFault 36911570SCurtis.Dunham@arm.comAtomicSimpleCPU::write(uint64_t data, Addr addr, 37010036SN/A unsigned flags, uint64_t *res); 3719885SN/A 37211960Sgabeblack@google.comtemplate 3739885SN/AFault 3747513SN/AAtomicSimpleCPU::write(uint32_t data, Addr addr, 37510451SN/A unsigned flags, uint64_t *res); 37611219Snilay@cs.wisc.edu 3779885SN/Atemplate 37811570SCurtis.Dunham@arm.comFault 37910036SN/AAtomicSimpleCPU::write(uint16_t data, Addr addr, 38011066Snilay@cs.wisc.edu unsigned flags, uint64_t *res); 38111066Snilay@cs.wisc.edu 38211570SCurtis.Dunham@arm.comtemplate 38311570SCurtis.Dunham@arm.comFault 38411570SCurtis.Dunham@arm.comAtomicSimpleCPU::write(uint8_t data, Addr addr, 38511440SCurtis.Dunham@arm.com unsigned flags, uint64_t *res); 38611570SCurtis.Dunham@arm.com 38711066Snilay@cs.wisc.edu#endif //DOXYGEN_SHOULD_SKIP_THIS 38811219Snilay@cs.wisc.edu 38911066Snilay@cs.wisc.edutemplate<> 3909885SN/AFault 3917524SN/AAtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 3929481SN/A{ 3938893SN/A return write(*(uint64_t*)&data, addr, flags, res); 39411066Snilay@cs.wisc.edu} 3957513SN/A 39611219Snilay@cs.wisc.edutemplate<> 39711219Snilay@cs.wisc.eduFault 39811219Snilay@cs.wisc.eduAtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 39911219Snilay@cs.wisc.edu{ 40011219Snilay@cs.wisc.edu return write(*(uint32_t*)&data, addr, flags, res); 40111219Snilay@cs.wisc.edu} 40211219Snilay@cs.wisc.edu 4037513SN/A 4047513SN/Atemplate<> 40510036SN/AFault 4067513SN/AAtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 4077513SN/A{ 40811960Sgabeblack@google.com return write((uint32_t)data, addr, flags, res); 4097513SN/A} 41011066Snilay@cs.wisc.edu 41111066Snilay@cs.wisc.edu 4127513SN/Avoid 4137513SN/AAtomicSimpleCPU::tick() 4147513SN/A{ 4157513SN/A Tick latency = cycles(1); // instruction takes one cycle by default 41610036SN/A 41711960Sgabeblack@google.com for (int i = 0; i < width; ++i) { 4187513SN/A numCycles++; 4197513SN/A 42011066Snilay@cs.wisc.edu ifetch_req->resetMin(); 42111960Sgabeblack@google.com ifetch_pkt->reset(); 4227513SN/A Fault fault = setupFetchPacket(ifetch_pkt); 42311960Sgabeblack@google.com 4247513SN/A if (fault == NoFault) { 42511960Sgabeblack@google.com Tick icache_complete = icachePort.sendAtomic(*ifetch_pkt); 4267513SN/A // ifetch_req is initialized to read the instruction directly 4277513SN/A // into the CPU object's inst field. 4287513SN/A 42910451SN/A dcache_access = false; // assume no dcache access 4307513SN/A preExecute(); 4319885SN/A fault = curStaticInst->execute(this, traceData); 4329885SN/A postExecute(); 4339885SN/A 43410315SN/A if (traceData) { 43510036SN/A traceData->finalize(); 43610315SN/A } 4379885SN/A 4389885SN/A if (simulate_stalls) { 43910315SN/A // This calculation assumes that the icache and dcache 44010315SN/A // access latencies are always a multiple of the CPU's 44110315SN/A // cycle time. If not, the next tick event may get 44210315SN/A // scheduled at a non-integer multiple of the CPU 44310315SN/A // cycle time. 44410315SN/A Tick icache_stall = icache_complete - curTick - cycles(1); 44510315SN/A Tick dcache_stall = 44610315SN/A dcache_access ? dcache_complete - curTick - cycles(1) : 0; 4477513SN/A latency += icache_stall + dcache_stall; 44810451SN/A } 44911960Sgabeblack@google.com 4509885SN/A } 45111570SCurtis.Dunham@arm.com 45210036SN/A advancePC(fault); 45311066Snilay@cs.wisc.edu } 45411066Snilay@cs.wisc.edu 45511570SCurtis.Dunham@arm.com tickEvent.schedule(curTick + latency); 45611570SCurtis.Dunham@arm.com} 45711570SCurtis.Dunham@arm.com 45811440SCurtis.Dunham@arm.com 45911570SCurtis.Dunham@arm.com//////////////////////////////////////////////////////////////////////// 46011066Snilay@cs.wisc.edu// 46111960Sgabeblack@google.com// AtomicSimpleCPU Simulation Object 46211066Snilay@cs.wisc.edu// 4639885SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 4647524SN/A 46511066Snilay@cs.wisc.edu Param<Counter> max_insts_any_thread; 4669265SN/A Param<Counter> max_insts_all_threads; 4678893SN/A Param<Counter> max_loads_any_thread; 4687513SN/A Param<Counter> max_loads_all_threads; 46911960Sgabeblack@google.com SimObjectParam<MemObject *> mem; 47011960Sgabeblack@google.com 47111960Sgabeblack@google.com#if FULL_SYSTEM 47211960Sgabeblack@google.com SimObjectParam<AlphaITB *> itb; 47311960Sgabeblack@google.com SimObjectParam<AlphaDTB *> dtb; 47411960Sgabeblack@google.com SimObjectParam<System *> system; 47511960Sgabeblack@google.com Param<int> cpu_id; 4767513SN/A Param<Tick> profile; 4778983SN/A#else 4789265SN/A SimObjectParam<Process *> workload; 4799885SN/A#endif // FULL_SYSTEM 4809885SN/A 48111570SCurtis.Dunham@arm.com Param<int> clock; 48210036SN/A 4838983SN/A Param<bool> defer_registration; 48411960Sgabeblack@google.com Param<int> width; 4857513SN/A Param<bool> function_trace; 4867513SN/A Param<Tick> function_trace_start; 4877513SN/A Param<bool> simulate_stalls; 48811570SCurtis.Dunham@arm.com 48911570SCurtis.Dunham@arm.comEND_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 49011570SCurtis.Dunham@arm.com 49111570SCurtis.Dunham@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 49211960Sgabeblack@google.com 4938893SN/A INIT_PARAM(max_insts_any_thread, 4947513SN/A "terminate when any thread reaches this inst count"), 4959885SN/A INIT_PARAM(max_insts_all_threads, 4969885SN/A "terminate when all threads have reached this inst count"), 49710036SN/A INIT_PARAM(max_loads_any_thread, 4989885SN/A "terminate when any thread reaches this load count"), 4999885SN/A INIT_PARAM(max_loads_all_threads, 500 "terminate when all threads have reached this load count"), 501 INIT_PARAM(mem, "memory"), 502 503#if FULL_SYSTEM 504 INIT_PARAM(itb, "Instruction TLB"), 505 INIT_PARAM(dtb, "Data TLB"), 506 INIT_PARAM(system, "system object"), 507 INIT_PARAM(cpu_id, "processor ID"), 508 INIT_PARAM(profile, ""), 509#else 510 INIT_PARAM(workload, "processes to run"), 511#endif // FULL_SYSTEM 512 513 INIT_PARAM(clock, "clock speed"), 514 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 515 INIT_PARAM(width, "cpu width"), 516 INIT_PARAM(function_trace, "Enable function trace"), 517 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 518 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 519 520END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 521 522 523CREATE_SIM_OBJECT(AtomicSimpleCPU) 524{ 525 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 526 params->name = getInstanceName(); 527 params->numberOfThreads = 1; 528 params->max_insts_any_thread = max_insts_any_thread; 529 params->max_insts_all_threads = max_insts_all_threads; 530 params->max_loads_any_thread = max_loads_any_thread; 531 params->max_loads_all_threads = max_loads_all_threads; 532 params->deferRegistration = defer_registration; 533 params->clock = clock; 534 params->functionTrace = function_trace; 535 params->functionTraceStart = function_trace_start; 536 params->width = width; 537 params->simulate_stalls = simulate_stalls; 538 params->mem = mem; 539 540#if FULL_SYSTEM 541 params->itb = itb; 542 params->dtb = dtb; 543 params->system = system; 544 params->cpu_id = cpu_id; 545 params->profile = profile; 546#else 547 params->process = workload; 548#endif 549 550 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 551 return cpu; 552} 553 554REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 555 556