atomic.cc revision 12749
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 312276Sanouk.vanlaer@arm.com * Copyright (c) 2012-2013,2015,2017 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/atomic.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 499647Sdam.sunwoo@arm.com#include "base/output.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 6011793Sbrandon.potter@amd.com#include "sim/full_system.hh" 612901Ssaidi@eecs.umich.edu#include "sim/system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/Avoid 672623SN/AAtomicSimpleCPU::init() 682623SN/A{ 6911147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 708921Sandreas.hansson@arm.com 7111148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 7212749Sgiacomo.travaglini@arm.com ifetch_req->setContext(cid); 7312749Sgiacomo.travaglini@arm.com data_read_req->setContext(cid); 7412749Sgiacomo.travaglini@arm.com data_write_req->setContext(cid); 752623SN/A} 762623SN/A 775529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 7812127Sspwilson2@wisc.edu : BaseSimpleCPU(p), 7912127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 8012127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 8112127Sspwilson2@wisc.edu width(p->width), locked(false), 825487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 835487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 849095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 859095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 8610537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 8710537Sandreas.hansson@arm.com ppCommit(nullptr) 882623SN/A{ 892623SN/A _status = Idle; 9012749Sgiacomo.travaglini@arm.com ifetch_req = std::make_shared<Request>(); 9112749Sgiacomo.travaglini@arm.com data_read_req = std::make_shared<Request>(); 9212749Sgiacomo.travaglini@arm.com data_write_req = std::make_shared<Request>(); 932623SN/A} 942623SN/A 952623SN/A 962623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 972623SN/A{ 986775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 996775SBrad.Beckmann@amd.com deschedule(tickEvent); 1006775SBrad.Beckmann@amd.com } 1012623SN/A} 1022623SN/A 10310913Sandreas.sandberg@arm.comDrainState 10410913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1052623SN/A{ 10612276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 10712276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 10812276Sanouk.vanlaer@arm.com 1099448SAndreas.Sandberg@ARM.com if (switchedOut()) 11010913Sandreas.sandberg@arm.com return DrainState::Drained; 1112623SN/A 1129443SAndreas.Sandberg@ARM.com if (!isDrained()) { 11311147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 11410913Sandreas.sandberg@arm.com return DrainState::Draining; 1159443SAndreas.Sandberg@ARM.com } else { 1169443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1179443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1182915Sktlim@umich.edu 11911147Smitch.hayenga@arm.com activeThreads.clear(); 1209443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 12110913Sandreas.sandberg@arm.com return DrainState::Drained; 1229443SAndreas.Sandberg@ARM.com } 1239342SAndreas.Sandberg@arm.com} 1249342SAndreas.Sandberg@arm.com 1252915Sktlim@umich.eduvoid 12611148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 12711148Smitch.hayenga@arm.com{ 12811148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 12911148Smitch.hayenga@arm.com pkt->cmdString()); 13011148Smitch.hayenga@arm.com 13111148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 13211148Smitch.hayenga@arm.com if (tid != sender) { 13311321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 13411151Smitch.hayenga@arm.com wakeup(tid); 13511148Smitch.hayenga@arm.com } 13611148Smitch.hayenga@arm.com 13711148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 13811148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 13911148Smitch.hayenga@arm.com } 14011148Smitch.hayenga@arm.com } 14111148Smitch.hayenga@arm.com} 14211148Smitch.hayenga@arm.com 14311148Smitch.hayenga@arm.comvoid 1449342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1452915Sktlim@umich.edu{ 1469448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1479448SAndreas.Sandberg@ARM.com if (switchedOut()) 1485220Ssaidi@eecs.umich.edu return; 1495220Ssaidi@eecs.umich.edu 1504940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1519523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1523324Shsul@eecs.umich.edu 1539448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1549448SAndreas.Sandberg@ARM.com 15511147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 15611147Smitch.hayenga@arm.com 15711147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15811147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 15911147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 16011147Smitch.hayenga@arm.com activeThreads.push_back(tid); 16111147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 16211147Smitch.hayenga@arm.com 16311147Smitch.hayenga@arm.com // Tick if any threads active 16411147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 16511147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 16611147Smitch.hayenga@arm.com } 16711147Smitch.hayenga@arm.com } else { 16811147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 16911147Smitch.hayenga@arm.com } 1709448SAndreas.Sandberg@ARM.com } 17112276Sanouk.vanlaer@arm.com 17212276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 17312276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 1742623SN/A} 1752623SN/A 1769443SAndreas.Sandberg@ARM.combool 1779443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1789443SAndreas.Sandberg@ARM.com{ 17910913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1809443SAndreas.Sandberg@ARM.com return false; 1819443SAndreas.Sandberg@ARM.com 18211147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1839443SAndreas.Sandberg@ARM.com if (!isDrained()) 1849443SAndreas.Sandberg@ARM.com return false; 1859443SAndreas.Sandberg@ARM.com 1869443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 18710913Sandreas.sandberg@arm.com signalDrainDone(); 1889443SAndreas.Sandberg@ARM.com 1899443SAndreas.Sandberg@ARM.com return true; 1909443SAndreas.Sandberg@ARM.com} 1919443SAndreas.Sandberg@ARM.com 1929443SAndreas.Sandberg@ARM.com 1932623SN/Avoid 1942798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1952623SN/A{ 1969429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1979429SAndreas.Sandberg@ARM.com 1989443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1999342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 2009443SAndreas.Sandberg@ARM.com assert(isDrained()); 2012623SN/A} 2022623SN/A 2032623SN/A 2042623SN/Avoid 2052623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2062623SN/A{ 2079429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2082623SN/A 2099443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2102623SN/A assert(!tickEvent.scheduled()); 2112623SN/A} 2122623SN/A 2139523SAndreas.Sandberg@ARM.comvoid 2149523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2159523SAndreas.Sandberg@ARM.com{ 2169524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2179523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2189523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2199523SAndreas.Sandberg@ARM.com } 2209523SAndreas.Sandberg@ARM.com} 2212623SN/A 2222623SN/Avoid 22310407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2242623SN/A{ 22510407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2264940Snate@binkert.org 22711147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2282623SN/A 22911147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 23011147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 23111147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 23210464SAndreas.Sandberg@ARM.com numCycles += delta; 2333686Sktlim@umich.edu 23411147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 23511147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 23611147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 23711147Smitch.hayenga@arm.com } 2389342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 23911147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 24011147Smitch.hayenga@arm.com == activeThreads.end()) { 24111147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 24211147Smitch.hayenga@arm.com } 24311526Sdavid.guillen@arm.com 24411526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2452623SN/A} 2462623SN/A 2472623SN/A 2482623SN/Avoid 2498737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2502623SN/A{ 2514940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2524940Snate@binkert.org 25311147Smitch.hayenga@arm.com assert(thread_num < numThreads); 25411147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2552623SN/A 2566043Sgblack@eecs.umich.edu if (_status == Idle) 2576043Sgblack@eecs.umich.edu return; 2586043Sgblack@eecs.umich.edu 2599342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2602626SN/A 26111147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2622623SN/A 26311147Smitch.hayenga@arm.com if (activeThreads.empty()) { 26411147Smitch.hayenga@arm.com _status = Idle; 26511147Smitch.hayenga@arm.com 26611147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 26711147Smitch.hayenga@arm.com deschedule(tickEvent); 26811147Smitch.hayenga@arm.com } 26911147Smitch.hayenga@arm.com } 27011147Smitch.hayenga@arm.com 27111526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2722623SN/A} 2732623SN/A 2742623SN/A 27510030SAli.Saidi@ARM.comTick 27610030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27710030SAli.Saidi@ARM.com{ 27810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27910030SAli.Saidi@ARM.com pkt->cmdString()); 28010030SAli.Saidi@ARM.com 28110529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 28210529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 28311148Smitch.hayenga@arm.com 28411148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 28511148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 28611151Smitch.hayenga@arm.com cpu->wakeup(tid); 28711148Smitch.hayenga@arm.com } 28810529Smorr@cs.wisc.edu } 28910529Smorr@cs.wisc.edu 29010030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29111356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 29211356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 29311356Skrinat01@arm.com // the processor accordingly 29411356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 29510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 29610030SAli.Saidi@ARM.com pkt->getAddr()); 29711147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 29811147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 29911147Smitch.hayenga@arm.com } 30010030SAli.Saidi@ARM.com } 30110030SAli.Saidi@ARM.com 30210030SAli.Saidi@ARM.com return 0; 30310030SAli.Saidi@ARM.com} 30410030SAli.Saidi@ARM.com 30510030SAli.Saidi@ARM.comvoid 30610030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 30710030SAli.Saidi@ARM.com{ 30810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 30910030SAli.Saidi@ARM.com pkt->cmdString()); 31010030SAli.Saidi@ARM.com 31110529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 31210529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 31311148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 31411321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 31511151Smitch.hayenga@arm.com cpu->wakeup(tid); 31611148Smitch.hayenga@arm.com } 31710529Smorr@cs.wisc.edu } 31810529Smorr@cs.wisc.edu 31910030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 32010030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 32110030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 32210030SAli.Saidi@ARM.com pkt->getAddr()); 32311147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 32411147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 32511147Smitch.hayenga@arm.com } 32610030SAli.Saidi@ARM.com } 32710030SAli.Saidi@ARM.com} 32810030SAli.Saidi@ARM.com 3292623SN/AFault 33011608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 33111608Snikos.nikoleris@arm.com Request::Flags flags) 3322623SN/A{ 33311147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 33411147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 33511147Smitch.hayenga@arm.com 3363169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 33712749Sgiacomo.travaglini@arm.com const RequestPtr &req = data_read_req; 3382623SN/A 33910665SAli.Saidi@ARM.com if (traceData) 34010665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3412623SN/A 3424999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3437520Sgblack@eecs.umich.edu int fullSize = size; 3442623SN/A 3454999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3464999Sgblack@eecs.umich.edu //across a cache line boundary. 3479814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3484999Sgblack@eecs.umich.edu 3497520Sgblack@eecs.umich.edu if (secondAddr > addr) 3507520Sgblack@eecs.umich.edu size = secondAddr - addr; 3514999Sgblack@eecs.umich.edu 3524999Sgblack@eecs.umich.edu dcache_latency = 0; 3534999Sgblack@eecs.umich.edu 35410024Sdam.sunwoo@arm.com req->taskId(taskId()); 3557520Sgblack@eecs.umich.edu while (1) { 3568832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3574999Sgblack@eecs.umich.edu 3584999Sgblack@eecs.umich.edu // translate to physical address 35911147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 36011147Smitch.hayenga@arm.com BaseTLB::Read); 3614999Sgblack@eecs.umich.edu 3624999Sgblack@eecs.umich.edu // Now do the access. 3636623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 36410739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3657520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3664999Sgblack@eecs.umich.edu 3678105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3684999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3694999Sgblack@eecs.umich.edu else { 3708931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3718931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3724999Sgblack@eecs.umich.edu else 3734999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3744999Sgblack@eecs.umich.edu } 3754999Sgblack@eecs.umich.edu dcache_access = true; 3765012Sgblack@eecs.umich.edu 3774999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3784999Sgblack@eecs.umich.edu 3796102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3804999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3814999Sgblack@eecs.umich.edu } 3824968Sacolyte@umich.edu } 3834986Ssaidi@eecs.umich.edu 3844999Sgblack@eecs.umich.edu //If there's a fault, return it 3856739Sgblack@eecs.umich.edu if (fault != NoFault) { 3866739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3876739Sgblack@eecs.umich.edu return NoFault; 3886739Sgblack@eecs.umich.edu } else { 3896739Sgblack@eecs.umich.edu return fault; 3906739Sgblack@eecs.umich.edu } 3916739Sgblack@eecs.umich.edu } 3926739Sgblack@eecs.umich.edu 3934999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3944999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3954999Sgblack@eecs.umich.edu { 39610760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3976078Sgblack@eecs.umich.edu assert(!locked); 3986078Sgblack@eecs.umich.edu locked = true; 3996078Sgblack@eecs.umich.edu } 40011147Smitch.hayenga@arm.com 4014999Sgblack@eecs.umich.edu return fault; 4024968Sacolyte@umich.edu } 4033170Sstever@eecs.umich.edu 4044999Sgblack@eecs.umich.edu /* 4054999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4064999Sgblack@eecs.umich.edu */ 4074999Sgblack@eecs.umich.edu 4084999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4097520Sgblack@eecs.umich.edu data += size; 4104999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4117520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4124999Sgblack@eecs.umich.edu //And access the right address. 4134999Sgblack@eecs.umich.edu addr = secondAddr; 4142623SN/A } 4152623SN/A} 4162623SN/A 41711303Ssteve.reinhardt@amd.comFault 41811608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 41911608Snikos.nikoleris@arm.com Request::Flags flags) 42011303Ssteve.reinhardt@amd.com{ 42111303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 42211303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 42311303Ssteve.reinhardt@amd.com} 4247520Sgblack@eecs.umich.edu 4252623SN/AFault 42611608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 42711608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4282623SN/A{ 42911147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 43011147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 43110031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 43210031SAli.Saidi@ARM.com 43310031SAli.Saidi@ARM.com if (data == NULL) { 43410031SAli.Saidi@ARM.com assert(size <= 64); 43512355Snikos.nikoleris@arm.com assert(flags & Request::STORE_NO_DATA); 43610031SAli.Saidi@ARM.com // This must be a cache block cleaning request 43710031SAli.Saidi@ARM.com data = zero_array; 43810031SAli.Saidi@ARM.com } 43910031SAli.Saidi@ARM.com 4403169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 44112749Sgiacomo.travaglini@arm.com const RequestPtr &req = data_write_req; 4422623SN/A 44310665SAli.Saidi@ARM.com if (traceData) 44410665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4452623SN/A 4464999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4477520Sgblack@eecs.umich.edu int fullSize = size; 4482623SN/A 4494999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4504999Sgblack@eecs.umich.edu //across a cache line boundary. 4519814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4524999Sgblack@eecs.umich.edu 45311321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4547520Sgblack@eecs.umich.edu size = secondAddr - addr; 4554999Sgblack@eecs.umich.edu 4564999Sgblack@eecs.umich.edu dcache_latency = 0; 4574999Sgblack@eecs.umich.edu 45810024Sdam.sunwoo@arm.com req->taskId(taskId()); 45911321Ssteve.reinhardt@amd.com while (1) { 4608832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4614999Sgblack@eecs.umich.edu 4624999Sgblack@eecs.umich.edu // translate to physical address 46311147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4644999Sgblack@eecs.umich.edu 4654999Sgblack@eecs.umich.edu // Now do the access. 4664999Sgblack@eecs.umich.edu if (fault == NoFault) { 4674999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4684999Sgblack@eecs.umich.edu 4696102Sgblack@eecs.umich.edu if (req->isLLSC()) { 47010030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4714999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4724999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4734999Sgblack@eecs.umich.edu assert(res); 4744999Sgblack@eecs.umich.edu req->setExtraData(*res); 4754999Sgblack@eecs.umich.edu } 4764999Sgblack@eecs.umich.edu } 4774999Sgblack@eecs.umich.edu 4786623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 47912355Snikos.nikoleris@arm.com Packet pkt(req, Packet::makeWriteCmd(req)); 4807520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4814999Sgblack@eecs.umich.edu 4828105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4834999Sgblack@eecs.umich.edu dcache_latency += 4844999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4854999Sgblack@eecs.umich.edu } else { 4868931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4878931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4884999Sgblack@eecs.umich.edu else 4894999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 49011148Smitch.hayenga@arm.com 49111148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 49211148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 4934999Sgblack@eecs.umich.edu } 4944999Sgblack@eecs.umich.edu dcache_access = true; 4954999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4964999Sgblack@eecs.umich.edu 4974999Sgblack@eecs.umich.edu if (req->isSwap()) { 4984999Sgblack@eecs.umich.edu assert(res); 49910563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 5004999Sgblack@eecs.umich.edu } 5014999Sgblack@eecs.umich.edu } 5024999Sgblack@eecs.umich.edu 5034999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5044999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5054878Sstever@eecs.umich.edu } 5064040Ssaidi@eecs.umich.edu } 5074040Ssaidi@eecs.umich.edu 5084999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5094999Sgblack@eecs.umich.edu //stop now. 5104999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5114999Sgblack@eecs.umich.edu { 51210760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5136078Sgblack@eecs.umich.edu assert(locked); 5146078Sgblack@eecs.umich.edu locked = false; 5156078Sgblack@eecs.umich.edu } 51611147Smitch.hayenga@arm.com 51711147Smitch.hayenga@arm.com 5186739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5196739Sgblack@eecs.umich.edu return NoFault; 5206739Sgblack@eecs.umich.edu } else { 5216739Sgblack@eecs.umich.edu return fault; 5226739Sgblack@eecs.umich.edu } 5233170Sstever@eecs.umich.edu } 5243170Sstever@eecs.umich.edu 5254999Sgblack@eecs.umich.edu /* 5264999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5274999Sgblack@eecs.umich.edu */ 5284999Sgblack@eecs.umich.edu 5294999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5307520Sgblack@eecs.umich.edu data += size; 5314999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5327520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5334999Sgblack@eecs.umich.edu //And access the right address. 5344999Sgblack@eecs.umich.edu addr = secondAddr; 5352623SN/A } 5362623SN/A} 5372623SN/A 5382623SN/A 5392623SN/Avoid 5402623SN/AAtomicSimpleCPU::tick() 5412623SN/A{ 5424940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5434940Snate@binkert.org 54411147Smitch.hayenga@arm.com // Change thread if multi-threaded 54511147Smitch.hayenga@arm.com swapActiveThread(); 54611147Smitch.hayenga@arm.com 54711147Smitch.hayenga@arm.com // Set memroy request ids to current thread 54811147Smitch.hayenga@arm.com if (numThreads > 1) { 54911148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 55011148Smitch.hayenga@arm.com 55112749Sgiacomo.travaglini@arm.com ifetch_req->setContext(cid); 55212749Sgiacomo.travaglini@arm.com data_read_req->setContext(cid); 55312749Sgiacomo.travaglini@arm.com data_write_req->setContext(cid); 55411147Smitch.hayenga@arm.com } 55511147Smitch.hayenga@arm.com 55611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 55711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 55811147Smitch.hayenga@arm.com 5595487Snate@binkert.org Tick latency = 0; 5602623SN/A 5616078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5622623SN/A numCycles++; 56312284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5642623SN/A 56510596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5663387Sgblack@eecs.umich.edu checkForInterrupts(); 56710596Sgabeblack@google.com checkPcEventQueue(); 56810596Sgabeblack@google.com } 5692626SN/A 5708143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5719443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5729443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5738143SAli.Saidi@ARM.com return; 5749443SAndreas.Sandberg@ARM.com } 5755348Ssaidi@eecs.umich.edu 5765669Sgblack@eecs.umich.edu Fault fault = NoFault; 5775669Sgblack@eecs.umich.edu 5787720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5797720Sgblack@eecs.umich.edu 5807720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5817720Sgblack@eecs.umich.edu !curMacroStaticInst; 5827720Sgblack@eecs.umich.edu if (needToFetch) { 58312749Sgiacomo.travaglini@arm.com ifetch_req->taskId(taskId()); 58412749Sgiacomo.travaglini@arm.com setupFetchRequest(ifetch_req); 58512749Sgiacomo.travaglini@arm.com fault = thread->itb->translateAtomic(ifetch_req, thread->getTC(), 5866023Snate@binkert.org BaseTLB::Execute); 5875894Sgblack@eecs.umich.edu } 5882623SN/A 5892623SN/A if (fault == NoFault) { 5904182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5914182Sgblack@eecs.umich.edu bool icache_access = false; 5924182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5932662Sstever@eecs.umich.edu 5947720Sgblack@eecs.umich.edu if (needToFetch) { 5959023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5965694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5975694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5985694Sgblack@eecs.umich.edu // this code should be uncommented. 5995669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 60011321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 6015669Sgblack@eecs.umich.edu //{ 6025669Sgblack@eecs.umich.edu icache_access = true; 60312749Sgiacomo.travaglini@arm.com Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq); 6045669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6052623SN/A 6068931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6078931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6085669Sgblack@eecs.umich.edu else 6095669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6104968Sacolyte@umich.edu 6115669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6124968Sacolyte@umich.edu 6135669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6145669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6155669Sgblack@eecs.umich.edu //} 6165669Sgblack@eecs.umich.edu } 6174182Sgblack@eecs.umich.edu 6182623SN/A preExecute(); 6193814Ssaidi@eecs.umich.edu 62011877Sbrandon.potter@amd.com Tick stall_ticks = 0; 6215001Sgblack@eecs.umich.edu if (curStaticInst) { 62211147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6234998Sgblack@eecs.umich.edu 6244998Sgblack@eecs.umich.edu // keep an instruction count 62510381Sdam.sunwoo@arm.com if (fault == NoFault) { 6264998Sgblack@eecs.umich.edu countInst(); 62710651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 62810381Sdam.sunwoo@arm.com } 6297655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6305001Sgblack@eecs.umich.edu delete traceData; 6315001Sgblack@eecs.umich.edu traceData = NULL; 6325001Sgblack@eecs.umich.edu } 6334998Sgblack@eecs.umich.edu 63412710Sgiacomo.travaglini@arm.com if (fault != NoFault && 63512710Sgiacomo.travaglini@arm.com dynamic_pointer_cast<SyscallRetryFault>(fault)) { 63611877Sbrandon.potter@amd.com // Retry execution of system calls after a delay. 63711877Sbrandon.potter@amd.com // Prevents immediate re-execution since conditions which 63811877Sbrandon.potter@amd.com // caused the retry are unlikely to change every tick. 63911877Sbrandon.potter@amd.com stall_ticks += clockEdge(syscallRetryLatency) - curTick(); 64011877Sbrandon.potter@amd.com } 64111877Sbrandon.potter@amd.com 6424182Sgblack@eecs.umich.edu postExecute(); 6434182Sgblack@eecs.umich.edu } 6442623SN/A 6453814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6464539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6474539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6483814Ssaidi@eecs.umich.edu instCnt++; 6493814Ssaidi@eecs.umich.edu 6505487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6515487Snate@binkert.org stall_ticks += icache_latency; 6525487Snate@binkert.org 6535487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6545487Snate@binkert.org stall_ticks += dcache_latency; 6555487Snate@binkert.org 6565487Snate@binkert.org if (stall_ticks) { 6579180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6589180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6599180Sandreas.hansson@arm.com // period 6609180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6619180Sandreas.hansson@arm.com clockPeriod(); 6622623SN/A } 6632623SN/A 6642623SN/A } 66511321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6664182Sgblack@eecs.umich.edu advancePC(fault); 6672623SN/A } 6682623SN/A 6699443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6709443SAndreas.Sandberg@ARM.com return; 6719443SAndreas.Sandberg@ARM.com 6725487Snate@binkert.org // instruction takes at least one cycle 6739179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6749179Sandreas.hansson@arm.com latency = clockPeriod(); 6755487Snate@binkert.org 6762626SN/A if (_status != Idle) 67711147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6782623SN/A} 6792623SN/A 68010381Sdam.sunwoo@arm.comvoid 68110381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 68210381Sdam.sunwoo@arm.com{ 68310464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 68410464SAndreas.Sandberg@ARM.com 68510381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68610381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68710381Sdam.sunwoo@arm.com} 6882623SN/A 6895315Sstever@gmail.comvoid 6905315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6915315Sstever@gmail.com{ 6925315Sstever@gmail.com dcachePort.printAddr(a); 6935315Sstever@gmail.com} 6945315Sstever@gmail.com 6952623SN/A//////////////////////////////////////////////////////////////////////// 6962623SN/A// 6972623SN/A// AtomicSimpleCPU Simulation Object 6982623SN/A// 6994762Snate@binkert.orgAtomicSimpleCPU * 7004762Snate@binkert.orgAtomicSimpleCPUParams::create() 7012623SN/A{ 7025529Snate@binkert.org return new AtomicSimpleCPU(this); 7032623SN/A} 704