atomic.cc revision 12127
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 311147Smitch.hayenga@arm.com * Copyright (c) 2012-2013,2015 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 4411793Sbrandon.potter@amd.com#include "cpu/simple/atomic.hh" 4511793Sbrandon.potter@amd.com 463170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 478105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 482623SN/A#include "arch/utility.hh" 494040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 509647Sdam.sunwoo@arm.com#include "base/output.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 522623SN/A#include "cpu/exetrace.hh" 539443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 548232Snate@binkert.org#include "debug/ExecFaulting.hh" 558232Snate@binkert.org#include "debug/SimpleCPU.hh" 563348Sbinkertn@umich.edu#include "mem/packet.hh" 573348Sbinkertn@umich.edu#include "mem/packet_access.hh" 588926Sandreas.hansson@arm.com#include "mem/physical.hh" 594762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 607678Sgblack@eecs.umich.edu#include "sim/faults.hh" 6111793Sbrandon.potter@amd.com#include "sim/full_system.hh" 622901Ssaidi@eecs.umich.edu#include "sim/system.hh" 632623SN/A 642623SN/Ausing namespace std; 652623SN/Ausing namespace TheISA; 662623SN/A 672623SN/Avoid 682623SN/AAtomicSimpleCPU::init() 692623SN/A{ 7011147Smitch.hayenga@arm.com BaseSimpleCPU::init(); 718921Sandreas.hansson@arm.com 7211148Smitch.hayenga@arm.com int cid = threadContexts[0]->contextId(); 7311435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 7411435Smitch.hayenga@arm.com data_read_req.setContext(cid); 7511435Smitch.hayenga@arm.com data_write_req.setContext(cid); 762623SN/A} 772623SN/A 785529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 7912127Sspwilson2@wisc.edu : BaseSimpleCPU(p), 8012127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 8112127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 8212127Sspwilson2@wisc.edu width(p->width), locked(false), 835487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 845487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 859095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 869095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 8710537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 8810537Sandreas.hansson@arm.com ppCommit(nullptr) 892623SN/A{ 902623SN/A _status = Idle; 912623SN/A} 922623SN/A 932623SN/A 942623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 952623SN/A{ 966775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 976775SBrad.Beckmann@amd.com deschedule(tickEvent); 986775SBrad.Beckmann@amd.com } 992623SN/A} 1002623SN/A 10110913Sandreas.sandberg@arm.comDrainState 10210913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1032623SN/A{ 1049448SAndreas.Sandberg@ARM.com if (switchedOut()) 10510913Sandreas.sandberg@arm.com return DrainState::Drained; 1062623SN/A 1079443SAndreas.Sandberg@ARM.com if (!isDrained()) { 10811147Smitch.hayenga@arm.com DPRINTF(Drain, "Requesting drain.\n"); 10910913Sandreas.sandberg@arm.com return DrainState::Draining; 1109443SAndreas.Sandberg@ARM.com } else { 1119443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1129443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1132915Sktlim@umich.edu 11411147Smitch.hayenga@arm.com activeThreads.clear(); 1159443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 11610913Sandreas.sandberg@arm.com return DrainState::Drained; 1179443SAndreas.Sandberg@ARM.com } 1189342SAndreas.Sandberg@arm.com} 1199342SAndreas.Sandberg@arm.com 1202915Sktlim@umich.eduvoid 12111148Smitch.hayenga@arm.comAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 12211148Smitch.hayenga@arm.com{ 12311148Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 12411148Smitch.hayenga@arm.com pkt->cmdString()); 12511148Smitch.hayenga@arm.com 12611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 12711148Smitch.hayenga@arm.com if (tid != sender) { 12811321Ssteve.reinhardt@amd.com if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12911151Smitch.hayenga@arm.com wakeup(tid); 13011148Smitch.hayenga@arm.com } 13111148Smitch.hayenga@arm.com 13211148Smitch.hayenga@arm.com TheISA::handleLockedSnoop(threadInfo[tid]->thread, 13311148Smitch.hayenga@arm.com pkt, dcachePort.cacheBlockMask); 13411148Smitch.hayenga@arm.com } 13511148Smitch.hayenga@arm.com } 13611148Smitch.hayenga@arm.com} 13711148Smitch.hayenga@arm.com 13811148Smitch.hayenga@arm.comvoid 1399342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1402915Sktlim@umich.edu{ 1419448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1429448SAndreas.Sandberg@ARM.com if (switchedOut()) 1435220Ssaidi@eecs.umich.edu return; 1445220Ssaidi@eecs.umich.edu 1454940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1469523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1473324Shsul@eecs.umich.edu 1489448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1499448SAndreas.Sandberg@ARM.com 15011147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Idle; 15111147Smitch.hayenga@arm.com 15211147Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 15311147Smitch.hayenga@arm.com if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 15411147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 1; 15511147Smitch.hayenga@arm.com activeThreads.push_back(tid); 15611147Smitch.hayenga@arm.com _status = BaseSimpleCPU::Running; 15711147Smitch.hayenga@arm.com 15811147Smitch.hayenga@arm.com // Tick if any threads active 15911147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 16011147Smitch.hayenga@arm.com schedule(tickEvent, nextCycle()); 16111147Smitch.hayenga@arm.com } 16211147Smitch.hayenga@arm.com } else { 16311147Smitch.hayenga@arm.com threadInfo[tid]->notIdleFraction = 0; 16411147Smitch.hayenga@arm.com } 1659448SAndreas.Sandberg@ARM.com } 1662623SN/A} 1672623SN/A 1689443SAndreas.Sandberg@ARM.combool 1699443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1709443SAndreas.Sandberg@ARM.com{ 17110913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1729443SAndreas.Sandberg@ARM.com return false; 1739443SAndreas.Sandberg@ARM.com 17411147Smitch.hayenga@arm.com DPRINTF(Drain, "tryCompleteDrain.\n"); 1759443SAndreas.Sandberg@ARM.com if (!isDrained()) 1769443SAndreas.Sandberg@ARM.com return false; 1779443SAndreas.Sandberg@ARM.com 1789443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 17910913Sandreas.sandberg@arm.com signalDrainDone(); 1809443SAndreas.Sandberg@ARM.com 1819443SAndreas.Sandberg@ARM.com return true; 1829443SAndreas.Sandberg@ARM.com} 1839443SAndreas.Sandberg@ARM.com 1849443SAndreas.Sandberg@ARM.com 1852623SN/Avoid 1862798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1872623SN/A{ 1889429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1899429SAndreas.Sandberg@ARM.com 1909443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1919342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1929443SAndreas.Sandberg@ARM.com assert(isDrained()); 1932623SN/A} 1942623SN/A 1952623SN/A 1962623SN/Avoid 1972623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1982623SN/A{ 1999429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2002623SN/A 2019443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2022623SN/A assert(!tickEvent.scheduled()); 2032623SN/A} 2042623SN/A 2059523SAndreas.Sandberg@ARM.comvoid 2069523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2079523SAndreas.Sandberg@ARM.com{ 2089524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2099523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2109523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2119523SAndreas.Sandberg@ARM.com } 2129523SAndreas.Sandberg@ARM.com} 2132623SN/A 2142623SN/Avoid 21510407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2162623SN/A{ 21710407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2184940Snate@binkert.org 21911147Smitch.hayenga@arm.com assert(thread_num < numThreads); 2202623SN/A 22111147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 1; 22211147Smitch.hayenga@arm.com Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 22311147Smitch.hayenga@arm.com threadInfo[thread_num]->thread->lastSuspend); 22410464SAndreas.Sandberg@ARM.com numCycles += delta; 22510464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2263686Sktlim@umich.edu 22711147Smitch.hayenga@arm.com if (!tickEvent.scheduled()) { 22811147Smitch.hayenga@arm.com //Make sure ticks are still on multiples of cycles 22911147Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 23011147Smitch.hayenga@arm.com } 2319342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 23211147Smitch.hayenga@arm.com if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 23311147Smitch.hayenga@arm.com == activeThreads.end()) { 23411147Smitch.hayenga@arm.com activeThreads.push_back(thread_num); 23511147Smitch.hayenga@arm.com } 23611526Sdavid.guillen@arm.com 23711526Sdavid.guillen@arm.com BaseCPU::activateContext(thread_num); 2382623SN/A} 2392623SN/A 2402623SN/A 2412623SN/Avoid 2428737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2432623SN/A{ 2444940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2454940Snate@binkert.org 24611147Smitch.hayenga@arm.com assert(thread_num < numThreads); 24711147Smitch.hayenga@arm.com activeThreads.remove(thread_num); 2482623SN/A 2496043Sgblack@eecs.umich.edu if (_status == Idle) 2506043Sgblack@eecs.umich.edu return; 2516043Sgblack@eecs.umich.edu 2529342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2532626SN/A 25411147Smitch.hayenga@arm.com threadInfo[thread_num]->notIdleFraction = 0; 2552623SN/A 25611147Smitch.hayenga@arm.com if (activeThreads.empty()) { 25711147Smitch.hayenga@arm.com _status = Idle; 25811147Smitch.hayenga@arm.com 25911147Smitch.hayenga@arm.com if (tickEvent.scheduled()) { 26011147Smitch.hayenga@arm.com deschedule(tickEvent); 26111147Smitch.hayenga@arm.com } 26211147Smitch.hayenga@arm.com } 26311147Smitch.hayenga@arm.com 26411526Sdavid.guillen@arm.com BaseCPU::suspendContext(thread_num); 2652623SN/A} 2662623SN/A 2672623SN/A 26810030SAli.Saidi@ARM.comTick 26910030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 27010030SAli.Saidi@ARM.com{ 27110030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27210030SAli.Saidi@ARM.com pkt->cmdString()); 27310030SAli.Saidi@ARM.com 27410529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 27510529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 27611148Smitch.hayenga@arm.com 27711148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 27811148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 27911151Smitch.hayenga@arm.com cpu->wakeup(tid); 28011148Smitch.hayenga@arm.com } 28110529Smorr@cs.wisc.edu } 28210529Smorr@cs.wisc.edu 28310030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 28411356Skrinat01@arm.com // When run without caches, Invalidation packets will not be received 28511356Skrinat01@arm.com // hence we must check if the incoming packets are writes and wakeup 28611356Skrinat01@arm.com // the processor accordingly 28711356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 28810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 28910030SAli.Saidi@ARM.com pkt->getAddr()); 29011147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 29111147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 29211147Smitch.hayenga@arm.com } 29310030SAli.Saidi@ARM.com } 29410030SAli.Saidi@ARM.com 29510030SAli.Saidi@ARM.com return 0; 29610030SAli.Saidi@ARM.com} 29710030SAli.Saidi@ARM.com 29810030SAli.Saidi@ARM.comvoid 29910030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 30010030SAli.Saidi@ARM.com{ 30110030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 30210030SAli.Saidi@ARM.com pkt->cmdString()); 30310030SAli.Saidi@ARM.com 30410529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 30510529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 30611148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 30711321Ssteve.reinhardt@amd.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 30811151Smitch.hayenga@arm.com cpu->wakeup(tid); 30911148Smitch.hayenga@arm.com } 31010529Smorr@cs.wisc.edu } 31110529Smorr@cs.wisc.edu 31210030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 31310030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 31410030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 31510030SAli.Saidi@ARM.com pkt->getAddr()); 31611147Smitch.hayenga@arm.com for (auto &t_info : cpu->threadInfo) { 31711147Smitch.hayenga@arm.com TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 31811147Smitch.hayenga@arm.com } 31910030SAli.Saidi@ARM.com } 32010030SAli.Saidi@ARM.com} 32110030SAli.Saidi@ARM.com 3222623SN/AFault 32311608Snikos.nikoleris@arm.comAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, 32411608Snikos.nikoleris@arm.com Request::Flags flags) 3252623SN/A{ 32611147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 32711147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 32811147Smitch.hayenga@arm.com 3293169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3304870Sstever@eecs.umich.edu Request *req = &data_read_req; 3312623SN/A 33210665SAli.Saidi@ARM.com if (traceData) 33310665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3342623SN/A 3354999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3367520Sgblack@eecs.umich.edu int fullSize = size; 3372623SN/A 3384999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3394999Sgblack@eecs.umich.edu //across a cache line boundary. 3409814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3414999Sgblack@eecs.umich.edu 3427520Sgblack@eecs.umich.edu if (secondAddr > addr) 3437520Sgblack@eecs.umich.edu size = secondAddr - addr; 3444999Sgblack@eecs.umich.edu 3454999Sgblack@eecs.umich.edu dcache_latency = 0; 3464999Sgblack@eecs.umich.edu 34710024Sdam.sunwoo@arm.com req->taskId(taskId()); 3487520Sgblack@eecs.umich.edu while (1) { 3498832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3504999Sgblack@eecs.umich.edu 3514999Sgblack@eecs.umich.edu // translate to physical address 35211147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 35311147Smitch.hayenga@arm.com BaseTLB::Read); 3544999Sgblack@eecs.umich.edu 3554999Sgblack@eecs.umich.edu // Now do the access. 3566623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 35710739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3587520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3594999Sgblack@eecs.umich.edu 3608105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3614999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3624999Sgblack@eecs.umich.edu else { 3638931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3648931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3654999Sgblack@eecs.umich.edu else 3664999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3674999Sgblack@eecs.umich.edu } 3684999Sgblack@eecs.umich.edu dcache_access = true; 3695012Sgblack@eecs.umich.edu 3704999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3714999Sgblack@eecs.umich.edu 3726102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3734999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3744999Sgblack@eecs.umich.edu } 3754968Sacolyte@umich.edu } 3764986Ssaidi@eecs.umich.edu 3774999Sgblack@eecs.umich.edu //If there's a fault, return it 3786739Sgblack@eecs.umich.edu if (fault != NoFault) { 3796739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3806739Sgblack@eecs.umich.edu return NoFault; 3816739Sgblack@eecs.umich.edu } else { 3826739Sgblack@eecs.umich.edu return fault; 3836739Sgblack@eecs.umich.edu } 3846739Sgblack@eecs.umich.edu } 3856739Sgblack@eecs.umich.edu 3864999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3874999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3884999Sgblack@eecs.umich.edu { 38910760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3906078Sgblack@eecs.umich.edu assert(!locked); 3916078Sgblack@eecs.umich.edu locked = true; 3926078Sgblack@eecs.umich.edu } 39311147Smitch.hayenga@arm.com 3944999Sgblack@eecs.umich.edu return fault; 3954968Sacolyte@umich.edu } 3963170Sstever@eecs.umich.edu 3974999Sgblack@eecs.umich.edu /* 3984999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3994999Sgblack@eecs.umich.edu */ 4004999Sgblack@eecs.umich.edu 4014999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4027520Sgblack@eecs.umich.edu data += size; 4034999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4047520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4054999Sgblack@eecs.umich.edu //And access the right address. 4064999Sgblack@eecs.umich.edu addr = secondAddr; 4072623SN/A } 4082623SN/A} 4092623SN/A 41011303Ssteve.reinhardt@amd.comFault 41111608Snikos.nikoleris@arm.comAtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, 41211608Snikos.nikoleris@arm.com Request::Flags flags) 41311303Ssteve.reinhardt@amd.com{ 41411303Ssteve.reinhardt@amd.com panic("initiateMemRead() is for timing accesses, and should " 41511303Ssteve.reinhardt@amd.com "never be called on AtomicSimpleCPU.\n"); 41611303Ssteve.reinhardt@amd.com} 4177520Sgblack@eecs.umich.edu 4182623SN/AFault 41911608Snikos.nikoleris@arm.comAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, 42011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 4212623SN/A{ 42211147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 42311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 42410031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 42510031SAli.Saidi@ARM.com 42610031SAli.Saidi@ARM.com if (data == NULL) { 42710031SAli.Saidi@ARM.com assert(size <= 64); 42810031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 42910031SAli.Saidi@ARM.com // This must be a cache block cleaning request 43010031SAli.Saidi@ARM.com data = zero_array; 43110031SAli.Saidi@ARM.com } 43210031SAli.Saidi@ARM.com 4333169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4344870Sstever@eecs.umich.edu Request *req = &data_write_req; 4352623SN/A 43610665SAli.Saidi@ARM.com if (traceData) 43710665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4382623SN/A 4394999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4407520Sgblack@eecs.umich.edu int fullSize = size; 4412623SN/A 4424999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4434999Sgblack@eecs.umich.edu //across a cache line boundary. 4449814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4454999Sgblack@eecs.umich.edu 44611321Ssteve.reinhardt@amd.com if (secondAddr > addr) 4477520Sgblack@eecs.umich.edu size = secondAddr - addr; 4484999Sgblack@eecs.umich.edu 4494999Sgblack@eecs.umich.edu dcache_latency = 0; 4504999Sgblack@eecs.umich.edu 45110024Sdam.sunwoo@arm.com req->taskId(taskId()); 45211321Ssteve.reinhardt@amd.com while (1) { 4538832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4544999Sgblack@eecs.umich.edu 4554999Sgblack@eecs.umich.edu // translate to physical address 45611147Smitch.hayenga@arm.com Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 4574999Sgblack@eecs.umich.edu 4584999Sgblack@eecs.umich.edu // Now do the access. 4594999Sgblack@eecs.umich.edu if (fault == NoFault) { 4604999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4614999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4624999Sgblack@eecs.umich.edu 4636102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4644999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 46510030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4664999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4674999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4684999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4694999Sgblack@eecs.umich.edu assert(res); 4704999Sgblack@eecs.umich.edu req->setExtraData(*res); 4714999Sgblack@eecs.umich.edu } 4724999Sgblack@eecs.umich.edu } 4734999Sgblack@eecs.umich.edu 4746623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4758949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4767520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4774999Sgblack@eecs.umich.edu 4788105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4794999Sgblack@eecs.umich.edu dcache_latency += 4804999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4814999Sgblack@eecs.umich.edu } else { 4828931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4838931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4844999Sgblack@eecs.umich.edu else 4854999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 48611148Smitch.hayenga@arm.com 48711148Smitch.hayenga@arm.com // Notify other threads on this CPU of write 48811148Smitch.hayenga@arm.com threadSnoop(&pkt, curThread); 4894999Sgblack@eecs.umich.edu } 4904999Sgblack@eecs.umich.edu dcache_access = true; 4914999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4924999Sgblack@eecs.umich.edu 4934999Sgblack@eecs.umich.edu if (req->isSwap()) { 4944999Sgblack@eecs.umich.edu assert(res); 49510563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 4964999Sgblack@eecs.umich.edu } 4974999Sgblack@eecs.umich.edu } 4984999Sgblack@eecs.umich.edu 4994999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 5004999Sgblack@eecs.umich.edu *res = req->getExtraData(); 5014878Sstever@eecs.umich.edu } 5024040Ssaidi@eecs.umich.edu } 5034040Ssaidi@eecs.umich.edu 5044999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 5054999Sgblack@eecs.umich.edu //stop now. 5064999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 5074999Sgblack@eecs.umich.edu { 50810760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 5096078Sgblack@eecs.umich.edu assert(locked); 5106078Sgblack@eecs.umich.edu locked = false; 5116078Sgblack@eecs.umich.edu } 51211147Smitch.hayenga@arm.com 51311147Smitch.hayenga@arm.com 5146739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 5156739Sgblack@eecs.umich.edu return NoFault; 5166739Sgblack@eecs.umich.edu } else { 5176739Sgblack@eecs.umich.edu return fault; 5186739Sgblack@eecs.umich.edu } 5193170Sstever@eecs.umich.edu } 5203170Sstever@eecs.umich.edu 5214999Sgblack@eecs.umich.edu /* 5224999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 5234999Sgblack@eecs.umich.edu */ 5244999Sgblack@eecs.umich.edu 5254999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 5267520Sgblack@eecs.umich.edu data += size; 5274999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 5287520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 5294999Sgblack@eecs.umich.edu //And access the right address. 5304999Sgblack@eecs.umich.edu addr = secondAddr; 5312623SN/A } 5322623SN/A} 5332623SN/A 5342623SN/A 5352623SN/Avoid 5362623SN/AAtomicSimpleCPU::tick() 5372623SN/A{ 5384940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5394940Snate@binkert.org 54011147Smitch.hayenga@arm.com // Change thread if multi-threaded 54111147Smitch.hayenga@arm.com swapActiveThread(); 54211147Smitch.hayenga@arm.com 54311147Smitch.hayenga@arm.com // Set memroy request ids to current thread 54411147Smitch.hayenga@arm.com if (numThreads > 1) { 54511148Smitch.hayenga@arm.com ContextID cid = threadContexts[curThread]->contextId(); 54611148Smitch.hayenga@arm.com 54711435Smitch.hayenga@arm.com ifetch_req.setContext(cid); 54811435Smitch.hayenga@arm.com data_read_req.setContext(cid); 54911435Smitch.hayenga@arm.com data_write_req.setContext(cid); 55011147Smitch.hayenga@arm.com } 55111147Smitch.hayenga@arm.com 55211147Smitch.hayenga@arm.com SimpleExecContext& t_info = *threadInfo[curThread]; 55311147Smitch.hayenga@arm.com SimpleThread* thread = t_info.thread; 55411147Smitch.hayenga@arm.com 5555487Snate@binkert.org Tick latency = 0; 5562623SN/A 5576078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5582623SN/A numCycles++; 55910464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5602623SN/A 56110596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5623387Sgblack@eecs.umich.edu checkForInterrupts(); 56310596Sgabeblack@google.com checkPcEventQueue(); 56410596Sgabeblack@google.com } 5652626SN/A 5668143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5679443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5689443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5698143SAli.Saidi@ARM.com return; 5709443SAndreas.Sandberg@ARM.com } 5715348Ssaidi@eecs.umich.edu 5725669Sgblack@eecs.umich.edu Fault fault = NoFault; 5735669Sgblack@eecs.umich.edu 5747720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5757720Sgblack@eecs.umich.edu 5767720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5777720Sgblack@eecs.umich.edu !curMacroStaticInst; 5787720Sgblack@eecs.umich.edu if (needToFetch) { 57910024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5805894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 58111147Smitch.hayenga@arm.com fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 5826023Snate@binkert.org BaseTLB::Execute); 5835894Sgblack@eecs.umich.edu } 5842623SN/A 5852623SN/A if (fault == NoFault) { 5864182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5874182Sgblack@eecs.umich.edu bool icache_access = false; 5884182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5892662Sstever@eecs.umich.edu 5907720Sgblack@eecs.umich.edu if (needToFetch) { 5919023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5925694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5935694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5945694Sgblack@eecs.umich.edu // this code should be uncommented. 5955669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 59611321Ssteve.reinhardt@amd.com //if (decoder.needMoreBytes()) 5975669Sgblack@eecs.umich.edu //{ 5985669Sgblack@eecs.umich.edu icache_access = true; 5998949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 6005669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 6012623SN/A 6028931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 6038931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 6045669Sgblack@eecs.umich.edu else 6055669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 6064968Sacolyte@umich.edu 6075669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 6084968Sacolyte@umich.edu 6095669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 6105669Sgblack@eecs.umich.edu // into the CPU object's inst field. 6115669Sgblack@eecs.umich.edu //} 6125669Sgblack@eecs.umich.edu } 6134182Sgblack@eecs.umich.edu 6142623SN/A preExecute(); 6153814Ssaidi@eecs.umich.edu 61611877Sbrandon.potter@amd.com Tick stall_ticks = 0; 6175001Sgblack@eecs.umich.edu if (curStaticInst) { 61811147Smitch.hayenga@arm.com fault = curStaticInst->execute(&t_info, traceData); 6194998Sgblack@eecs.umich.edu 6204998Sgblack@eecs.umich.edu // keep an instruction count 62110381Sdam.sunwoo@arm.com if (fault == NoFault) { 6224998Sgblack@eecs.umich.edu countInst(); 62310651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 62410381Sdam.sunwoo@arm.com } 6257655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 6265001Sgblack@eecs.umich.edu delete traceData; 6275001Sgblack@eecs.umich.edu traceData = NULL; 6285001Sgblack@eecs.umich.edu } 6294998Sgblack@eecs.umich.edu 63011877Sbrandon.potter@amd.com if (dynamic_pointer_cast<SyscallRetryFault>(fault)) { 63111877Sbrandon.potter@amd.com // Retry execution of system calls after a delay. 63211877Sbrandon.potter@amd.com // Prevents immediate re-execution since conditions which 63311877Sbrandon.potter@amd.com // caused the retry are unlikely to change every tick. 63411877Sbrandon.potter@amd.com stall_ticks += clockEdge(syscallRetryLatency) - curTick(); 63511877Sbrandon.potter@amd.com } 63611877Sbrandon.potter@amd.com 6374182Sgblack@eecs.umich.edu postExecute(); 6384182Sgblack@eecs.umich.edu } 6392623SN/A 6403814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 6414539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 6424539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 6433814Ssaidi@eecs.umich.edu instCnt++; 6443814Ssaidi@eecs.umich.edu 6455487Snate@binkert.org if (simulate_inst_stalls && icache_access) 6465487Snate@binkert.org stall_ticks += icache_latency; 6475487Snate@binkert.org 6485487Snate@binkert.org if (simulate_data_stalls && dcache_access) 6495487Snate@binkert.org stall_ticks += dcache_latency; 6505487Snate@binkert.org 6515487Snate@binkert.org if (stall_ticks) { 6529180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 6539180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 6549180Sandreas.hansson@arm.com // period 6559180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6569180Sandreas.hansson@arm.com clockPeriod(); 6572623SN/A } 6582623SN/A 6592623SN/A } 66011321Ssteve.reinhardt@amd.com if (fault != NoFault || !t_info.stayAtPC) 6614182Sgblack@eecs.umich.edu advancePC(fault); 6622623SN/A } 6632623SN/A 6649443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6659443SAndreas.Sandberg@ARM.com return; 6669443SAndreas.Sandberg@ARM.com 6675487Snate@binkert.org // instruction takes at least one cycle 6689179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6699179Sandreas.hansson@arm.com latency = clockPeriod(); 6705487Snate@binkert.org 6712626SN/A if (_status != Idle) 67211147Smitch.hayenga@arm.com reschedule(tickEvent, curTick() + latency, true); 6732623SN/A} 6742623SN/A 67510381Sdam.sunwoo@arm.comvoid 67610381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 67710381Sdam.sunwoo@arm.com{ 67810464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 67910464SAndreas.Sandberg@ARM.com 68010381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 68110381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 68210381Sdam.sunwoo@arm.com} 6832623SN/A 6845315Sstever@gmail.comvoid 6855315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6865315Sstever@gmail.com{ 6875315Sstever@gmail.com dcachePort.printAddr(a); 6885315Sstever@gmail.com} 6895315Sstever@gmail.com 6902623SN/A//////////////////////////////////////////////////////////////////////// 6912623SN/A// 6922623SN/A// AtomicSimpleCPU Simulation Object 6932623SN/A// 6944762Snate@binkert.orgAtomicSimpleCPU * 6954762Snate@binkert.orgAtomicSimpleCPUParams::create() 6962623SN/A{ 6975529Snate@binkert.org return new AtomicSimpleCPU(this); 6982623SN/A} 699