atomic.cc revision 11526
17202Sgblack@eecs.umich.edu/* 27202Sgblack@eecs.umich.edu * Copyright 2014 Google, Inc. 37202Sgblack@eecs.umich.edu * Copyright (c) 2012-2013,2015 ARM Limited 47202Sgblack@eecs.umich.edu * All rights reserved. 57202Sgblack@eecs.umich.edu * 67202Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 77202Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 87202Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 97202Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 107202Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 117202Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 127202Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 137202Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 147202Sgblack@eecs.umich.edu * 157202Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 167202Sgblack@eecs.umich.edu * All rights reserved. 177202Sgblack@eecs.umich.edu * 187202Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 197202Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 207202Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 217202Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 227202Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 237202Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 247202Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 257202Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 267202Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 277202Sgblack@eecs.umich.edu * this software without specific prior written permission. 287202Sgblack@eecs.umich.edu * 297202Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307202Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317202Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327202Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337202Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347202Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357202Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367202Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377202Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387202Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397202Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407202Sgblack@eecs.umich.edu * 417202Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 427202Sgblack@eecs.umich.edu */ 437202Sgblack@eecs.umich.edu 447202Sgblack@eecs.umich.edu#include "arch/locked_mem.hh" 457202Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 467202Sgblack@eecs.umich.edu#include "arch/utility.hh" 477202Sgblack@eecs.umich.edu#include "base/bigint.hh" 487202Sgblack@eecs.umich.edu#include "base/output.hh" 497202Sgblack@eecs.umich.edu#include "config/the_isa.hh" 507202Sgblack@eecs.umich.edu#include "cpu/simple/atomic.hh" 517202Sgblack@eecs.umich.edu#include "cpu/exetrace.hh" 527202Sgblack@eecs.umich.edu#include "debug/Drain.hh" 537202Sgblack@eecs.umich.edu#include "debug/ExecFaulting.hh" 547202Sgblack@eecs.umich.edu#include "debug/SimpleCPU.hh" 557202Sgblack@eecs.umich.edu#include "mem/packet.hh" 567202Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 577202Sgblack@eecs.umich.edu#include "mem/physical.hh" 587202Sgblack@eecs.umich.edu#include "params/AtomicSimpleCPU.hh" 597202Sgblack@eecs.umich.edu#include "sim/faults.hh" 607202Sgblack@eecs.umich.edu#include "sim/system.hh" 617202Sgblack@eecs.umich.edu#include "sim/full_system.hh" 627202Sgblack@eecs.umich.edu 637202Sgblack@eecs.umich.eduusing namespace std; 647202Sgblack@eecs.umich.eduusing namespace TheISA; 657202Sgblack@eecs.umich.edu 667202Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 677202Sgblack@eecs.umich.edu : Event(CPU_Tick_Pri), cpu(c) 687202Sgblack@eecs.umich.edu{ 697202Sgblack@eecs.umich.edu} 707202Sgblack@eecs.umich.edu 717202Sgblack@eecs.umich.edu 727202Sgblack@eecs.umich.eduvoid 737202Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::process() 747202Sgblack@eecs.umich.edu{ 757202Sgblack@eecs.umich.edu cpu->tick(); 767202Sgblack@eecs.umich.edu} 777202Sgblack@eecs.umich.edu 787202Sgblack@eecs.umich.educonst char * 797202Sgblack@eecs.umich.eduAtomicSimpleCPU::TickEvent::description() const 807202Sgblack@eecs.umich.edu{ 817202Sgblack@eecs.umich.edu return "AtomicSimpleCPU tick"; 827202Sgblack@eecs.umich.edu} 837202Sgblack@eecs.umich.edu 847202Sgblack@eecs.umich.eduvoid 857202Sgblack@eecs.umich.eduAtomicSimpleCPU::init() 867202Sgblack@eecs.umich.edu{ 877202Sgblack@eecs.umich.edu BaseSimpleCPU::init(); 887202Sgblack@eecs.umich.edu 897202Sgblack@eecs.umich.edu int cid = threadContexts[0]->contextId(); 907202Sgblack@eecs.umich.edu ifetch_req.setContext(cid); 917202Sgblack@eecs.umich.edu data_read_req.setContext(cid); 927202Sgblack@eecs.umich.edu data_write_req.setContext(cid); 937202Sgblack@eecs.umich.edu} 947202Sgblack@eecs.umich.edu 957202Sgblack@eecs.umich.eduAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 967202Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 977202Sgblack@eecs.umich.edu simulate_data_stalls(p->simulate_data_stalls), 987202Sgblack@eecs.umich.edu simulate_inst_stalls(p->simulate_inst_stalls), 997202Sgblack@eecs.umich.edu icachePort(name() + ".icache_port", this), 1007202Sgblack@eecs.umich.edu dcachePort(name() + ".dcache_port", this), 1017208Sgblack@eecs.umich.edu fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 1027306Sgblack@eecs.umich.edu ppCommit(nullptr) 1037306Sgblack@eecs.umich.edu{ 1047306Sgblack@eecs.umich.edu _status = Idle; 1057306Sgblack@eecs.umich.edu} 1067306Sgblack@eecs.umich.edu 1077306Sgblack@eecs.umich.edu 1087330Sgblack@eecs.umich.eduAtomicSimpleCPU::~AtomicSimpleCPU() 1097306Sgblack@eecs.umich.edu{ 1107306Sgblack@eecs.umich.edu if (tickEvent.scheduled()) { 1117306Sgblack@eecs.umich.edu deschedule(tickEvent); 1127306Sgblack@eecs.umich.edu } 1137306Sgblack@eecs.umich.edu} 1147330Sgblack@eecs.umich.edu 1157306Sgblack@eecs.umich.eduDrainState 1167306Sgblack@eecs.umich.eduAtomicSimpleCPU::drain() 1177306Sgblack@eecs.umich.edu{ 1187306Sgblack@eecs.umich.edu if (switchedOut()) 1197306Sgblack@eecs.umich.edu return DrainState::Drained; 1207306Sgblack@eecs.umich.edu 1217332Sgblack@eecs.umich.edu if (!isDrained()) { 1227332Sgblack@eecs.umich.edu DPRINTF(Drain, "Requesting drain.\n"); 1237332Sgblack@eecs.umich.edu return DrainState::Draining; 1247332Sgblack@eecs.umich.edu } else { 1257332Sgblack@eecs.umich.edu if (tickEvent.scheduled()) 1267332Sgblack@eecs.umich.edu deschedule(tickEvent); 1277332Sgblack@eecs.umich.edu 1287332Sgblack@eecs.umich.edu activeThreads.clear(); 1297332Sgblack@eecs.umich.edu DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 1307332Sgblack@eecs.umich.edu return DrainState::Drained; 1317332Sgblack@eecs.umich.edu } 1327332Sgblack@eecs.umich.edu} 1337332Sgblack@eecs.umich.edu 1347332Sgblack@eecs.umich.eduvoid 1357332Sgblack@eecs.umich.eduAtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) 1367332Sgblack@eecs.umich.edu{ 1377332Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 1387332Sgblack@eecs.umich.edu pkt->cmdString()); 1397332Sgblack@eecs.umich.edu 1407332Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1417261Sgblack@eecs.umich.edu if (tid != sender) { 1427208Sgblack@eecs.umich.edu if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 1437208Sgblack@eecs.umich.edu wakeup(tid); 1447208Sgblack@eecs.umich.edu } 1457208Sgblack@eecs.umich.edu 1467208Sgblack@eecs.umich.edu TheISA::handleLockedSnoop(threadInfo[tid]->thread, 1477208Sgblack@eecs.umich.edu pkt, dcachePort.cacheBlockMask); 1487208Sgblack@eecs.umich.edu } 1497208Sgblack@eecs.umich.edu } 1507208Sgblack@eecs.umich.edu} 1517208Sgblack@eecs.umich.edu 1527208Sgblack@eecs.umich.eduvoid 1537261Sgblack@eecs.umich.eduAtomicSimpleCPU::drainResume() 1547208Sgblack@eecs.umich.edu{ 1557208Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 1567208Sgblack@eecs.umich.edu if (switchedOut()) 1577208Sgblack@eecs.umich.edu return; 1587208Sgblack@eecs.umich.edu 1597208Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 1607208Sgblack@eecs.umich.edu verifyMemoryMode(); 1617225Sgblack@eecs.umich.edu 1627233Sgblack@eecs.umich.edu assert(!threadContexts.empty()); 1637233Sgblack@eecs.umich.edu 1647233Sgblack@eecs.umich.edu _status = BaseSimpleCPU::Idle; 1657233Sgblack@eecs.umich.edu 1667233Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 1677233Sgblack@eecs.umich.edu if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 1687233Sgblack@eecs.umich.edu threadInfo[tid]->notIdleFraction = 1; 1697233Sgblack@eecs.umich.edu activeThreads.push_back(tid); 1707330Sgblack@eecs.umich.edu _status = BaseSimpleCPU::Running; 1717233Sgblack@eecs.umich.edu 1727233Sgblack@eecs.umich.edu // Tick if any threads active 1737233Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 1747233Sgblack@eecs.umich.edu schedule(tickEvent, nextCycle()); 1757233Sgblack@eecs.umich.edu } 1767233Sgblack@eecs.umich.edu } else { 1777233Sgblack@eecs.umich.edu threadInfo[tid]->notIdleFraction = 0; 1787233Sgblack@eecs.umich.edu } 1797233Sgblack@eecs.umich.edu } 1807330Sgblack@eecs.umich.edu} 1817233Sgblack@eecs.umich.edu 1827233Sgblack@eecs.umich.edubool 1837233Sgblack@eecs.umich.eduAtomicSimpleCPU::tryCompleteDrain() 1847233Sgblack@eecs.umich.edu{ 1857233Sgblack@eecs.umich.edu if (drainState() != DrainState::Draining) 1867233Sgblack@eecs.umich.edu return false; 1877233Sgblack@eecs.umich.edu 1887241Sgblack@eecs.umich.edu DPRINTF(Drain, "tryCompleteDrain.\n"); 1897241Sgblack@eecs.umich.edu if (!isDrained()) 1907241Sgblack@eecs.umich.edu return false; 1917241Sgblack@eecs.umich.edu 1927241Sgblack@eecs.umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1937241Sgblack@eecs.umich.edu signalDrainDone(); 1947241Sgblack@eecs.umich.edu 1957241Sgblack@eecs.umich.edu return true; 1967241Sgblack@eecs.umich.edu} 1977241Sgblack@eecs.umich.edu 1987241Sgblack@eecs.umich.edu 1997241Sgblack@eecs.umich.eduvoid 2007241Sgblack@eecs.umich.eduAtomicSimpleCPU::switchOut() 2017241Sgblack@eecs.umich.edu{ 2027241Sgblack@eecs.umich.edu BaseSimpleCPU::switchOut(); 2037241Sgblack@eecs.umich.edu 2047241Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 2057241Sgblack@eecs.umich.edu assert(_status == BaseSimpleCPU::Running || _status == Idle); 2067241Sgblack@eecs.umich.edu assert(isDrained()); 2077241Sgblack@eecs.umich.edu} 2087241Sgblack@eecs.umich.edu 2097241Sgblack@eecs.umich.edu 2107241Sgblack@eecs.umich.eduvoid 2117241Sgblack@eecs.umich.eduAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2127241Sgblack@eecs.umich.edu{ 2137241Sgblack@eecs.umich.edu BaseSimpleCPU::takeOverFrom(oldCPU); 2147238Sgblack@eecs.umich.edu 2157238Sgblack@eecs.umich.edu // The tick event should have been descheduled by drain() 2167238Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 2177238Sgblack@eecs.umich.edu} 2187238Sgblack@eecs.umich.edu 2197238Sgblack@eecs.umich.eduvoid 2207238Sgblack@eecs.umich.eduAtomicSimpleCPU::verifyMemoryMode() const 2217238Sgblack@eecs.umich.edu{ 2227238Sgblack@eecs.umich.edu if (!system->isAtomicMode()) { 2237238Sgblack@eecs.umich.edu fatal("The atomic CPU requires the memory system to be in " 2247238Sgblack@eecs.umich.edu "'atomic' mode.\n"); 2257238Sgblack@eecs.umich.edu } 2267238Sgblack@eecs.umich.edu} 2277238Sgblack@eecs.umich.edu 2287238Sgblack@eecs.umich.eduvoid 2297238Sgblack@eecs.umich.eduAtomicSimpleCPU::activateContext(ThreadID thread_num) 2307238Sgblack@eecs.umich.edu{ 2317238Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2327238Sgblack@eecs.umich.edu 2337238Sgblack@eecs.umich.edu assert(thread_num < numThreads); 2347238Sgblack@eecs.umich.edu 2357238Sgblack@eecs.umich.edu threadInfo[thread_num]->notIdleFraction = 1; 2367238Sgblack@eecs.umich.edu Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 2377238Sgblack@eecs.umich.edu threadInfo[thread_num]->thread->lastSuspend); 2387331Sgblack@eecs.umich.edu numCycles += delta; 2397331Sgblack@eecs.umich.edu ppCycles->notify(delta); 2407331Sgblack@eecs.umich.edu 2417331Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) { 2427331Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2437331Sgblack@eecs.umich.edu schedule(tickEvent, clockEdge(Cycles(0))); 2447331Sgblack@eecs.umich.edu } 2457331Sgblack@eecs.umich.edu _status = BaseSimpleCPU::Running; 2467331Sgblack@eecs.umich.edu if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 2477331Sgblack@eecs.umich.edu == activeThreads.end()) { 2487331Sgblack@eecs.umich.edu activeThreads.push_back(thread_num); 2497331Sgblack@eecs.umich.edu } 2507331Sgblack@eecs.umich.edu 2517331Sgblack@eecs.umich.edu BaseCPU::activateContext(thread_num); 2527331Sgblack@eecs.umich.edu} 2537331Sgblack@eecs.umich.edu 2547331Sgblack@eecs.umich.edu 2557331Sgblack@eecs.umich.eduvoid 2567331Sgblack@eecs.umich.eduAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2577331Sgblack@eecs.umich.edu{ 2587331Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2597331Sgblack@eecs.umich.edu 2607331Sgblack@eecs.umich.edu assert(thread_num < numThreads); 2617331Sgblack@eecs.umich.edu activeThreads.remove(thread_num); 2627331Sgblack@eecs.umich.edu 2637253Sgblack@eecs.umich.edu if (_status == Idle) 2647253Sgblack@eecs.umich.edu return; 2657253Sgblack@eecs.umich.edu 2667253Sgblack@eecs.umich.edu assert(_status == BaseSimpleCPU::Running); 2677253Sgblack@eecs.umich.edu 2687253Sgblack@eecs.umich.edu threadInfo[thread_num]->notIdleFraction = 0; 2697253Sgblack@eecs.umich.edu 2707253Sgblack@eecs.umich.edu if (activeThreads.empty()) { 2717330Sgblack@eecs.umich.edu _status = Idle; 2727253Sgblack@eecs.umich.edu 2737253Sgblack@eecs.umich.edu if (tickEvent.scheduled()) { 2747253Sgblack@eecs.umich.edu deschedule(tickEvent); 2757253Sgblack@eecs.umich.edu } 2767253Sgblack@eecs.umich.edu } 2777253Sgblack@eecs.umich.edu 2787253Sgblack@eecs.umich.edu BaseCPU::suspendContext(thread_num); 2797253Sgblack@eecs.umich.edu} 2807330Sgblack@eecs.umich.edu 2817330Sgblack@eecs.umich.edu 2827253Sgblack@eecs.umich.eduTick 2837253Sgblack@eecs.umich.eduAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 2847253Sgblack@eecs.umich.edu{ 2857253Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 2867253Sgblack@eecs.umich.edu pkt->cmdString()); 2877253Sgblack@eecs.umich.edu 2887253Sgblack@eecs.umich.edu // X86 ISA: Snooping an invalidation for monitor/mwait 2897232Sgblack@eecs.umich.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 2907225Sgblack@eecs.umich.edu 2917225Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 2927225Sgblack@eecs.umich.edu if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 2937225Sgblack@eecs.umich.edu cpu->wakeup(tid); 2947225Sgblack@eecs.umich.edu } 2957225Sgblack@eecs.umich.edu } 2967330Sgblack@eecs.umich.edu 2977225Sgblack@eecs.umich.edu // if snoop invalidates, release any associated locks 2987225Sgblack@eecs.umich.edu // When run without caches, Invalidation packets will not be received 2997225Sgblack@eecs.umich.edu // hence we must check if the incoming packets are writes and wakeup 3007225Sgblack@eecs.umich.edu // the processor accordingly 3017232Sgblack@eecs.umich.edu if (pkt->isInvalidate() || pkt->isWrite()) { 3027225Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 3037225Sgblack@eecs.umich.edu pkt->getAddr()); 3047330Sgblack@eecs.umich.edu for (auto &t_info : cpu->threadInfo) { 3057225Sgblack@eecs.umich.edu TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 3067225Sgblack@eecs.umich.edu } 3077232Sgblack@eecs.umich.edu } 3087225Sgblack@eecs.umich.edu 3097225Sgblack@eecs.umich.edu return 0; 3107225Sgblack@eecs.umich.edu} 3117225Sgblack@eecs.umich.edu 3127225Sgblack@eecs.umich.eduvoid 3137232Sgblack@eecs.umich.eduAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 3147225Sgblack@eecs.umich.edu{ 3157225Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 3167225Sgblack@eecs.umich.edu pkt->cmdString()); 3177225Sgblack@eecs.umich.edu 3187225Sgblack@eecs.umich.edu // X86 ISA: Snooping an invalidation for monitor/mwait 3197225Sgblack@eecs.umich.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 3207330Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 3217225Sgblack@eecs.umich.edu if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 3227225Sgblack@eecs.umich.edu cpu->wakeup(tid); 3237225Sgblack@eecs.umich.edu } 3247225Sgblack@eecs.umich.edu } 3257225Sgblack@eecs.umich.edu 3267232Sgblack@eecs.umich.edu // if snoop invalidates, release any associated locks 3277225Sgblack@eecs.umich.edu if (pkt->isInvalidate()) { 3287225Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 3297330Sgblack@eecs.umich.edu pkt->getAddr()); 3307225Sgblack@eecs.umich.edu for (auto &t_info : cpu->threadInfo) { 3317225Sgblack@eecs.umich.edu TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 3327225Sgblack@eecs.umich.edu } 3337225Sgblack@eecs.umich.edu } 3347232Sgblack@eecs.umich.edu} 3357225Sgblack@eecs.umich.edu 3367225Sgblack@eecs.umich.eduFault 3377225Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3387225Sgblack@eecs.umich.edu unsigned size, unsigned flags) 339{ 340 SimpleExecContext& t_info = *threadInfo[curThread]; 341 SimpleThread* thread = t_info.thread; 342 343 // use the CPU's statically allocated read request and packet objects 344 Request *req = &data_read_req; 345 346 if (traceData) 347 traceData->setMem(addr, size, flags); 348 349 //The size of the data we're trying to read. 350 int fullSize = size; 351 352 //The address of the second part of this access if it needs to be split 353 //across a cache line boundary. 354 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 355 356 if (secondAddr > addr) 357 size = secondAddr - addr; 358 359 dcache_latency = 0; 360 361 req->taskId(taskId()); 362 while (1) { 363 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 364 365 // translate to physical address 366 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 367 BaseTLB::Read); 368 369 // Now do the access. 370 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 371 Packet pkt(req, Packet::makeReadCmd(req)); 372 pkt.dataStatic(data); 373 374 if (req->isMmappedIpr()) 375 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 376 else { 377 if (fastmem && system->isMemAddr(pkt.getAddr())) 378 system->getPhysMem().access(&pkt); 379 else 380 dcache_latency += dcachePort.sendAtomic(&pkt); 381 } 382 dcache_access = true; 383 384 assert(!pkt.isError()); 385 386 if (req->isLLSC()) { 387 TheISA::handleLockedRead(thread, req); 388 } 389 } 390 391 //If there's a fault, return it 392 if (fault != NoFault) { 393 if (req->isPrefetch()) { 394 return NoFault; 395 } else { 396 return fault; 397 } 398 } 399 400 //If we don't need to access a second cache line, stop now. 401 if (secondAddr <= addr) 402 { 403 if (req->isLockedRMW() && fault == NoFault) { 404 assert(!locked); 405 locked = true; 406 } 407 408 return fault; 409 } 410 411 /* 412 * Set up for accessing the second cache line. 413 */ 414 415 //Move the pointer we're reading into to the correct location. 416 data += size; 417 //Adjust the size to get the remaining bytes. 418 size = addr + fullSize - secondAddr; 419 //And access the right address. 420 addr = secondAddr; 421 } 422} 423 424Fault 425AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) 426{ 427 panic("initiateMemRead() is for timing accesses, and should " 428 "never be called on AtomicSimpleCPU.\n"); 429} 430 431Fault 432AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 433 Addr addr, unsigned flags, uint64_t *res) 434{ 435 SimpleExecContext& t_info = *threadInfo[curThread]; 436 SimpleThread* thread = t_info.thread; 437 static uint8_t zero_array[64] = {}; 438 439 if (data == NULL) { 440 assert(size <= 64); 441 assert(flags & Request::CACHE_BLOCK_ZERO); 442 // This must be a cache block cleaning request 443 data = zero_array; 444 } 445 446 // use the CPU's statically allocated write request and packet objects 447 Request *req = &data_write_req; 448 449 if (traceData) 450 traceData->setMem(addr, size, flags); 451 452 //The size of the data we're trying to read. 453 int fullSize = size; 454 455 //The address of the second part of this access if it needs to be split 456 //across a cache line boundary. 457 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 458 459 if (secondAddr > addr) 460 size = secondAddr - addr; 461 462 dcache_latency = 0; 463 464 req->taskId(taskId()); 465 while (1) { 466 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 467 468 // translate to physical address 469 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 470 471 // Now do the access. 472 if (fault == NoFault) { 473 MemCmd cmd = MemCmd::WriteReq; // default 474 bool do_access = true; // flag to suppress cache access 475 476 if (req->isLLSC()) { 477 cmd = MemCmd::StoreCondReq; 478 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 479 } else if (req->isSwap()) { 480 cmd = MemCmd::SwapReq; 481 if (req->isCondSwap()) { 482 assert(res); 483 req->setExtraData(*res); 484 } 485 } 486 487 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 488 Packet pkt = Packet(req, cmd); 489 pkt.dataStatic(data); 490 491 if (req->isMmappedIpr()) { 492 dcache_latency += 493 TheISA::handleIprWrite(thread->getTC(), &pkt); 494 } else { 495 if (fastmem && system->isMemAddr(pkt.getAddr())) 496 system->getPhysMem().access(&pkt); 497 else 498 dcache_latency += dcachePort.sendAtomic(&pkt); 499 500 // Notify other threads on this CPU of write 501 threadSnoop(&pkt, curThread); 502 } 503 dcache_access = true; 504 assert(!pkt.isError()); 505 506 if (req->isSwap()) { 507 assert(res); 508 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 509 } 510 } 511 512 if (res && !req->isSwap()) { 513 *res = req->getExtraData(); 514 } 515 } 516 517 //If there's a fault or we don't need to access a second cache line, 518 //stop now. 519 if (fault != NoFault || secondAddr <= addr) 520 { 521 if (req->isLockedRMW() && fault == NoFault) { 522 assert(locked); 523 locked = false; 524 } 525 526 527 if (fault != NoFault && req->isPrefetch()) { 528 return NoFault; 529 } else { 530 return fault; 531 } 532 } 533 534 /* 535 * Set up for accessing the second cache line. 536 */ 537 538 //Move the pointer we're reading into to the correct location. 539 data += size; 540 //Adjust the size to get the remaining bytes. 541 size = addr + fullSize - secondAddr; 542 //And access the right address. 543 addr = secondAddr; 544 } 545} 546 547 548void 549AtomicSimpleCPU::tick() 550{ 551 DPRINTF(SimpleCPU, "Tick\n"); 552 553 // Change thread if multi-threaded 554 swapActiveThread(); 555 556 // Set memroy request ids to current thread 557 if (numThreads > 1) { 558 ContextID cid = threadContexts[curThread]->contextId(); 559 560 ifetch_req.setContext(cid); 561 data_read_req.setContext(cid); 562 data_write_req.setContext(cid); 563 } 564 565 SimpleExecContext& t_info = *threadInfo[curThread]; 566 SimpleThread* thread = t_info.thread; 567 568 Tick latency = 0; 569 570 for (int i = 0; i < width || locked; ++i) { 571 numCycles++; 572 ppCycles->notify(1); 573 574 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 575 checkForInterrupts(); 576 checkPcEventQueue(); 577 } 578 579 // We must have just got suspended by a PC event 580 if (_status == Idle) { 581 tryCompleteDrain(); 582 return; 583 } 584 585 Fault fault = NoFault; 586 587 TheISA::PCState pcState = thread->pcState(); 588 589 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 590 !curMacroStaticInst; 591 if (needToFetch) { 592 ifetch_req.taskId(taskId()); 593 setupFetchRequest(&ifetch_req); 594 fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(), 595 BaseTLB::Execute); 596 } 597 598 if (fault == NoFault) { 599 Tick icache_latency = 0; 600 bool icache_access = false; 601 dcache_access = false; // assume no dcache access 602 603 if (needToFetch) { 604 // This is commented out because the decoder would act like 605 // a tiny cache otherwise. It wouldn't be flushed when needed 606 // like the I cache. It should be flushed, and when that works 607 // this code should be uncommented. 608 //Fetch more instruction memory if necessary 609 //if (decoder.needMoreBytes()) 610 //{ 611 icache_access = true; 612 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 613 ifetch_pkt.dataStatic(&inst); 614 615 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 616 system->getPhysMem().access(&ifetch_pkt); 617 else 618 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 619 620 assert(!ifetch_pkt.isError()); 621 622 // ifetch_req is initialized to read the instruction directly 623 // into the CPU object's inst field. 624 //} 625 } 626 627 preExecute(); 628 629 if (curStaticInst) { 630 fault = curStaticInst->execute(&t_info, traceData); 631 632 // keep an instruction count 633 if (fault == NoFault) { 634 countInst(); 635 ppCommit->notify(std::make_pair(thread, curStaticInst)); 636 } 637 else if (traceData && !DTRACE(ExecFaulting)) { 638 delete traceData; 639 traceData = NULL; 640 } 641 642 postExecute(); 643 } 644 645 // @todo remove me after debugging with legion done 646 if (curStaticInst && (!curStaticInst->isMicroop() || 647 curStaticInst->isFirstMicroop())) 648 instCnt++; 649 650 Tick stall_ticks = 0; 651 if (simulate_inst_stalls && icache_access) 652 stall_ticks += icache_latency; 653 654 if (simulate_data_stalls && dcache_access) 655 stall_ticks += dcache_latency; 656 657 if (stall_ticks) { 658 // the atomic cpu does its accounting in ticks, so 659 // keep counting in ticks but round to the clock 660 // period 661 latency += divCeil(stall_ticks, clockPeriod()) * 662 clockPeriod(); 663 } 664 665 } 666 if (fault != NoFault || !t_info.stayAtPC) 667 advancePC(fault); 668 } 669 670 if (tryCompleteDrain()) 671 return; 672 673 // instruction takes at least one cycle 674 if (latency < clockPeriod()) 675 latency = clockPeriod(); 676 677 if (_status != Idle) 678 reschedule(tickEvent, curTick() + latency, true); 679} 680 681void 682AtomicSimpleCPU::regProbePoints() 683{ 684 BaseCPU::regProbePoints(); 685 686 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 687 (getProbeManager(), "Commit"); 688} 689 690void 691AtomicSimpleCPU::printAddr(Addr a) 692{ 693 dcachePort.printAddr(a); 694} 695 696//////////////////////////////////////////////////////////////////////// 697// 698// AtomicSimpleCPU Simulation Object 699// 700AtomicSimpleCPU * 701AtomicSimpleCPUParams::create() 702{ 703 return new AtomicSimpleCPU(this); 704} 705