atomic.cc revision 10913
12623SN/A/* 210596Sgabeblack@google.com * Copyright 2014 Google, Inc. 310030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 48926Sandreas.hansson@arm.com * All rights reserved. 58926Sandreas.hansson@arm.com * 68926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148926Sandreas.hansson@arm.com * 152623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162623SN/A * All rights reserved. 172623SN/A * 182623SN/A * Redistribution and use in source and binary forms, with or without 192623SN/A * modification, are permitted provided that the following conditions are 202623SN/A * met: redistributions of source code must retain the above copyright 212623SN/A * notice, this list of conditions and the following disclaimer; 222623SN/A * redistributions in binary form must reproduce the above copyright 232623SN/A * notice, this list of conditions and the following disclaimer in the 242623SN/A * documentation and/or other materials provided with the distribution; 252623SN/A * neither the name of the copyright holders nor the names of its 262623SN/A * contributors may be used to endorse or promote products derived from 272623SN/A * this software without specific prior written permission. 282623SN/A * 292623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422623SN/A */ 432623SN/A 443170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 458105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 462623SN/A#include "arch/utility.hh" 474040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 489647Sdam.sunwoo@arm.com#include "base/output.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 508229Snate@binkert.org#include "cpu/simple/atomic.hh" 512623SN/A#include "cpu/exetrace.hh" 529443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 538232Snate@binkert.org#include "debug/ExecFaulting.hh" 548232Snate@binkert.org#include "debug/SimpleCPU.hh" 553348Sbinkertn@umich.edu#include "mem/packet.hh" 563348Sbinkertn@umich.edu#include "mem/packet_access.hh" 578926Sandreas.hansson@arm.com#include "mem/physical.hh" 584762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 597678Sgblack@eecs.umich.edu#include "sim/faults.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 618779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 622623SN/A 632623SN/Ausing namespace std; 642623SN/Ausing namespace TheISA; 652623SN/A 662623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 675606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 682623SN/A{ 692623SN/A} 702623SN/A 712623SN/A 722623SN/Avoid 732623SN/AAtomicSimpleCPU::TickEvent::process() 742623SN/A{ 752623SN/A cpu->tick(); 762623SN/A} 772623SN/A 782623SN/Aconst char * 795336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 802623SN/A{ 814873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 822623SN/A} 832623SN/A 842623SN/Avoid 852623SN/AAtomicSimpleCPU::init() 862623SN/A{ 872623SN/A BaseCPU::init(); 888921Sandreas.hansson@arm.com 898921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 908921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 918921Sandreas.hansson@arm.com 929433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 938779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 948779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 958779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 968779Sgblack@eecs.umich.edu // initialize CPU, including PC 978779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 988779Sgblack@eecs.umich.edu } 992623SN/A } 1008706Sandreas.hansson@arm.com 1015714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1025712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1035712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1045712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1052623SN/A} 1062623SN/A 1075529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1086078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1095487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1105487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1119095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1129095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 11310537Sandreas.hansson@arm.com fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 11410537Sandreas.hansson@arm.com ppCommit(nullptr) 1152623SN/A{ 1162623SN/A _status = Idle; 1172623SN/A} 1182623SN/A 1192623SN/A 1202623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1212623SN/A{ 1226775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1236775SBrad.Beckmann@amd.com deschedule(tickEvent); 1246775SBrad.Beckmann@amd.com } 1252623SN/A} 1262623SN/A 12710913Sandreas.sandberg@arm.comDrainState 12810913Sandreas.sandberg@arm.comAtomicSimpleCPU::drain() 1292623SN/A{ 1309448SAndreas.Sandberg@ARM.com if (switchedOut()) 13110913Sandreas.sandberg@arm.com return DrainState::Drained; 1322623SN/A 1339443SAndreas.Sandberg@ARM.com if (!isDrained()) { 1349443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 13510913Sandreas.sandberg@arm.com return DrainState::Draining; 1369443SAndreas.Sandberg@ARM.com } else { 1379443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1389443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1392915Sktlim@umich.edu 1409443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 14110913Sandreas.sandberg@arm.com return DrainState::Drained; 1429443SAndreas.Sandberg@ARM.com } 1439342SAndreas.Sandberg@arm.com} 1449342SAndreas.Sandberg@arm.com 1452915Sktlim@umich.eduvoid 1469342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1472915Sktlim@umich.edu{ 1489448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1499448SAndreas.Sandberg@ARM.com if (switchedOut()) 1505220Ssaidi@eecs.umich.edu return; 1515220Ssaidi@eecs.umich.edu 1524940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1539523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1543324Shsul@eecs.umich.edu 1559448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1569448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1579448SAndreas.Sandberg@ARM.com fatal("The atomic CPU only supports one thread.\n"); 1589448SAndreas.Sandberg@ARM.com 1599448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1609443SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 1619448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1629837Slena@cs.wisc,edu notIdleFraction = 1; 1639448SAndreas.Sandberg@ARM.com } else { 1649448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1659837Slena@cs.wisc,edu notIdleFraction = 0; 1669448SAndreas.Sandberg@ARM.com } 1672623SN/A} 1682623SN/A 1699443SAndreas.Sandberg@ARM.combool 1709443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1719443SAndreas.Sandberg@ARM.com{ 17210913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining) 1739443SAndreas.Sandberg@ARM.com return false; 1749443SAndreas.Sandberg@ARM.com 1759443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1769443SAndreas.Sandberg@ARM.com if (!isDrained()) 1779443SAndreas.Sandberg@ARM.com return false; 1789443SAndreas.Sandberg@ARM.com 1799443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 18010913Sandreas.sandberg@arm.com signalDrainDone(); 1819443SAndreas.Sandberg@ARM.com 1829443SAndreas.Sandberg@ARM.com return true; 1839443SAndreas.Sandberg@ARM.com} 1849443SAndreas.Sandberg@ARM.com 1859443SAndreas.Sandberg@ARM.com 1862623SN/Avoid 1872798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1882623SN/A{ 1899429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1909429SAndreas.Sandberg@ARM.com 1919443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1929342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1939443SAndreas.Sandberg@ARM.com assert(isDrained()); 1942623SN/A} 1952623SN/A 1962623SN/A 1972623SN/Avoid 1982623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1992623SN/A{ 2009429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2012623SN/A 2029443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2032623SN/A assert(!tickEvent.scheduled()); 2042623SN/A 2055712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2065712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2075712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2082623SN/A} 2092623SN/A 2109523SAndreas.Sandberg@ARM.comvoid 2119523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2129523SAndreas.Sandberg@ARM.com{ 2139524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2149523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2159523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2169523SAndreas.Sandberg@ARM.com } 2179523SAndreas.Sandberg@ARM.com} 2182623SN/A 2192623SN/Avoid 22010407Smitch.hayenga@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num) 2212623SN/A{ 22210407Smitch.hayenga@arm.com DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 2234940Snate@binkert.org 2242623SN/A assert(thread_num == 0); 2252683Sktlim@umich.edu assert(thread); 2262623SN/A 2272623SN/A assert(_status == Idle); 2282623SN/A assert(!tickEvent.scheduled()); 2292623SN/A 2309837Slena@cs.wisc,edu notIdleFraction = 1; 23110464SAndreas.Sandberg@ARM.com Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend); 23210464SAndreas.Sandberg@ARM.com numCycles += delta; 23310464SAndreas.Sandberg@ARM.com ppCycles->notify(delta); 2343686Sktlim@umich.edu 2353430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 23610407Smitch.hayenga@arm.com schedule(tickEvent, clockEdge(Cycles(0))); 2379342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2382623SN/A} 2392623SN/A 2402623SN/A 2412623SN/Avoid 2428737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2432623SN/A{ 2444940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2454940Snate@binkert.org 2462623SN/A assert(thread_num == 0); 2472683Sktlim@umich.edu assert(thread); 2482623SN/A 2496043Sgblack@eecs.umich.edu if (_status == Idle) 2506043Sgblack@eecs.umich.edu return; 2516043Sgblack@eecs.umich.edu 2529342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2532626SN/A 2542626SN/A // tick event may not be scheduled if this gets called from inside 2552626SN/A // an instruction's execution, e.g. "quiesce" 2562626SN/A if (tickEvent.scheduled()) 2575606Snate@binkert.org deschedule(tickEvent); 2582623SN/A 2599837Slena@cs.wisc,edu notIdleFraction = 0; 2602623SN/A _status = Idle; 2612623SN/A} 2622623SN/A 2632623SN/A 26410030SAli.Saidi@ARM.comTick 26510030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 26610030SAli.Saidi@ARM.com{ 26710030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 26810030SAli.Saidi@ARM.com pkt->cmdString()); 26910030SAli.Saidi@ARM.com 27010529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 27110529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 27210529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 27310529Smorr@cs.wisc.edu cpu->wakeup(); 27410529Smorr@cs.wisc.edu } 27510529Smorr@cs.wisc.edu 27610030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 27710030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 27810030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 27910030SAli.Saidi@ARM.com pkt->getAddr()); 28010030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 28110030SAli.Saidi@ARM.com } 28210030SAli.Saidi@ARM.com 28310030SAli.Saidi@ARM.com return 0; 28410030SAli.Saidi@ARM.com} 28510030SAli.Saidi@ARM.com 28610030SAli.Saidi@ARM.comvoid 28710030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 28810030SAli.Saidi@ARM.com{ 28910030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 29010030SAli.Saidi@ARM.com pkt->cmdString()); 29110030SAli.Saidi@ARM.com 29210529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 29310529Smorr@cs.wisc.edu AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 29410529Smorr@cs.wisc.edu if(cpu->getAddrMonitor()->doMonitor(pkt)) { 29510529Smorr@cs.wisc.edu cpu->wakeup(); 29610529Smorr@cs.wisc.edu } 29710529Smorr@cs.wisc.edu 29810030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29910030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 30010030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 30110030SAli.Saidi@ARM.com pkt->getAddr()); 30210030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 30310030SAli.Saidi@ARM.com } 30410030SAli.Saidi@ARM.com} 30510030SAli.Saidi@ARM.com 3062623SN/AFault 3078444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 3088444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3092623SN/A{ 3103169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3114870Sstever@eecs.umich.edu Request *req = &data_read_req; 3122623SN/A 31310665SAli.Saidi@ARM.com if (traceData) 31410665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 3152623SN/A 3164999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3177520Sgblack@eecs.umich.edu int fullSize = size; 3182623SN/A 3194999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3204999Sgblack@eecs.umich.edu //across a cache line boundary. 3219814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3224999Sgblack@eecs.umich.edu 3237520Sgblack@eecs.umich.edu if (secondAddr > addr) 3247520Sgblack@eecs.umich.edu size = secondAddr - addr; 3254999Sgblack@eecs.umich.edu 3264999Sgblack@eecs.umich.edu dcache_latency = 0; 3274999Sgblack@eecs.umich.edu 32810024Sdam.sunwoo@arm.com req->taskId(taskId()); 3297520Sgblack@eecs.umich.edu while (1) { 3308832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3314999Sgblack@eecs.umich.edu 3324999Sgblack@eecs.umich.edu // translate to physical address 3336023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3344999Sgblack@eecs.umich.edu 3354999Sgblack@eecs.umich.edu // Now do the access. 3366623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 33710739Ssteve.reinhardt@amd.com Packet pkt(req, Packet::makeReadCmd(req)); 3387520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3394999Sgblack@eecs.umich.edu 3408105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3414999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3424999Sgblack@eecs.umich.edu else { 3438931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3448931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3454999Sgblack@eecs.umich.edu else 3464999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3474999Sgblack@eecs.umich.edu } 3484999Sgblack@eecs.umich.edu dcache_access = true; 3495012Sgblack@eecs.umich.edu 3504999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3514999Sgblack@eecs.umich.edu 3526102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3534999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3544999Sgblack@eecs.umich.edu } 3554968Sacolyte@umich.edu } 3564986Ssaidi@eecs.umich.edu 3574999Sgblack@eecs.umich.edu //If there's a fault, return it 3586739Sgblack@eecs.umich.edu if (fault != NoFault) { 3596739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3606739Sgblack@eecs.umich.edu return NoFault; 3616739Sgblack@eecs.umich.edu } else { 3626739Sgblack@eecs.umich.edu return fault; 3636739Sgblack@eecs.umich.edu } 3646739Sgblack@eecs.umich.edu } 3656739Sgblack@eecs.umich.edu 3664999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3674999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3684999Sgblack@eecs.umich.edu { 36910760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 3706078Sgblack@eecs.umich.edu assert(!locked); 3716078Sgblack@eecs.umich.edu locked = true; 3726078Sgblack@eecs.umich.edu } 3734999Sgblack@eecs.umich.edu return fault; 3744968Sacolyte@umich.edu } 3753170Sstever@eecs.umich.edu 3764999Sgblack@eecs.umich.edu /* 3774999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3784999Sgblack@eecs.umich.edu */ 3794999Sgblack@eecs.umich.edu 3804999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3817520Sgblack@eecs.umich.edu data += size; 3824999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3837520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3844999Sgblack@eecs.umich.edu //And access the right address. 3854999Sgblack@eecs.umich.edu addr = secondAddr; 3862623SN/A } 3872623SN/A} 3882623SN/A 3897520Sgblack@eecs.umich.edu 3902623SN/AFault 3918444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3928444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3932623SN/A{ 39410031SAli.Saidi@ARM.com 39510031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 39610031SAli.Saidi@ARM.com 39710031SAli.Saidi@ARM.com if (data == NULL) { 39810031SAli.Saidi@ARM.com assert(size <= 64); 39910031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 40010031SAli.Saidi@ARM.com // This must be a cache block cleaning request 40110031SAli.Saidi@ARM.com data = zero_array; 40210031SAli.Saidi@ARM.com } 40310031SAli.Saidi@ARM.com 4043169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 4054870Sstever@eecs.umich.edu Request *req = &data_write_req; 4062623SN/A 40710665SAli.Saidi@ARM.com if (traceData) 40810665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 4092623SN/A 4104999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4117520Sgblack@eecs.umich.edu int fullSize = size; 4122623SN/A 4134999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4144999Sgblack@eecs.umich.edu //across a cache line boundary. 4159814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4164999Sgblack@eecs.umich.edu 4174999Sgblack@eecs.umich.edu if(secondAddr > addr) 4187520Sgblack@eecs.umich.edu size = secondAddr - addr; 4194999Sgblack@eecs.umich.edu 4204999Sgblack@eecs.umich.edu dcache_latency = 0; 4214999Sgblack@eecs.umich.edu 42210024Sdam.sunwoo@arm.com req->taskId(taskId()); 4234999Sgblack@eecs.umich.edu while(1) { 4248832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4254999Sgblack@eecs.umich.edu 4264999Sgblack@eecs.umich.edu // translate to physical address 4276023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4284999Sgblack@eecs.umich.edu 4294999Sgblack@eecs.umich.edu // Now do the access. 4304999Sgblack@eecs.umich.edu if (fault == NoFault) { 4314999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4324999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4334999Sgblack@eecs.umich.edu 4346102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4354999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 43610030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4374999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4384999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4394999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4404999Sgblack@eecs.umich.edu assert(res); 4414999Sgblack@eecs.umich.edu req->setExtraData(*res); 4424999Sgblack@eecs.umich.edu } 4434999Sgblack@eecs.umich.edu } 4444999Sgblack@eecs.umich.edu 4456623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4468949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4477520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4484999Sgblack@eecs.umich.edu 4498105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4504999Sgblack@eecs.umich.edu dcache_latency += 4514999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4524999Sgblack@eecs.umich.edu } else { 4538931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4548931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4554999Sgblack@eecs.umich.edu else 4564999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4574999Sgblack@eecs.umich.edu } 4584999Sgblack@eecs.umich.edu dcache_access = true; 4594999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4604999Sgblack@eecs.umich.edu 4614999Sgblack@eecs.umich.edu if (req->isSwap()) { 4624999Sgblack@eecs.umich.edu assert(res); 46310563Sandreas.hansson@arm.com memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 4644999Sgblack@eecs.umich.edu } 4654999Sgblack@eecs.umich.edu } 4664999Sgblack@eecs.umich.edu 4674999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4684999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4694878Sstever@eecs.umich.edu } 4704040Ssaidi@eecs.umich.edu } 4714040Ssaidi@eecs.umich.edu 4724999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4734999Sgblack@eecs.umich.edu //stop now. 4744999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4754999Sgblack@eecs.umich.edu { 47610760Ssteve.reinhardt@amd.com if (req->isLockedRMW() && fault == NoFault) { 4776078Sgblack@eecs.umich.edu assert(locked); 4786078Sgblack@eecs.umich.edu locked = false; 4796078Sgblack@eecs.umich.edu } 4806739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4816739Sgblack@eecs.umich.edu return NoFault; 4826739Sgblack@eecs.umich.edu } else { 4836739Sgblack@eecs.umich.edu return fault; 4846739Sgblack@eecs.umich.edu } 4853170Sstever@eecs.umich.edu } 4863170Sstever@eecs.umich.edu 4874999Sgblack@eecs.umich.edu /* 4884999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4894999Sgblack@eecs.umich.edu */ 4904999Sgblack@eecs.umich.edu 4914999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4927520Sgblack@eecs.umich.edu data += size; 4934999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4947520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4954999Sgblack@eecs.umich.edu //And access the right address. 4964999Sgblack@eecs.umich.edu addr = secondAddr; 4972623SN/A } 4982623SN/A} 4992623SN/A 5002623SN/A 5012623SN/Avoid 5022623SN/AAtomicSimpleCPU::tick() 5032623SN/A{ 5044940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 5054940Snate@binkert.org 5065487Snate@binkert.org Tick latency = 0; 5072623SN/A 5086078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5092623SN/A numCycles++; 51010464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5112623SN/A 51210596Sgabeblack@google.com if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 5133387Sgblack@eecs.umich.edu checkForInterrupts(); 51410596Sgabeblack@google.com checkPcEventQueue(); 51510596Sgabeblack@google.com } 5162626SN/A 5178143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5189443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5199443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5208143SAli.Saidi@ARM.com return; 5219443SAndreas.Sandberg@ARM.com } 5225348Ssaidi@eecs.umich.edu 5235669Sgblack@eecs.umich.edu Fault fault = NoFault; 5245669Sgblack@eecs.umich.edu 5257720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5267720Sgblack@eecs.umich.edu 5277720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5287720Sgblack@eecs.umich.edu !curMacroStaticInst; 5297720Sgblack@eecs.umich.edu if (needToFetch) { 53010024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5315894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 5326023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 5336023Snate@binkert.org BaseTLB::Execute); 5345894Sgblack@eecs.umich.edu } 5352623SN/A 5362623SN/A if (fault == NoFault) { 5374182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5384182Sgblack@eecs.umich.edu bool icache_access = false; 5394182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5402662Sstever@eecs.umich.edu 5417720Sgblack@eecs.umich.edu if (needToFetch) { 5429023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5435694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5445694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5455694Sgblack@eecs.umich.edu // this code should be uncommented. 5465669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5479023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 5485669Sgblack@eecs.umich.edu //{ 5495669Sgblack@eecs.umich.edu icache_access = true; 5508949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 5515669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5522623SN/A 5538931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5548931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5555669Sgblack@eecs.umich.edu else 5565669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5574968Sacolyte@umich.edu 5585669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5594968Sacolyte@umich.edu 5605669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5615669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5625669Sgblack@eecs.umich.edu //} 5635669Sgblack@eecs.umich.edu } 5644182Sgblack@eecs.umich.edu 5652623SN/A preExecute(); 5663814Ssaidi@eecs.umich.edu 5675001Sgblack@eecs.umich.edu if (curStaticInst) { 5684182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5694998Sgblack@eecs.umich.edu 5704998Sgblack@eecs.umich.edu // keep an instruction count 57110381Sdam.sunwoo@arm.com if (fault == NoFault) { 5724998Sgblack@eecs.umich.edu countInst(); 57310651Snikos.nikoleris@gmail.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 57410381Sdam.sunwoo@arm.com } 5757655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5765001Sgblack@eecs.umich.edu delete traceData; 5775001Sgblack@eecs.umich.edu traceData = NULL; 5785001Sgblack@eecs.umich.edu } 5794998Sgblack@eecs.umich.edu 5804182Sgblack@eecs.umich.edu postExecute(); 5814182Sgblack@eecs.umich.edu } 5822623SN/A 5833814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5844539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5854539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5863814Ssaidi@eecs.umich.edu instCnt++; 5873814Ssaidi@eecs.umich.edu 5885487Snate@binkert.org Tick stall_ticks = 0; 5895487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5905487Snate@binkert.org stall_ticks += icache_latency; 5915487Snate@binkert.org 5925487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5935487Snate@binkert.org stall_ticks += dcache_latency; 5945487Snate@binkert.org 5955487Snate@binkert.org if (stall_ticks) { 5969180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 5979180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 5989180Sandreas.hansson@arm.com // period 5999180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 6009180Sandreas.hansson@arm.com clockPeriod(); 6012623SN/A } 6022623SN/A 6032623SN/A } 6044377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 6054182Sgblack@eecs.umich.edu advancePC(fault); 6062623SN/A } 6072623SN/A 6089443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6099443SAndreas.Sandberg@ARM.com return; 6109443SAndreas.Sandberg@ARM.com 6115487Snate@binkert.org // instruction takes at least one cycle 6129179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6139179Sandreas.hansson@arm.com latency = clockPeriod(); 6145487Snate@binkert.org 6152626SN/A if (_status != Idle) 6167823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 6172623SN/A} 6182623SN/A 61910381Sdam.sunwoo@arm.comvoid 62010381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 62110381Sdam.sunwoo@arm.com{ 62210464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 62310464SAndreas.Sandberg@ARM.com 62410381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 62510381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 62610381Sdam.sunwoo@arm.com} 6272623SN/A 6285315Sstever@gmail.comvoid 6295315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6305315Sstever@gmail.com{ 6315315Sstever@gmail.com dcachePort.printAddr(a); 6325315Sstever@gmail.com} 6335315Sstever@gmail.com 6342623SN/A//////////////////////////////////////////////////////////////////////// 6352623SN/A// 6362623SN/A// AtomicSimpleCPU Simulation Object 6372623SN/A// 6384762Snate@binkert.orgAtomicSimpleCPU * 6394762Snate@binkert.orgAtomicSimpleCPUParams::create() 6402623SN/A{ 6415529Snate@binkert.org numThreads = 1; 6428779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 6434762Snate@binkert.org panic("only one workload allowed"); 6445529Snate@binkert.org return new AtomicSimpleCPU(this); 6452623SN/A} 646