atomic.cc revision 10381
12623SN/A/* 210030SAli.Saidi@ARM.com * Copyright (c) 2012-2013 ARM Limited 38926Sandreas.hansson@arm.com * All rights reserved. 48926Sandreas.hansson@arm.com * 58926Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68926Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78926Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88926Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98926Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108926Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118926Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128926Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138926Sandreas.hansson@arm.com * 142623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272623SN/A * 282623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412623SN/A */ 422623SN/A 433170Sstever@eecs.umich.edu#include "arch/locked_mem.hh" 448105Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 452623SN/A#include "arch/utility.hh" 464040Ssaidi@eecs.umich.edu#include "base/bigint.hh" 479647Sdam.sunwoo@arm.com#include "base/output.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498229Snate@binkert.org#include "cpu/simple/atomic.hh" 502623SN/A#include "cpu/exetrace.hh" 519443SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 528232Snate@binkert.org#include "debug/ExecFaulting.hh" 538232Snate@binkert.org#include "debug/SimpleCPU.hh" 543348Sbinkertn@umich.edu#include "mem/packet.hh" 553348Sbinkertn@umich.edu#include "mem/packet_access.hh" 568926Sandreas.hansson@arm.com#include "mem/physical.hh" 574762Snate@binkert.org#include "params/AtomicSimpleCPU.hh" 587678Sgblack@eecs.umich.edu#include "sim/faults.hh" 592901Ssaidi@eecs.umich.edu#include "sim/system.hh" 608779Sgblack@eecs.umich.edu#include "sim/full_system.hh" 612623SN/A 622623SN/Ausing namespace std; 632623SN/Ausing namespace TheISA; 642623SN/A 652623SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 665606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 672623SN/A{ 682623SN/A} 692623SN/A 702623SN/A 712623SN/Avoid 722623SN/AAtomicSimpleCPU::TickEvent::process() 732623SN/A{ 742623SN/A cpu->tick(); 752623SN/A} 762623SN/A 772623SN/Aconst char * 785336Shines@cs.fsu.eduAtomicSimpleCPU::TickEvent::description() const 792623SN/A{ 804873Sstever@eecs.umich.edu return "AtomicSimpleCPU tick"; 812623SN/A} 822623SN/A 832623SN/Avoid 842623SN/AAtomicSimpleCPU::init() 852623SN/A{ 862623SN/A BaseCPU::init(); 878921Sandreas.hansson@arm.com 888921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 898921Sandreas.hansson@arm.com tcBase()->initMemProxies(tcBase()); 908921Sandreas.hansson@arm.com 919433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 928779Sgblack@eecs.umich.edu ThreadID size = threadContexts.size(); 938779Sgblack@eecs.umich.edu for (ThreadID i = 0; i < size; ++i) { 948779Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 958779Sgblack@eecs.umich.edu // initialize CPU, including PC 968779Sgblack@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 978779Sgblack@eecs.umich.edu } 982623SN/A } 998706Sandreas.hansson@arm.com 1005714Shsul@eecs.umich.edu // Atomic doesn't do MT right now, so contextId == threadId 1015712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 1025712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1035712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 1042623SN/A} 1052623SN/A 1065529Snate@binkert.orgAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1076078Sgblack@eecs.umich.edu : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 1085487Snate@binkert.org simulate_data_stalls(p->simulate_data_stalls), 1095487Snate@binkert.org simulate_inst_stalls(p->simulate_inst_stalls), 1109443SAndreas.Sandberg@ARM.com drain_manager(NULL), 1119095Sandreas.hansson@arm.com icachePort(name() + ".icache_port", this), 1129095Sandreas.hansson@arm.com dcachePort(name() + ".dcache_port", this), 11310381Sdam.sunwoo@arm.com fastmem(p->fastmem) 1142623SN/A{ 1152623SN/A _status = Idle; 1162623SN/A} 1172623SN/A 1182623SN/A 1192623SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 1202623SN/A{ 1216775SBrad.Beckmann@amd.com if (tickEvent.scheduled()) { 1226775SBrad.Beckmann@amd.com deschedule(tickEvent); 1236775SBrad.Beckmann@amd.com } 1242623SN/A} 1252623SN/A 1269443SAndreas.Sandberg@ARM.comunsigned int 1279443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::drain(DrainManager *dm) 1282623SN/A{ 1299443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1309448SAndreas.Sandberg@ARM.com if (switchedOut()) 1319443SAndreas.Sandberg@ARM.com return 0; 1322623SN/A 1339443SAndreas.Sandberg@ARM.com if (!isDrained()) { 1349443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 1359443SAndreas.Sandberg@ARM.com drain_manager = dm; 1369443SAndreas.Sandberg@ARM.com return 1; 1379443SAndreas.Sandberg@ARM.com } else { 1389443SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 1399443SAndreas.Sandberg@ARM.com deschedule(tickEvent); 1402915Sktlim@umich.edu 1419443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 1429443SAndreas.Sandberg@ARM.com return 0; 1439443SAndreas.Sandberg@ARM.com } 1449342SAndreas.Sandberg@arm.com} 1459342SAndreas.Sandberg@arm.com 1462915Sktlim@umich.eduvoid 1479342SAndreas.Sandberg@arm.comAtomicSimpleCPU::drainResume() 1482915Sktlim@umich.edu{ 1499448SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1509443SAndreas.Sandberg@ARM.com assert(!drain_manager); 1519448SAndreas.Sandberg@ARM.com if (switchedOut()) 1525220Ssaidi@eecs.umich.edu return; 1535220Ssaidi@eecs.umich.edu 1544940Snate@binkert.org DPRINTF(SimpleCPU, "Resume\n"); 1559523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 1563324Shsul@eecs.umich.edu 1579448SAndreas.Sandberg@ARM.com assert(!threadContexts.empty()); 1589448SAndreas.Sandberg@ARM.com if (threadContexts.size() > 1) 1599448SAndreas.Sandberg@ARM.com fatal("The atomic CPU only supports one thread.\n"); 1609448SAndreas.Sandberg@ARM.com 1619448SAndreas.Sandberg@ARM.com if (thread->status() == ThreadContext::Active) { 1629443SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 1639448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Running; 1649837Slena@cs.wisc,edu notIdleFraction = 1; 1659448SAndreas.Sandberg@ARM.com } else { 1669448SAndreas.Sandberg@ARM.com _status = BaseSimpleCPU::Idle; 1679837Slena@cs.wisc,edu notIdleFraction = 0; 1689448SAndreas.Sandberg@ARM.com } 1699443SAndreas.Sandberg@ARM.com 1707897Shestness@cs.utexas.edu system->totalNumInsts = 0; 1712623SN/A} 1722623SN/A 1739443SAndreas.Sandberg@ARM.combool 1749443SAndreas.Sandberg@ARM.comAtomicSimpleCPU::tryCompleteDrain() 1759443SAndreas.Sandberg@ARM.com{ 1769443SAndreas.Sandberg@ARM.com if (!drain_manager) 1779443SAndreas.Sandberg@ARM.com return false; 1789443SAndreas.Sandberg@ARM.com 1799443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 1809443SAndreas.Sandberg@ARM.com if (!isDrained()) 1819443SAndreas.Sandberg@ARM.com return false; 1829443SAndreas.Sandberg@ARM.com 1839443SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1849443SAndreas.Sandberg@ARM.com drain_manager->signalDrainDone(); 1859443SAndreas.Sandberg@ARM.com drain_manager = NULL; 1869443SAndreas.Sandberg@ARM.com 1879443SAndreas.Sandberg@ARM.com return true; 1889443SAndreas.Sandberg@ARM.com} 1899443SAndreas.Sandberg@ARM.com 1909443SAndreas.Sandberg@ARM.com 1912623SN/Avoid 1922798Sktlim@umich.eduAtomicSimpleCPU::switchOut() 1932623SN/A{ 1949429SAndreas.Sandberg@ARM.com BaseSimpleCPU::switchOut(); 1959429SAndreas.Sandberg@ARM.com 1969443SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 1979342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running || _status == Idle); 1989443SAndreas.Sandberg@ARM.com assert(isDrained()); 1992623SN/A} 2002623SN/A 2012623SN/A 2022623SN/Avoid 2032623SN/AAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2042623SN/A{ 2059429SAndreas.Sandberg@ARM.com BaseSimpleCPU::takeOverFrom(oldCPU); 2062623SN/A 2079443SAndreas.Sandberg@ARM.com // The tick event should have been descheduled by drain() 2082623SN/A assert(!tickEvent.scheduled()); 2092623SN/A 2105712Shsul@eecs.umich.edu ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 2115712Shsul@eecs.umich.edu data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2125712Shsul@eecs.umich.edu data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2132623SN/A} 2142623SN/A 2159523SAndreas.Sandberg@ARM.comvoid 2169523SAndreas.Sandberg@ARM.comAtomicSimpleCPU::verifyMemoryMode() const 2179523SAndreas.Sandberg@ARM.com{ 2189524SAndreas.Sandberg@ARM.com if (!system->isAtomicMode()) { 2199523SAndreas.Sandberg@ARM.com fatal("The atomic CPU requires the memory system to be in " 2209523SAndreas.Sandberg@ARM.com "'atomic' mode.\n"); 2219523SAndreas.Sandberg@ARM.com } 2229523SAndreas.Sandberg@ARM.com} 2232623SN/A 2242623SN/Avoid 2259180Sandreas.hansson@arm.comAtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) 2262623SN/A{ 2274940Snate@binkert.org DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 2284940Snate@binkert.org 2292623SN/A assert(thread_num == 0); 2302683Sktlim@umich.edu assert(thread); 2312623SN/A 2322623SN/A assert(_status == Idle); 2332623SN/A assert(!tickEvent.scheduled()); 2342623SN/A 2359837Slena@cs.wisc,edu notIdleFraction = 1; 2369180Sandreas.hansson@arm.com numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend); 2373686Sktlim@umich.edu 2383430Sgblack@eecs.umich.edu //Make sure ticks are still on multiples of cycles 2399179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2409342SAndreas.Sandberg@arm.com _status = BaseSimpleCPU::Running; 2412623SN/A} 2422623SN/A 2432623SN/A 2442623SN/Avoid 2458737Skoansin.tan@gmail.comAtomicSimpleCPU::suspendContext(ThreadID thread_num) 2462623SN/A{ 2474940Snate@binkert.org DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 2484940Snate@binkert.org 2492623SN/A assert(thread_num == 0); 2502683Sktlim@umich.edu assert(thread); 2512623SN/A 2526043Sgblack@eecs.umich.edu if (_status == Idle) 2536043Sgblack@eecs.umich.edu return; 2546043Sgblack@eecs.umich.edu 2559342SAndreas.Sandberg@arm.com assert(_status == BaseSimpleCPU::Running); 2562626SN/A 2572626SN/A // tick event may not be scheduled if this gets called from inside 2582626SN/A // an instruction's execution, e.g. "quiesce" 2592626SN/A if (tickEvent.scheduled()) 2605606Snate@binkert.org deschedule(tickEvent); 2612623SN/A 2629837Slena@cs.wisc,edu notIdleFraction = 0; 2632623SN/A _status = Idle; 2642623SN/A} 2652623SN/A 2662623SN/A 26710030SAli.Saidi@ARM.comTick 26810030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 26910030SAli.Saidi@ARM.com{ 27010030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 27110030SAli.Saidi@ARM.com pkt->cmdString()); 27210030SAli.Saidi@ARM.com 27310030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 27410030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 27510030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 27610030SAli.Saidi@ARM.com pkt->getAddr()); 27710030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 27810030SAli.Saidi@ARM.com } 27910030SAli.Saidi@ARM.com 28010030SAli.Saidi@ARM.com return 0; 28110030SAli.Saidi@ARM.com} 28210030SAli.Saidi@ARM.com 28310030SAli.Saidi@ARM.comvoid 28410030SAli.Saidi@ARM.comAtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 28510030SAli.Saidi@ARM.com{ 28610030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 28710030SAli.Saidi@ARM.com pkt->cmdString()); 28810030SAli.Saidi@ARM.com 28910030SAli.Saidi@ARM.com // if snoop invalidates, release any associated locks 29010030SAli.Saidi@ARM.com if (pkt->isInvalidate()) { 29110030SAli.Saidi@ARM.com DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 29210030SAli.Saidi@ARM.com pkt->getAddr()); 29310030SAli.Saidi@ARM.com TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 29410030SAli.Saidi@ARM.com } 29510030SAli.Saidi@ARM.com} 29610030SAli.Saidi@ARM.com 2972623SN/AFault 2988444Sgblack@eecs.umich.eduAtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 2998444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 3002623SN/A{ 3013169Sstever@eecs.umich.edu // use the CPU's statically allocated read request and packet objects 3024870Sstever@eecs.umich.edu Request *req = &data_read_req; 3032623SN/A 3042623SN/A if (traceData) { 3052623SN/A traceData->setAddr(addr); 3062623SN/A } 3072623SN/A 3084999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 3097520Sgblack@eecs.umich.edu int fullSize = size; 3102623SN/A 3114999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 3124999Sgblack@eecs.umich.edu //across a cache line boundary. 3139814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 3144999Sgblack@eecs.umich.edu 3157520Sgblack@eecs.umich.edu if (secondAddr > addr) 3167520Sgblack@eecs.umich.edu size = secondAddr - addr; 3174999Sgblack@eecs.umich.edu 3184999Sgblack@eecs.umich.edu dcache_latency = 0; 3194999Sgblack@eecs.umich.edu 32010024Sdam.sunwoo@arm.com req->taskId(taskId()); 3217520Sgblack@eecs.umich.edu while (1) { 3228832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 3234999Sgblack@eecs.umich.edu 3244999Sgblack@eecs.umich.edu // translate to physical address 3256023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 3264999Sgblack@eecs.umich.edu 3274999Sgblack@eecs.umich.edu // Now do the access. 3286623Sgblack@eecs.umich.edu if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 32910342SCurtis.Dunham@arm.com Packet pkt(req, MemCmd::ReadReq); 33010342SCurtis.Dunham@arm.com pkt.refineCommand(); 3317520Sgblack@eecs.umich.edu pkt.dataStatic(data); 3324999Sgblack@eecs.umich.edu 3338105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) 3344999Sgblack@eecs.umich.edu dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 3354999Sgblack@eecs.umich.edu else { 3368931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 3378931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 3384999Sgblack@eecs.umich.edu else 3394999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 3404999Sgblack@eecs.umich.edu } 3414999Sgblack@eecs.umich.edu dcache_access = true; 3425012Sgblack@eecs.umich.edu 3434999Sgblack@eecs.umich.edu assert(!pkt.isError()); 3444999Sgblack@eecs.umich.edu 3456102Sgblack@eecs.umich.edu if (req->isLLSC()) { 3464999Sgblack@eecs.umich.edu TheISA::handleLockedRead(thread, req); 3474999Sgblack@eecs.umich.edu } 3484968Sacolyte@umich.edu } 3494986Ssaidi@eecs.umich.edu 3504999Sgblack@eecs.umich.edu //If there's a fault, return it 3516739Sgblack@eecs.umich.edu if (fault != NoFault) { 3526739Sgblack@eecs.umich.edu if (req->isPrefetch()) { 3536739Sgblack@eecs.umich.edu return NoFault; 3546739Sgblack@eecs.umich.edu } else { 3556739Sgblack@eecs.umich.edu return fault; 3566739Sgblack@eecs.umich.edu } 3576739Sgblack@eecs.umich.edu } 3586739Sgblack@eecs.umich.edu 3594999Sgblack@eecs.umich.edu //If we don't need to access a second cache line, stop now. 3604999Sgblack@eecs.umich.edu if (secondAddr <= addr) 3614999Sgblack@eecs.umich.edu { 3626078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 3636078Sgblack@eecs.umich.edu assert(!locked); 3646078Sgblack@eecs.umich.edu locked = true; 3656078Sgblack@eecs.umich.edu } 3664999Sgblack@eecs.umich.edu return fault; 3674968Sacolyte@umich.edu } 3683170Sstever@eecs.umich.edu 3694999Sgblack@eecs.umich.edu /* 3704999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 3714999Sgblack@eecs.umich.edu */ 3724999Sgblack@eecs.umich.edu 3734999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 3747520Sgblack@eecs.umich.edu data += size; 3754999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 3767520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 3774999Sgblack@eecs.umich.edu //And access the right address. 3784999Sgblack@eecs.umich.edu addr = secondAddr; 3792623SN/A } 3802623SN/A} 3812623SN/A 3827520Sgblack@eecs.umich.edu 3832623SN/AFault 3848444Sgblack@eecs.umich.eduAtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 3858444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 3862623SN/A{ 38710031SAli.Saidi@ARM.com 38810031SAli.Saidi@ARM.com static uint8_t zero_array[64] = {}; 38910031SAli.Saidi@ARM.com 39010031SAli.Saidi@ARM.com if (data == NULL) { 39110031SAli.Saidi@ARM.com assert(size <= 64); 39210031SAli.Saidi@ARM.com assert(flags & Request::CACHE_BLOCK_ZERO); 39310031SAli.Saidi@ARM.com // This must be a cache block cleaning request 39410031SAli.Saidi@ARM.com data = zero_array; 39510031SAli.Saidi@ARM.com } 39610031SAli.Saidi@ARM.com 3973169Sstever@eecs.umich.edu // use the CPU's statically allocated write request and packet objects 3984870Sstever@eecs.umich.edu Request *req = &data_write_req; 3992623SN/A 4002623SN/A if (traceData) { 4012623SN/A traceData->setAddr(addr); 4022623SN/A } 4032623SN/A 4044999Sgblack@eecs.umich.edu //The size of the data we're trying to read. 4057520Sgblack@eecs.umich.edu int fullSize = size; 4062623SN/A 4074999Sgblack@eecs.umich.edu //The address of the second part of this access if it needs to be split 4084999Sgblack@eecs.umich.edu //across a cache line boundary. 4099814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 4104999Sgblack@eecs.umich.edu 4114999Sgblack@eecs.umich.edu if(secondAddr > addr) 4127520Sgblack@eecs.umich.edu size = secondAddr - addr; 4134999Sgblack@eecs.umich.edu 4144999Sgblack@eecs.umich.edu dcache_latency = 0; 4154999Sgblack@eecs.umich.edu 41610024Sdam.sunwoo@arm.com req->taskId(taskId()); 4174999Sgblack@eecs.umich.edu while(1) { 4188832SAli.Saidi@ARM.com req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 4194999Sgblack@eecs.umich.edu 4204999Sgblack@eecs.umich.edu // translate to physical address 4216023Snate@binkert.org Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 4224999Sgblack@eecs.umich.edu 4234999Sgblack@eecs.umich.edu // Now do the access. 4244999Sgblack@eecs.umich.edu if (fault == NoFault) { 4254999Sgblack@eecs.umich.edu MemCmd cmd = MemCmd::WriteReq; // default 4264999Sgblack@eecs.umich.edu bool do_access = true; // flag to suppress cache access 4274999Sgblack@eecs.umich.edu 4286102Sgblack@eecs.umich.edu if (req->isLLSC()) { 4294999Sgblack@eecs.umich.edu cmd = MemCmd::StoreCondReq; 43010030SAli.Saidi@ARM.com do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 4314999Sgblack@eecs.umich.edu } else if (req->isSwap()) { 4324999Sgblack@eecs.umich.edu cmd = MemCmd::SwapReq; 4334999Sgblack@eecs.umich.edu if (req->isCondSwap()) { 4344999Sgblack@eecs.umich.edu assert(res); 4354999Sgblack@eecs.umich.edu req->setExtraData(*res); 4364999Sgblack@eecs.umich.edu } 4374999Sgblack@eecs.umich.edu } 4384999Sgblack@eecs.umich.edu 4396623Sgblack@eecs.umich.edu if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 4408949Sandreas.hansson@arm.com Packet pkt = Packet(req, cmd); 4417520Sgblack@eecs.umich.edu pkt.dataStatic(data); 4424999Sgblack@eecs.umich.edu 4438105Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 4444999Sgblack@eecs.umich.edu dcache_latency += 4454999Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread->getTC(), &pkt); 4464999Sgblack@eecs.umich.edu } else { 4478931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(pkt.getAddr())) 4488931Sandreas.hansson@arm.com system->getPhysMem().access(&pkt); 4494999Sgblack@eecs.umich.edu else 4504999Sgblack@eecs.umich.edu dcache_latency += dcachePort.sendAtomic(&pkt); 4514999Sgblack@eecs.umich.edu } 4524999Sgblack@eecs.umich.edu dcache_access = true; 4534999Sgblack@eecs.umich.edu assert(!pkt.isError()); 4544999Sgblack@eecs.umich.edu 4554999Sgblack@eecs.umich.edu if (req->isSwap()) { 4564999Sgblack@eecs.umich.edu assert(res); 4577520Sgblack@eecs.umich.edu memcpy(res, pkt.getPtr<uint8_t>(), fullSize); 4584999Sgblack@eecs.umich.edu } 4594999Sgblack@eecs.umich.edu } 4604999Sgblack@eecs.umich.edu 4614999Sgblack@eecs.umich.edu if (res && !req->isSwap()) { 4624999Sgblack@eecs.umich.edu *res = req->getExtraData(); 4634878Sstever@eecs.umich.edu } 4644040Ssaidi@eecs.umich.edu } 4654040Ssaidi@eecs.umich.edu 4664999Sgblack@eecs.umich.edu //If there's a fault or we don't need to access a second cache line, 4674999Sgblack@eecs.umich.edu //stop now. 4684999Sgblack@eecs.umich.edu if (fault != NoFault || secondAddr <= addr) 4694999Sgblack@eecs.umich.edu { 4706078Sgblack@eecs.umich.edu if (req->isLocked() && fault == NoFault) { 4716078Sgblack@eecs.umich.edu assert(locked); 4726078Sgblack@eecs.umich.edu locked = false; 4736078Sgblack@eecs.umich.edu } 4746739Sgblack@eecs.umich.edu if (fault != NoFault && req->isPrefetch()) { 4756739Sgblack@eecs.umich.edu return NoFault; 4766739Sgblack@eecs.umich.edu } else { 4776739Sgblack@eecs.umich.edu return fault; 4786739Sgblack@eecs.umich.edu } 4793170Sstever@eecs.umich.edu } 4803170Sstever@eecs.umich.edu 4814999Sgblack@eecs.umich.edu /* 4824999Sgblack@eecs.umich.edu * Set up for accessing the second cache line. 4834999Sgblack@eecs.umich.edu */ 4844999Sgblack@eecs.umich.edu 4854999Sgblack@eecs.umich.edu //Move the pointer we're reading into to the correct location. 4867520Sgblack@eecs.umich.edu data += size; 4874999Sgblack@eecs.umich.edu //Adjust the size to get the remaining bytes. 4887520Sgblack@eecs.umich.edu size = addr + fullSize - secondAddr; 4894999Sgblack@eecs.umich.edu //And access the right address. 4904999Sgblack@eecs.umich.edu addr = secondAddr; 4912623SN/A } 4922623SN/A} 4932623SN/A 4942623SN/A 4952623SN/Avoid 4962623SN/AAtomicSimpleCPU::tick() 4972623SN/A{ 4984940Snate@binkert.org DPRINTF(SimpleCPU, "Tick\n"); 4994940Snate@binkert.org 5005487Snate@binkert.org Tick latency = 0; 5012623SN/A 5026078Sgblack@eecs.umich.edu for (int i = 0; i < width || locked; ++i) { 5032623SN/A numCycles++; 5042623SN/A 5053387Sgblack@eecs.umich.edu if (!curStaticInst || !curStaticInst->isDelayedCommit()) 5063387Sgblack@eecs.umich.edu checkForInterrupts(); 5072626SN/A 5085348Ssaidi@eecs.umich.edu checkPcEventQueue(); 5098143SAli.Saidi@ARM.com // We must have just got suspended by a PC event 5109443SAndreas.Sandberg@ARM.com if (_status == Idle) { 5119443SAndreas.Sandberg@ARM.com tryCompleteDrain(); 5128143SAli.Saidi@ARM.com return; 5139443SAndreas.Sandberg@ARM.com } 5145348Ssaidi@eecs.umich.edu 5155669Sgblack@eecs.umich.edu Fault fault = NoFault; 5165669Sgblack@eecs.umich.edu 5177720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5187720Sgblack@eecs.umich.edu 5197720Sgblack@eecs.umich.edu bool needToFetch = !isRomMicroPC(pcState.microPC()) && 5207720Sgblack@eecs.umich.edu !curMacroStaticInst; 5217720Sgblack@eecs.umich.edu if (needToFetch) { 52210024Sdam.sunwoo@arm.com ifetch_req.taskId(taskId()); 5235894Sgblack@eecs.umich.edu setupFetchRequest(&ifetch_req); 5246023Snate@binkert.org fault = thread->itb->translateAtomic(&ifetch_req, tc, 5256023Snate@binkert.org BaseTLB::Execute); 5265894Sgblack@eecs.umich.edu } 5272623SN/A 5282623SN/A if (fault == NoFault) { 5294182Sgblack@eecs.umich.edu Tick icache_latency = 0; 5304182Sgblack@eecs.umich.edu bool icache_access = false; 5314182Sgblack@eecs.umich.edu dcache_access = false; // assume no dcache access 5322662Sstever@eecs.umich.edu 5337720Sgblack@eecs.umich.edu if (needToFetch) { 5349023Sgblack@eecs.umich.edu // This is commented out because the decoder would act like 5355694Sgblack@eecs.umich.edu // a tiny cache otherwise. It wouldn't be flushed when needed 5365694Sgblack@eecs.umich.edu // like the I cache. It should be flushed, and when that works 5375694Sgblack@eecs.umich.edu // this code should be uncommented. 5385669Sgblack@eecs.umich.edu //Fetch more instruction memory if necessary 5399023Sgblack@eecs.umich.edu //if(decoder.needMoreBytes()) 5405669Sgblack@eecs.umich.edu //{ 5415669Sgblack@eecs.umich.edu icache_access = true; 5428949Sandreas.hansson@arm.com Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 5435669Sgblack@eecs.umich.edu ifetch_pkt.dataStatic(&inst); 5442623SN/A 5458931Sandreas.hansson@arm.com if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 5468931Sandreas.hansson@arm.com system->getPhysMem().access(&ifetch_pkt); 5475669Sgblack@eecs.umich.edu else 5485669Sgblack@eecs.umich.edu icache_latency = icachePort.sendAtomic(&ifetch_pkt); 5494968Sacolyte@umich.edu 5505669Sgblack@eecs.umich.edu assert(!ifetch_pkt.isError()); 5514968Sacolyte@umich.edu 5525669Sgblack@eecs.umich.edu // ifetch_req is initialized to read the instruction directly 5535669Sgblack@eecs.umich.edu // into the CPU object's inst field. 5545669Sgblack@eecs.umich.edu //} 5555669Sgblack@eecs.umich.edu } 5564182Sgblack@eecs.umich.edu 5572623SN/A preExecute(); 5583814Ssaidi@eecs.umich.edu 5595001Sgblack@eecs.umich.edu if (curStaticInst) { 5604182Sgblack@eecs.umich.edu fault = curStaticInst->execute(this, traceData); 5614998Sgblack@eecs.umich.edu 5624998Sgblack@eecs.umich.edu // keep an instruction count 56310381Sdam.sunwoo@arm.com if (fault == NoFault) { 5644998Sgblack@eecs.umich.edu countInst(); 56510381Sdam.sunwoo@arm.com if (!curStaticInst->isMicroop() || 56610381Sdam.sunwoo@arm.com curStaticInst->isLastMicroop()) { 56710381Sdam.sunwoo@arm.com ppCommit->notify(std::make_pair(thread, curStaticInst)); 56810381Sdam.sunwoo@arm.com } 56910381Sdam.sunwoo@arm.com } 5707655Sali.saidi@arm.com else if (traceData && !DTRACE(ExecFaulting)) { 5715001Sgblack@eecs.umich.edu delete traceData; 5725001Sgblack@eecs.umich.edu traceData = NULL; 5735001Sgblack@eecs.umich.edu } 5744998Sgblack@eecs.umich.edu 5754182Sgblack@eecs.umich.edu postExecute(); 5764182Sgblack@eecs.umich.edu } 5772623SN/A 5783814Ssaidi@eecs.umich.edu // @todo remove me after debugging with legion done 5794539Sgblack@eecs.umich.edu if (curStaticInst && (!curStaticInst->isMicroop() || 5804539Sgblack@eecs.umich.edu curStaticInst->isFirstMicroop())) 5813814Ssaidi@eecs.umich.edu instCnt++; 5823814Ssaidi@eecs.umich.edu 5835487Snate@binkert.org Tick stall_ticks = 0; 5845487Snate@binkert.org if (simulate_inst_stalls && icache_access) 5855487Snate@binkert.org stall_ticks += icache_latency; 5865487Snate@binkert.org 5875487Snate@binkert.org if (simulate_data_stalls && dcache_access) 5885487Snate@binkert.org stall_ticks += dcache_latency; 5895487Snate@binkert.org 5905487Snate@binkert.org if (stall_ticks) { 5919180Sandreas.hansson@arm.com // the atomic cpu does its accounting in ticks, so 5929180Sandreas.hansson@arm.com // keep counting in ticks but round to the clock 5939180Sandreas.hansson@arm.com // period 5949180Sandreas.hansson@arm.com latency += divCeil(stall_ticks, clockPeriod()) * 5959180Sandreas.hansson@arm.com clockPeriod(); 5962623SN/A } 5972623SN/A 5982623SN/A } 5994377Sgblack@eecs.umich.edu if(fault != NoFault || !stayAtPC) 6004182Sgblack@eecs.umich.edu advancePC(fault); 6012623SN/A } 6022623SN/A 6039443SAndreas.Sandberg@ARM.com if (tryCompleteDrain()) 6049443SAndreas.Sandberg@ARM.com return; 6059443SAndreas.Sandberg@ARM.com 6065487Snate@binkert.org // instruction takes at least one cycle 6079179Sandreas.hansson@arm.com if (latency < clockPeriod()) 6089179Sandreas.hansson@arm.com latency = clockPeriod(); 6095487Snate@binkert.org 6102626SN/A if (_status != Idle) 6117823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + latency); 6122623SN/A} 6132623SN/A 61410381Sdam.sunwoo@arm.comvoid 61510381Sdam.sunwoo@arm.comAtomicSimpleCPU::regProbePoints() 61610381Sdam.sunwoo@arm.com{ 61710381Sdam.sunwoo@arm.com ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 61810381Sdam.sunwoo@arm.com (getProbeManager(), "Commit"); 61910381Sdam.sunwoo@arm.com} 6202623SN/A 6215315Sstever@gmail.comvoid 6225315Sstever@gmail.comAtomicSimpleCPU::printAddr(Addr a) 6235315Sstever@gmail.com{ 6245315Sstever@gmail.com dcachePort.printAddr(a); 6255315Sstever@gmail.com} 6265315Sstever@gmail.com 6272623SN/A//////////////////////////////////////////////////////////////////////// 6282623SN/A// 6292623SN/A// AtomicSimpleCPU Simulation Object 6302623SN/A// 6314762Snate@binkert.orgAtomicSimpleCPU * 6324762Snate@binkert.orgAtomicSimpleCPUParams::create() 6332623SN/A{ 6345529Snate@binkert.org numThreads = 1; 6358779Sgblack@eecs.umich.edu if (!FullSystem && workload.size() != 1) 6364762Snate@binkert.org panic("only one workload allowed"); 6375529Snate@binkert.org return new AtomicSimpleCPU(this); 6382623SN/A} 639