reg_class.hh revision 13762:36d5a1d9f5e6 
1/*
2 * Copyright (c) 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Advanced Micro Devices, Inc.
15 * All rights reserved
16 *.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathanael Premillieu
42 *          Rekai Gonzalez
43 */
44
45#ifndef __CPU__REG_CLASS_HH__
46#define __CPU__REG_CLASS_HH__
47
48#include <cassert>
49#include <cstddef>
50
51#include "arch/generic/types.hh"
52#include "arch/registers.hh"
53#include "config/the_isa.hh"
54
55/** Enumerate the classes of registers. */
56enum RegClass {
57    IntRegClass,        ///< Integer register
58    FloatRegClass,      ///< Floating-point register
59    /** Vector Register. */
60    VecRegClass,
61    /** Vector Register Native Elem lane. */
62    VecElemClass,
63    VecPredRegClass,
64    CCRegClass,         ///< Condition-code register
65    MiscRegClass        ///< Control (misc) register
66};
67
68/** Number of register classes.
69 * This value is not part of the enum, because putting it there makes the
70 * compiler complain about unhandled cases in some switch statements.
71 */
72const int NumRegClasses = MiscRegClass + 1;
73
74/** Register ID: describe an architectural register with its class and index.
75 * This structure is used instead of just the register index to disambiguate
76 * between different classes of registers. For example, a integer register with
77 * index 3 is represented by Regid(IntRegClass, 3).
78 */
79class RegId {
80  private:
81    static const char* regClassStrings[];
82    RegClass regClass;
83    RegIndex regIdx;
84    ElemIndex elemIdx;
85    static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
86    friend struct std::hash<RegId>;
87  public:
88    RegId() : regClass(IntRegClass), regIdx(0), elemIdx(-1) {}
89    RegId(RegClass reg_class, RegIndex reg_idx)
90        : regClass(reg_class), regIdx(reg_idx), elemIdx(-1)
91    {
92        panic_if(regClass == VecElemClass,
93                "Creating vector physical index w/o element index");
94    }
95
96    explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
97        : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx)
98    {
99        panic_if(regClass != VecElemClass,
100                "Creating non-vector physical index w/ element index");
101    }
102
103    bool operator==(const RegId& that) const {
104        return regClass == that.classValue() && regIdx == that.index()
105                                             && elemIdx == that.elemIndex();
106    }
107
108    bool operator!=(const RegId& that) const {
109        return !(*this==that);
110    }
111
112    /** Order operator.
113     * The order is required to implement maps with key type RegId
114     */
115    bool operator<(const RegId& that) const {
116        return regClass < that.classValue() ||
117            (regClass == that.classValue() && (
118                   regIdx < that.index() ||
119                   (regIdx == that.index() && elemIdx < that.elemIndex())));
120    }
121
122    /**
123     * Return true if this register can be renamed
124     */
125    bool isRenameable() const
126    {
127        return regClass != MiscRegClass;
128    }
129
130    /**
131     * Check if this is the zero register.
132     * Returns true if this register is a zero register (needs to have a
133     * constant zero value throughout the execution).
134     */
135
136    inline bool isZeroReg() const
137    {
138        return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
139               (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
140                regIdx == TheISA::ZeroReg));
141    }
142
143    /** @return true if it is an integer physical register. */
144    bool isIntReg() const { return regClass == IntRegClass; }
145
146    /** @return true if it is a floating-point physical register. */
147    bool isFloatReg() const { return regClass == FloatRegClass; }
148
149    /** @Return true if it is a  condition-code physical register. */
150    bool isVecReg() const { return regClass == VecRegClass; }
151
152    /** @Return true if it is a  condition-code physical register. */
153    bool isVecElem() const { return regClass == VecElemClass; }
154
155    /** @Return true if it is a predicate physical register. */
156    bool isVecPredReg() const { return regClass == VecPredRegClass; }
157
158    /** @Return true if it is a  condition-code physical register. */
159    bool isCCReg() const { return regClass == CCRegClass; }
160
161    /** @Return true if it is a  condition-code physical register. */
162    bool isMiscReg() const { return regClass == MiscRegClass; }
163
164    /**
165     * Return true if this register can be renamed
166     */
167    bool isRenameable()
168    {
169        return regClass != MiscRegClass;
170    }
171
172    /** Index accessors */
173    /** @{ */
174    const RegIndex& index() const { return regIdx; }
175    RegIndex& index() { return regIdx; }
176
177    /** Index flattening.
178     * Required to be able to use a vector for the register mapping.
179     */
180    inline RegIndex flatIndex() const
181    {
182        switch (regClass) {
183          case IntRegClass:
184          case FloatRegClass:
185          case VecRegClass:
186          case VecPredRegClass:
187          case CCRegClass:
188          case MiscRegClass:
189            return regIdx;
190          case VecElemClass:
191            return Scale*regIdx + elemIdx;
192        }
193        panic("Trying to flatten a register without class!");
194        return -1;
195    }
196    /** @} */
197
198    /** Elem accessor */
199    const RegIndex& elemIndex() const { return elemIdx; }
200    /** Class accessor */
201    const RegClass& classValue() const { return regClass; }
202    /** Return a const char* with the register class name. */
203    const char* className() const { return regClassStrings[regClass]; }
204
205    friend std::ostream&
206    operator<<(std::ostream& os, const RegId& rid) {
207        return os << rid.className() << "{" << rid.index() << "}";
208    }
209};
210
211/** Physical register index type.
212 * Although the Impl might be a better for this, but there are a few classes
213 * that need this typedef yet are not templated on the Impl.
214 */
215using PhysRegIndex = short int;
216
217/** Physical register ID.
218 * Like a register ID but physical. The inheritance is private because the
219 * only relationship between this types is functional, and it is done to
220 * prevent code replication. */
221class PhysRegId : private RegId {
222  private:
223    PhysRegIndex flatIdx;
224
225  public:
226    explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1) {}
227
228    /** Scalar PhysRegId constructor. */
229    explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
230              PhysRegIndex _flatIdx)
231        : RegId(_regClass, _regIdx), flatIdx(_flatIdx)
232    {}
233
234    /** Vector PhysRegId constructor (w/ elemIndex). */
235    explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
236              ElemIndex elem_idx, PhysRegIndex flat_idx)
237        : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx) { }
238
239    /** Visible RegId methods */
240    /** @{ */
241    using RegId::index;
242    using RegId::classValue;
243    using RegId::isZeroReg;
244    using RegId::className;
245    using RegId::elemIndex;
246     /** @} */
247    /**
248     * Explicit forward methods, to prevent comparisons of PhysRegId with
249     * RegIds.
250     */
251    /** @{ */
252    bool operator<(const PhysRegId& that) const {
253        return RegId::operator<(that);
254    }
255
256    bool operator==(const PhysRegId& that) const {
257        return RegId::operator==(that);
258    }
259
260    bool operator!=(const PhysRegId& that) const {
261        return RegId::operator!=(that);
262    }
263    /** @} */
264
265    /** @return true if it is an integer physical register. */
266    bool isIntPhysReg() const { return isIntReg(); }
267
268    /** @return true if it is a floating-point physical register. */
269    bool isFloatPhysReg() const { return isFloatReg(); }
270
271    /** @Return true if it is a  condition-code physical register. */
272    bool isCCPhysReg() const { return isCCReg(); }
273
274    /** @Return true if it is a vector physical register. */
275    bool isVectorPhysReg() const { return isVecReg(); }
276
277    /** @Return true if it is a vector element physical register. */
278    bool isVectorPhysElem() const { return isVecElem(); }
279
280    /** @return true if it is a vector predicate physical register. */
281    bool isVecPredPhysReg() const { return isVecPredReg(); }
282
283    /** @Return true if it is a  condition-code physical register. */
284    bool isMiscPhysReg() const { return isMiscReg(); }
285
286    /**
287     * Returns true if this register is always associated to the same
288     * architectural register.
289     */
290    bool isFixedMapping() const
291    {
292        return !isRenameable();
293    }
294
295    /** Flat index accessor */
296    const PhysRegIndex& flatIndex() const { return flatIdx; }
297
298    static PhysRegId elemId(const PhysRegId* vid, ElemIndex elem)
299    {
300        assert(vid->isVectorPhysReg());
301        return PhysRegId(VecElemClass, vid->index(), elem);
302    }
303};
304
305/** Constant pointer definition.
306 * PhysRegIds only need to be created once and then we can just share
307 * pointers */
308using PhysRegIdPtr = const PhysRegId*;
309
310namespace std
311{
312template<>
313struct hash<RegId>
314{
315    size_t operator()(const RegId& reg_id) const
316    {
317        // Extract unique integral values for the effective fields of a RegId.
318        const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
319        const size_t class_num = static_cast<size_t>(reg_id.regClass);
320
321        const size_t shifted_class_num = class_num << (sizeof(RegIndex) << 3);
322
323        // Concatenate the class_num to the end of the flat_index, in order to
324        // maximize information retained.
325        const size_t concatenated_hash = flat_index | shifted_class_num;
326
327        // If RegIndex is larger than size_t, then class_num will not be
328        // considered by this hash function, so we may wish to perform a
329        // different operation to include that information in the hash.
330        static_assert(sizeof(RegIndex) < sizeof(size_t),
331            "sizeof(RegIndex) should be less than sizeof(size_t)");
332
333        return concatenated_hash;
334    }
335};
336}
337
338#endif // __CPU__REG_CLASS_HH__
339