reg_class.hh revision 12858 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Advanced Micro Devices, Inc.
15 * All rights reserved
16 *.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathanael Premillieu
42 *          Rekai Gonzalez
43 */
44
45#ifndef __CPU__REG_CLASS_HH__
46#define __CPU__REG_CLASS_HH__
47
48#include <cassert>
49#include <cstddef>
50
51#include "arch/generic/types.hh"
52#include "arch/registers.hh"
53#include "config/the_isa.hh"
54
55/** Enumerate the classes of registers. */
56enum RegClass {
57    IntRegClass,        ///< Integer register
58    FloatRegClass,      ///< Floating-point register
59    /** Vector Register. */
60    VecRegClass,
61    /** Vector Register Native Elem lane. */
62    VecElemClass,
63    CCRegClass,         ///< Condition-code register
64    MiscRegClass        ///< Control (misc) register
65};
66
67/** Number of register classes.
68 * This value is not part of the enum, because putting it there makes the
69 * compiler complain about unhandled cases in some switch statements.
70 */
71const int NumRegClasses = MiscRegClass + 1;
72
73/** Register ID: describe an architectural register with its class and index.
74 * This structure is used instead of just the register index to disambiguate
75 * between different classes of registers. For example, a integer register with
76 * index 3 is represented by Regid(IntRegClass, 3).
77 */
78class RegId {
79  private:
80    static const char* regClassStrings[];
81    RegClass regClass;
82    RegIndex regIdx;
83    ElemIndex elemIdx;
84    static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
85    friend struct std::hash<RegId>;
86  public:
87    RegId() {};
88    RegId(RegClass reg_class, RegIndex reg_idx)
89        : regClass(reg_class), regIdx(reg_idx), elemIdx(-1)
90    {
91        panic_if(regClass == VecElemClass,
92                "Creating vector physical index w/o element index");
93    }
94
95    explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
96        : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx)
97    {
98        panic_if(regClass != VecElemClass,
99                "Creating non-vector physical index w/ element index");
100    }
101
102    bool operator==(const RegId& that) const {
103        return regClass == that.classValue() && regIdx == that.index()
104                                             && elemIdx == that.elemIndex();
105    }
106
107    bool operator!=(const RegId& that) const {
108        return !(*this==that);
109    }
110
111    /** Order operator.
112     * The order is required to implement maps with key type RegId
113     */
114    bool operator<(const RegId& that) const {
115        return regClass < that.classValue() ||
116            (regClass == that.classValue() && (
117                   regIdx < that.index() ||
118                   (regIdx == that.index() && elemIdx < that.elemIndex())));
119    }
120
121    /**
122     * Return true if this register can be renamed
123     */
124    bool isRenameable() const
125    {
126        return regClass != MiscRegClass;
127    }
128
129    /**
130     * Check if this is the zero register.
131     * Returns true if this register is a zero register (needs to have a
132     * constant zero value throughout the execution).
133     */
134
135    inline bool isZeroReg() const
136    {
137        return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
138               (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
139                regIdx == TheISA::ZeroReg));
140    }
141
142    /** @return true if it is an integer physical register. */
143    bool isIntReg() const { return regClass == IntRegClass; }
144
145    /** @return true if it is a floating-point physical register. */
146    bool isFloatReg() const { return regClass == FloatRegClass; }
147
148    /** @Return true if it is a  condition-code physical register. */
149    bool isVecReg() const { return regClass == VecRegClass; }
150
151    /** @Return true if it is a  condition-code physical register. */
152    bool isVecElem() const { return regClass == VecElemClass; }
153
154    /** @Return true if it is a  condition-code physical register. */
155    bool isCCReg() const { return regClass == CCRegClass; }
156
157    /** @Return true if it is a  condition-code physical register. */
158    bool isMiscReg() const { return regClass == MiscRegClass; }
159
160    /**
161     * Return true if this register can be renamed
162     */
163    bool isRenameable()
164    {
165        return regClass != MiscRegClass;
166    }
167
168    /** Index accessors */
169    /** @{ */
170    const RegIndex& index() const { return regIdx; }
171    RegIndex& index() { return regIdx; }
172
173    /** Index flattening.
174     * Required to be able to use a vector for the register mapping.
175     */
176    inline RegIndex flatIndex() const
177    {
178        switch (regClass) {
179          case IntRegClass:
180          case FloatRegClass:
181          case VecRegClass:
182          case CCRegClass:
183          case MiscRegClass:
184            return regIdx;
185          case VecElemClass:
186            return Scale*regIdx + elemIdx;
187        }
188        panic("Trying to flatten a register without class!");
189        return -1;
190    }
191    /** @} */
192
193    /** Elem accessor */
194    const RegIndex& elemIndex() const { return elemIdx; }
195    /** Class accessor */
196    const RegClass& classValue() const { return regClass; }
197    /** Return a const char* with the register class name. */
198    const char* className() const { return regClassStrings[regClass]; }
199
200    friend std::ostream&
201    operator<<(std::ostream& os, const RegId& rid) {
202        return os << rid.className() << "{" << rid.index() << "}";
203    }
204};
205
206namespace std
207{
208template<>
209struct hash<RegId>
210{
211    size_t operator()(const RegId& reg_id) const
212    {
213        // Extract unique integral values for the effective fields of a RegId.
214        const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
215        const size_t class_num = static_cast<size_t>(reg_id.regClass);
216
217        const size_t shifted_class_num = class_num << (sizeof(RegIndex) << 3);
218
219        // Concatenate the class_num to the end of the flat_index, in order to
220        // maximize information retained.
221        const size_t concatenated_hash = flat_index | shifted_class_num;
222
223        // If RegIndex is larger than size_t, then class_num will not be
224        // considered by this hash function, so we may wish to perform a
225        // different operation to include that information in the hash.
226        static_assert(sizeof(RegIndex) < sizeof(size_t),
227            "sizeof(RegIndex) should be less than sizeof(size_t)");
228
229        return concatenated_hash;
230    }
231};
232}
233
234#endif // __CPU__REG_CLASS_HH__
235