reg_class.hh revision 12857
1/* 2 * Copyright (c) 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2013 Advanced Micro Devices, Inc. 15 * All rights reserved 16 *. 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathanael Premillieu 42 * Rekai Gonzalez 43 */ 44 45#ifndef __CPU__REG_CLASS_HH__ 46#define __CPU__REG_CLASS_HH__ 47 48#include <cassert> 49#include <cstddef> 50 51#include "arch/generic/types.hh" 52#include "arch/registers.hh" 53#include "config/the_isa.hh" 54 55/** Enumerate the classes of registers. */ 56enum RegClass { 57 IntRegClass, ///< Integer register 58 FloatRegClass, ///< Floating-point register 59 /** Vector Register. */ 60 VecRegClass, 61 /** Vector Register Native Elem lane. */ 62 VecElemClass, 63 CCRegClass, ///< Condition-code register 64 MiscRegClass ///< Control (misc) register 65}; 66 67/** Number of register classes. 68 * This value is not part of the enum, because putting it there makes the 69 * compiler complain about unhandled cases in some switch statements. 70 */ 71const int NumRegClasses = MiscRegClass + 1; 72 73/** Register ID: describe an architectural register with its class and index. 74 * This structure is used instead of just the register index to disambiguate 75 * between different classes of registers. For example, a integer register with 76 * index 3 is represented by Regid(IntRegClass, 3). 77 */ 78class RegId { 79 private: 80 static const char* regClassStrings[]; 81 RegClass regClass; 82 RegIndex regIdx; 83 ElemIndex elemIdx; 84 static constexpr size_t Scale = TheISA::NumVecElemPerVecReg; 85 public: 86 RegId() {}; 87 RegId(RegClass reg_class, RegIndex reg_idx) 88 : regClass(reg_class), regIdx(reg_idx), elemIdx(-1) 89 { 90 panic_if(regClass == VecElemClass, 91 "Creating vector physical index w/o element index"); 92 } 93 94 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) 95 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx) 96 { 97 panic_if(regClass != VecElemClass, 98 "Creating non-vector physical index w/ element index"); 99 } 100 101 bool operator==(const RegId& that) const { 102 return regClass == that.classValue() && regIdx == that.index() 103 && elemIdx == that.elemIndex(); 104 } 105 106 bool operator!=(const RegId& that) const { 107 return !(*this==that); 108 } 109 110 /** Order operator. 111 * The order is required to implement maps with key type RegId 112 */ 113 bool operator<(const RegId& that) const { 114 return regClass < that.classValue() || 115 (regClass == that.classValue() && ( 116 regIdx < that.index() || 117 (regIdx == that.index() && elemIdx < that.elemIndex()))); 118 } 119 120 /** 121 * Return true if this register can be renamed 122 */ 123 bool isRenameable() const 124 { 125 return regClass != MiscRegClass; 126 } 127 128 /** 129 * Check if this is the zero register. 130 * Returns true if this register is a zero register (needs to have a 131 * constant zero value throughout the execution). 132 */ 133 134 inline bool isZeroReg() const 135 { 136 return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) || 137 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass && 138 regIdx == TheISA::ZeroReg)); 139 } 140 141 /** @return true if it is an integer physical register. */ 142 bool isIntReg() const { return regClass == IntRegClass; } 143 144 /** @return true if it is a floating-point physical register. */ 145 bool isFloatReg() const { return regClass == FloatRegClass; } 146 147 /** @Return true if it is a condition-code physical register. */ 148 bool isVecReg() const { return regClass == VecRegClass; } 149 150 /** @Return true if it is a condition-code physical register. */ 151 bool isVecElem() const { return regClass == VecElemClass; } 152 153 /** @Return true if it is a condition-code physical register. */ 154 bool isCCReg() const { return regClass == CCRegClass; } 155 156 /** @Return true if it is a condition-code physical register. */ 157 bool isMiscReg() const { return regClass == MiscRegClass; } 158 159 /** 160 * Return true if this register can be renamed 161 */ 162 bool isRenameable() 163 { 164 return regClass != MiscRegClass; 165 } 166 167 /** Index accessors */ 168 /** @{ */ 169 const RegIndex& index() const { return regIdx; } 170 RegIndex& index() { return regIdx; } 171 172 /** Index flattening. 173 * Required to be able to use a vector for the register mapping. 174 */ 175 inline RegIndex flatIndex() const 176 { 177 switch (regClass) { 178 case IntRegClass: 179 case FloatRegClass: 180 case VecRegClass: 181 case CCRegClass: 182 case MiscRegClass: 183 return regIdx; 184 case VecElemClass: 185 return Scale*regIdx + elemIdx; 186 } 187 panic("Trying to flatten a register without class!"); 188 return -1; 189 } 190 /** @} */ 191 192 /** Elem accessor */ 193 const RegIndex& elemIndex() const { return elemIdx; } 194 /** Class accessor */ 195 const RegClass& classValue() const { return regClass; } 196 /** Return a const char* with the register class name. */ 197 const char* className() const { return regClassStrings[regClass]; } 198 199 friend std::ostream& 200 operator<<(std::ostream& os, const RegId& rid) { 201 return os << rid.className() << "{" << rid.index() << "}"; 202 } 203}; 204#endif // __CPU__REG_CLASS_HH__ 205