reg_class.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Advanced Micro Devices, Inc.
15 * All rights reserved
16 *.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathanael Premillieu
42 */
43
44#ifndef __CPU__REG_CLASS_HH__
45#define __CPU__REG_CLASS_HH__
46
47#include <cassert>
48#include <cstddef>
49
50#include "arch/generic/types.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53
54/** Enumerate the classes of registers. */
55enum RegClass {
56    IntRegClass,        ///< Integer register
57    FloatRegClass,      ///< Floating-point register
58    CCRegClass,         ///< Condition-code register
59    MiscRegClass        ///< Control (misc) register
60};
61
62/** Number of register classes.
63 * This value is not part of the enum, because putting it there makes the
64 * compiler complain about unhandled cases in some switch statements.
65 */
66const int NumRegClasses = MiscRegClass + 1;
67
68/** Register ID: describe an architectural register with its class and index.
69 * This structure is used instead of just the register index to disambiguate
70 * between different classes of registers. For example, a integer register with
71 * index 3 is represented by Regid(IntRegClass, 3).
72 */
73class RegId {
74  private:
75    static const char* regClassStrings[];
76    RegClass regClass;
77    RegIndex regIdx;
78  public:
79    RegId() {};
80    RegId(RegClass reg_class, RegIndex reg_idx)
81        : regClass(reg_class), regIdx(reg_idx)
82    {}
83
84    bool operator==(const RegId& that) const {
85        return regClass == that.classValue() && regIdx == that.index();
86    }
87
88    bool operator!=(const RegId& that) const {
89        return !(*this==that);
90    }
91
92    /** Order operator.
93     * The order is required to implement maps with key type RegId
94     */
95    bool operator<(const RegId& that) const {
96        return regClass < that.classValue() ||
97                (regClass == that.classValue() && regIdx < that.index());
98    }
99
100    /**
101     * Return true if this register can be renamed
102     */
103    bool isRenameable() const
104    {
105        return regClass != MiscRegClass;
106    }
107
108    /**
109     * Check if this is the zero register.
110     * Returns true if this register is a zero register (needs to have a
111     * constant zero value throughout the execution).
112     */
113
114    inline bool isZeroReg() const;
115
116    /** @return true if it is an integer physical register. */
117    bool isIntReg() const { return regClass == IntRegClass; }
118
119    /** @return true if it is a floating-point physical register. */
120    bool isFloatReg() const { return regClass == FloatRegClass; }
121
122    /** @Return true if it is a  condition-code physical register. */
123    bool isCCReg() const { return regClass == CCRegClass; }
124
125    /** @Return true if it is a  condition-code physical register. */
126    bool isMiscReg() const { return regClass == MiscRegClass; }
127
128    /** Index accessors */
129    /** @{ */
130    const RegIndex& index() const { return regIdx; }
131    RegIndex& index() { return regIdx; }
132
133    /** Index flattening.
134     * Required to be able to use a vector for the register mapping.
135     */
136    inline RegIndex flatIndex() const;
137    /** @} */
138
139    /** Class accessor */
140    const RegClass& classValue() const { return regClass; }
141    /** Return a const char* with the register class name. */
142    const char* className() const { return regClassStrings[regClass]; }
143
144    friend std::ostream&
145    operator<<(std::ostream& os, const RegId& rid) {
146        return os << rid.className() << "{" << rid.index() << "}";
147    }
148};
149#endif // __CPU__REG_CLASS_HH__
150