reg_class.hh revision 12104:edd63f9c6184 
1/*
2 * Copyright (c) 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Advanced Micro Devices, Inc.
15 * All rights reserved
16 *.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathanael Premillieu
42 */
43
44#ifndef __CPU__REG_CLASS_HH__
45#define __CPU__REG_CLASS_HH__
46
47#include <cassert>
48#include <cstddef>
49
50#include "arch/generic/types.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53
54/// Enumerate the classes of registers.
55enum RegClass {
56    IntRegClass,        ///< Integer register
57    FloatRegClass,      ///< Floating-point register
58    CCRegClass,         ///< Condition-code register
59    MiscRegClass        ///< Control (misc) register
60};
61
62/// Number of register classes.  This value is not part of the enum,
63/// because putting it there makes the compiler complain about
64/// unhandled cases in some switch statements.
65const int NumRegClasses = MiscRegClass + 1;
66
67/// Register ID: describe an architectural register with its class and index.
68/// This structure is used instead of just the register index to disambiguate
69/// between different classes of registers.
70/// For example, a integer register with index 3 is represented by
71/// Regid(IntRegClass, 3).
72struct RegId {
73    RegClass regClass;
74    RegIndex regIdx;
75    RegId() {};
76    RegId(RegClass reg_class, RegIndex reg_idx)
77        : regClass(reg_class), regIdx(reg_idx)
78    {}
79
80    bool operator==(const RegId& that) const {
81        return regClass == that.regClass && regIdx == that.regIdx;
82    }
83
84    bool operator!=(const RegId& that) const {
85        return !(*this==that);
86    }
87
88    /**
89     * Returns true if this register is a zero register (needs to have a
90     * constant zero value throughout the execution)
91     */
92    bool isZeroReg() const
93    {
94        return (regIdx == TheISA::ZeroReg &&
95                (regClass == IntRegClass ||
96                 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass)));
97    }
98
99    /**
100     * Return true if this register can be renamed
101     */
102    bool isRenameable()
103    {
104        return regClass != MiscRegClass;
105    }
106
107    static const RegId zeroReg;
108};
109
110/// Map enum values to strings for debugging
111extern const char *RegClassStrings[];
112#endif // __CPU__REG_CLASS_HH__
113