reg_class.hh revision 9920
19913Ssteve.reinhardt@amd.com/* 29913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 39913Ssteve.reinhardt@amd.com * All rights reserved 49913Ssteve.reinhardt@amd.com *. 59913Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 69913Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 79913Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 89913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 99913Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 109913Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 119913Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 129913Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 139913Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 149913Ssteve.reinhardt@amd.com * this software without specific prior written permission. 159913Ssteve.reinhardt@amd.com * 169913Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179913Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189913Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199913Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209913Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219913Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229913Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239913Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249913Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259913Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269913Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279913Ssteve.reinhardt@amd.com * 289913Ssteve.reinhardt@amd.com * Authors: Steve Reinhardt 299913Ssteve.reinhardt@amd.com */ 309913Ssteve.reinhardt@amd.com 319913Ssteve.reinhardt@amd.com#ifndef __CPU__REG_CLASS_HH__ 329913Ssteve.reinhardt@amd.com#define __CPU__REG_CLASS_HH__ 339913Ssteve.reinhardt@amd.com 349913Ssteve.reinhardt@amd.com#include <cassert> 359913Ssteve.reinhardt@amd.com#include <cstddef> 369913Ssteve.reinhardt@amd.com 379913Ssteve.reinhardt@amd.com#include "arch/registers.hh" 389913Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 399913Ssteve.reinhardt@amd.com 409913Ssteve.reinhardt@amd.com/// Enumerate the classes of registers. 419913Ssteve.reinhardt@amd.comenum RegClass { 429913Ssteve.reinhardt@amd.com IntRegClass, ///< Integer register 439913Ssteve.reinhardt@amd.com FloatRegClass, ///< Floating-point register 449920Syasuko.eckert@amd.com CCRegClass, ///< Condition-code register 459913Ssteve.reinhardt@amd.com MiscRegClass ///< Control (misc) register 469913Ssteve.reinhardt@amd.com}; 479913Ssteve.reinhardt@amd.com 489913Ssteve.reinhardt@amd.com/// Number of register classes. This value is not part of the enum, 499913Ssteve.reinhardt@amd.com/// because putting it there makes the compiler complain about 509913Ssteve.reinhardt@amd.com/// unhandled cases in some switch statements. 519913Ssteve.reinhardt@amd.comconst int NumRegClasses = MiscRegClass + 1; 529913Ssteve.reinhardt@amd.com 539913Ssteve.reinhardt@amd.com/** 549913Ssteve.reinhardt@amd.com * Map a 'unified' architectural register index to its register class. 559913Ssteve.reinhardt@amd.com * The unified architectural register index space is used to represent 569913Ssteve.reinhardt@amd.com * all architectural register identifiers in a single contiguous 579913Ssteve.reinhardt@amd.com * index space. See http://gem5.org/Register_Indexing. 589913Ssteve.reinhardt@amd.com * 599913Ssteve.reinhardt@amd.com * @param reg_idx Unified-space register index 609913Ssteve.reinhardt@amd.com * @param rel_reg_idx Optional output param pointer; if non-NULL, location 619913Ssteve.reinhardt@amd.com * will be written with the relative register index for reg_idx 629913Ssteve.reinhardt@amd.com * 639913Ssteve.reinhardt@amd.com * @return Register class of reg_idx 649913Ssteve.reinhardt@amd.com */ 659913Ssteve.reinhardt@amd.cominline 669913Ssteve.reinhardt@amd.comRegClass regIdxToClass(TheISA::RegIndex reg_idx, 679913Ssteve.reinhardt@amd.com TheISA::RegIndex *rel_reg_idx = NULL) 689913Ssteve.reinhardt@amd.com{ 699918Ssteve.reinhardt@amd.com assert(reg_idx < TheISA::Max_Reg_Index); 709913Ssteve.reinhardt@amd.com RegClass cl; 719913Ssteve.reinhardt@amd.com int offset; 729913Ssteve.reinhardt@amd.com 739918Ssteve.reinhardt@amd.com if (reg_idx < TheISA::FP_Reg_Base) { 749913Ssteve.reinhardt@amd.com cl = IntRegClass; 759913Ssteve.reinhardt@amd.com offset = 0; 769920Syasuko.eckert@amd.com } else if (reg_idx < TheISA::CC_Reg_Base) { 779913Ssteve.reinhardt@amd.com cl = FloatRegClass; 789918Ssteve.reinhardt@amd.com offset = TheISA::FP_Reg_Base; 799920Syasuko.eckert@amd.com } else if (reg_idx < TheISA::Misc_Reg_Base) { 809920Syasuko.eckert@amd.com // if there are no CC regs, the ISA should set 819920Syasuko.eckert@amd.com // CC_Reg_Base == Misc_Reg_Base so the if above 829920Syasuko.eckert@amd.com // never succeeds 839920Syasuko.eckert@amd.com cl = CCRegClass; 849920Syasuko.eckert@amd.com offset = TheISA::CC_Reg_Base; 859913Ssteve.reinhardt@amd.com } else { 869913Ssteve.reinhardt@amd.com cl = MiscRegClass; 879918Ssteve.reinhardt@amd.com offset = TheISA::Misc_Reg_Base; 889913Ssteve.reinhardt@amd.com } 899913Ssteve.reinhardt@amd.com 909913Ssteve.reinhardt@amd.com if (rel_reg_idx) 919913Ssteve.reinhardt@amd.com *rel_reg_idx = reg_idx - offset; 929913Ssteve.reinhardt@amd.com return cl; 939913Ssteve.reinhardt@amd.com} 949913Ssteve.reinhardt@amd.com 959913Ssteve.reinhardt@amd.com/// Map enum values to strings for debugging 969913Ssteve.reinhardt@amd.comextern const char *RegClassStrings[]; 979913Ssteve.reinhardt@amd.com 989913Ssteve.reinhardt@amd.com 999913Ssteve.reinhardt@amd.com#endif // __CPU__REG_CLASS_HH__ 100