tage.hh revision 13654:dc3878f03a0c
19651SAndreas.Sandberg@ARM.com/* 29651SAndreas.Sandberg@ARM.com * Copyright (c) 2014 The University of Wisconsin 39651SAndreas.Sandberg@ARM.com * 49651SAndreas.Sandberg@ARM.com * Copyright (c) 2006 INRIA (Institut National de Recherche en 59651SAndreas.Sandberg@ARM.com * Informatique et en Automatique / French National Research Institute 69651SAndreas.Sandberg@ARM.com * for Computer Science and Applied Mathematics) 79651SAndreas.Sandberg@ARM.com * 89651SAndreas.Sandberg@ARM.com * All rights reserved. 99651SAndreas.Sandberg@ARM.com * 109651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 119651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 129651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 139651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 149651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 159651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 169651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 179651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 189651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 199651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 209651SAndreas.Sandberg@ARM.com * 219651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 229651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 239651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 249651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 259651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 269651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 279651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 289651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 299651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 309651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 319651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 329651SAndreas.Sandberg@ARM.com * 339651SAndreas.Sandberg@ARM.com * Authors: Vignyan Reddy, Dibakar Gope and Arthur Perais, 349651SAndreas.Sandberg@ARM.com * from André Seznec's code. 359651SAndreas.Sandberg@ARM.com */ 369651SAndreas.Sandberg@ARM.com 379651SAndreas.Sandberg@ARM.com/* @file 389651SAndreas.Sandberg@ARM.com * Implementation of a TAGE branch predictor. TAGE is a global-history based 399651SAndreas.Sandberg@ARM.com * branch predictor. It features a PC-indexed bimodal predictor and N 409651SAndreas.Sandberg@ARM.com * partially tagged tables, indexed with a hash of the PC and the global 419651SAndreas.Sandberg@ARM.com * branch history. The different lengths of global branch history used to 429651SAndreas.Sandberg@ARM.com * index the partially tagged tables grow geometrically. A small path history 439651SAndreas.Sandberg@ARM.com * is also used in the hash. 449651SAndreas.Sandberg@ARM.com * 459651SAndreas.Sandberg@ARM.com * All TAGE tables are accessed in parallel, and the one using the longest 469651SAndreas.Sandberg@ARM.com * history that matches provides the prediction (some exceptions apply). 479651SAndreas.Sandberg@ARM.com * Entries are allocated in components using a longer history than the 489651SAndreas.Sandberg@ARM.com * one that predicted when the prediction is incorrect. 499651SAndreas.Sandberg@ARM.com */ 509651SAndreas.Sandberg@ARM.com 519651SAndreas.Sandberg@ARM.com#ifndef __CPU_PRED_TAGE 529651SAndreas.Sandberg@ARM.com#define __CPU_PRED_TAGE 539651SAndreas.Sandberg@ARM.com 549651SAndreas.Sandberg@ARM.com#include <vector> 559651SAndreas.Sandberg@ARM.com 569651SAndreas.Sandberg@ARM.com#include "base/types.hh" 579651SAndreas.Sandberg@ARM.com#include "cpu/pred/bpred_unit.hh" 589651SAndreas.Sandberg@ARM.com#include "cpu/pred/tage_base.hh" 599651SAndreas.Sandberg@ARM.com#include "params/TAGE.hh" 609651SAndreas.Sandberg@ARM.com 619651SAndreas.Sandberg@ARM.comclass TAGE: public BPredUnit 629651SAndreas.Sandberg@ARM.com{ 639651SAndreas.Sandberg@ARM.com protected: 649651SAndreas.Sandberg@ARM.com TAGEBase *tage; 659651SAndreas.Sandberg@ARM.com 669651SAndreas.Sandberg@ARM.com struct TageBranchInfo { 679651SAndreas.Sandberg@ARM.com TAGEBase::BranchInfo *tageBranchInfo; 689651SAndreas.Sandberg@ARM.com 699651SAndreas.Sandberg@ARM.com TageBranchInfo(TAGEBase &tage) : tageBranchInfo(tage.makeBranchInfo()) 709651SAndreas.Sandberg@ARM.com {} 719651SAndreas.Sandberg@ARM.com 729651SAndreas.Sandberg@ARM.com virtual ~TageBranchInfo() 739651SAndreas.Sandberg@ARM.com { 749651SAndreas.Sandberg@ARM.com delete tageBranchInfo; 759651SAndreas.Sandberg@ARM.com } 769651SAndreas.Sandberg@ARM.com }; 779651SAndreas.Sandberg@ARM.com 789651SAndreas.Sandberg@ARM.com virtual bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, 799651SAndreas.Sandberg@ARM.com void* &b); 809651SAndreas.Sandberg@ARM.com public: 819651SAndreas.Sandberg@ARM.com 829651SAndreas.Sandberg@ARM.com TAGE(const TAGEParams *params); 839651SAndreas.Sandberg@ARM.com 849651SAndreas.Sandberg@ARM.com // Base class methods. 859651SAndreas.Sandberg@ARM.com void uncondBranch(ThreadID tid, Addr br_pc, void* &bp_history) override; 869651SAndreas.Sandberg@ARM.com bool lookup(ThreadID tid, Addr branch_addr, void* &bp_history) override; 879651SAndreas.Sandberg@ARM.com void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override; 889651SAndreas.Sandberg@ARM.com void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, 899651SAndreas.Sandberg@ARM.com bool squashed, const StaticInstPtr & inst, 909651SAndreas.Sandberg@ARM.com Addr corrTarget) override; 919651SAndreas.Sandberg@ARM.com virtual void squash(ThreadID tid, void *bp_history) override; 929651SAndreas.Sandberg@ARM.com}; 939651SAndreas.Sandberg@ARM.com 949651SAndreas.Sandberg@ARM.com#endif // __CPU_PRED_TAGE 959651SAndreas.Sandberg@ARM.com