btb.cc revision 11425:e24d92c62860 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include "base/intmath.hh"
32#include "base/trace.hh"
33#include "cpu/pred/btb.hh"
34#include "debug/Fetch.hh"
35
36DefaultBTB::DefaultBTB(unsigned _numEntries,
37                       unsigned _tagBits,
38                       unsigned _instShiftAmt,
39                       unsigned _num_threads)
40    : numEntries(_numEntries),
41      tagBits(_tagBits),
42      instShiftAmt(_instShiftAmt),
43      log2NumThreads(floorLog2(_num_threads))
44{
45    DPRINTF(Fetch, "BTB: Creating BTB object.\n");
46
47    if (!isPowerOf2(numEntries)) {
48        fatal("BTB entries is not a power of 2!");
49    }
50
51    btb.resize(numEntries);
52
53    for (unsigned i = 0; i < numEntries; ++i) {
54        btb[i].valid = false;
55    }
56
57    idxMask = numEntries - 1;
58
59    tagMask = (1 << tagBits) - 1;
60
61    tagShiftAmt = instShiftAmt + floorLog2(numEntries);
62}
63
64void
65DefaultBTB::reset()
66{
67    for (unsigned i = 0; i < numEntries; ++i) {
68        btb[i].valid = false;
69    }
70}
71
72inline
73unsigned
74DefaultBTB::getIndex(Addr instPC, ThreadID tid)
75{
76    // Need to shift PC over by the word offset.
77    return ((instPC >> instShiftAmt)
78            ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
79            & idxMask;
80}
81
82inline
83Addr
84DefaultBTB::getTag(Addr instPC)
85{
86    return (instPC >> tagShiftAmt) & tagMask;
87}
88
89bool
90DefaultBTB::valid(Addr instPC, ThreadID tid)
91{
92    unsigned btb_idx = getIndex(instPC, tid);
93
94    Addr inst_tag = getTag(instPC);
95
96    assert(btb_idx < numEntries);
97
98    if (btb[btb_idx].valid
99        && inst_tag == btb[btb_idx].tag
100        && btb[btb_idx].tid == tid) {
101        return true;
102    } else {
103        return false;
104    }
105}
106
107// @todo Create some sort of return struct that has both whether or not the
108// address is valid, and also the address.  For now will just use addr = 0 to
109// represent invalid entry.
110TheISA::PCState
111DefaultBTB::lookup(Addr instPC, ThreadID tid)
112{
113    unsigned btb_idx = getIndex(instPC, tid);
114
115    Addr inst_tag = getTag(instPC);
116
117    assert(btb_idx < numEntries);
118
119    if (btb[btb_idx].valid
120        && inst_tag == btb[btb_idx].tag
121        && btb[btb_idx].tid == tid) {
122        return btb[btb_idx].target;
123    } else {
124        return 0;
125    }
126}
127
128void
129DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
130{
131    unsigned btb_idx = getIndex(instPC, tid);
132
133    assert(btb_idx < numEntries);
134
135    btb[btb_idx].tid = tid;
136    btb[btb_idx].valid = true;
137    btb[btb_idx].target = target;
138    btb[btb_idx].tag = getTag(instPC);
139}
140