pc_event.cc revision 8232
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
292665Ssaidi@eecs.umich.edu *          Steve Reinhardt
302SN/A */
312SN/A
322SN/A#include <algorithm>
332SN/A#include <map>
342SN/A#include <string>
352SN/A#include <utility>
362SN/A
375882Snate@binkert.org#include "base/debug.hh"
381492SN/A#include "base/trace.hh"
391858SN/A#include "config/full_system.hh"
401717SN/A#include "cpu/base.hh"
418229Snate@binkert.org#include "cpu/pc_event.hh"
422680Sktlim@umich.edu#include "cpu/thread_context.hh"
438232Snate@binkert.org#include "debug/PCEvent.hh"
444167Sbinkertn@umich.edu#include "sim/core.hh"
452190SN/A#include "sim/system.hh"
462SN/A
472SN/Ausing namespace std;
482SN/A
492SN/APCEventQueue::PCEventQueue()
502SN/A{}
512SN/A
522SN/APCEventQueue::~PCEventQueue()
532SN/A{}
542SN/A
552SN/Abool
562SN/APCEventQueue::remove(PCEvent *event)
572SN/A{
582SN/A    int removed = 0;
592SN/A    range_t range = equal_range(event);
602SN/A    for (iterator i = range.first; i != range.second; ++i) {
612SN/A        if (*i == event) {
622SN/A            DPRINTF(PCEvent, "PC based event removed at %#x: %s\n",
632SN/A                    event->pc(), event->descr());
642SN/A            pc_map.erase(i);
652SN/A            ++removed;
662SN/A        }
672SN/A    }
682SN/A
692SN/A    return removed > 0;
702SN/A}
712SN/A
722SN/Abool
732SN/APCEventQueue::schedule(PCEvent *event)
742SN/A{
752SN/A    pc_map.push_back(event);
762SN/A    sort(pc_map.begin(), pc_map.end(), MapCompare());
772SN/A
782SN/A    DPRINTF(PCEvent, "PC based event scheduled for %#x: %s\n",
792SN/A            event->pc(), event->descr());
802SN/A
812SN/A    return true;
822SN/A}
832SN/A
842SN/Abool
852680Sktlim@umich.eduPCEventQueue::doService(ThreadContext *tc)
862SN/A{
877720Sgblack@eecs.umich.edu    Addr pc = tc->instAddr() & ~0x3;
882SN/A    int serviced = 0;
892SN/A    range_t range = equal_range(pc);
902SN/A    for (iterator i = range.first; i != range.second; ++i) {
912SN/A        // Make sure that the pc wasn't changed as the side effect of
922SN/A        // another event.  This for example, prevents two invocations
932SN/A        // of the SkipFuncEvent.  Maybe we should have separate PC
942SN/A        // event queues for each processor?
957720Sgblack@eecs.umich.edu        if (pc != (tc->instAddr() & ~0x3))
962SN/A            continue;
972SN/A
982SN/A        DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
992SN/A                (*i)->pc(), (*i)->descr());
1002SN/A
1012680Sktlim@umich.edu        (*i)->process(tc);
1022SN/A        ++serviced;
1032SN/A    }
1042SN/A
1052SN/A    return serviced > 0;
1062SN/A}
1072SN/A
1082SN/Avoid
1092SN/APCEventQueue::dump() const
1102SN/A{
1112SN/A    const_iterator i = pc_map.begin();
1122SN/A    const_iterator e = pc_map.end();
1132SN/A
1142SN/A    for (; i != e; ++i)
1157823Ssteve.reinhardt@amd.com        cprintf("%d: event at %#x: %s\n", curTick(), (*i)->pc(),
1162SN/A                (*i)->descr());
1172SN/A}
1182SN/A
1192SN/APCEventQueue::range_t
1202SN/APCEventQueue::equal_range(Addr pc)
1212SN/A{
1222SN/A    return std::equal_range(pc_map.begin(), pc_map.end(), pc, MapCompare());
1232SN/A}
1242SN/A
1251885SN/ABreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr,
1261885SN/A                           bool del)
1271885SN/A    : PCEvent(q, desc, addr), remove(del)
1282SN/A{
1292SN/A}
1302SN/A
1312SN/Avoid
1322680Sktlim@umich.eduBreakPCEvent::process(ThreadContext *tc)
1332SN/A{
1342680Sktlim@umich.edu    StringWrap name(tc->getCpuPtr()->name() + ".break_event");
1351646SN/A    DPRINTFN("break event %s triggered\n", descr());
1368231Snate@binkert.org    Debug::breakpoint();
1372SN/A    if (remove)
1382SN/A        delete this;
1392SN/A}
1402SN/A
1411858SN/A#if FULL_SYSTEM
1422SN/Avoid
1432130SN/Asched_break_pc_sys(System *sys, Addr addr)
1442SN/A{
1451885SN/A    new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
1462SN/A}
1472SN/A
1482SN/Avoid
1492130SN/Asched_break_pc(Addr addr)
1502SN/A{
1512SN/A     for (vector<System *>::iterator sysi = System::systemList.begin();
1522SN/A          sysi != System::systemList.end(); ++sysi) {
1532SN/A         sched_break_pc_sys(*sysi, addr);
1542SN/A    }
1552SN/A
1562SN/A}
1572SN/A#endif
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