thread_state.hh revision 2292
1 2#ifndef __CPU_O3_THREAD_STATE_HH__ 3#define __CPU_O3_THREAD_STATE_HH__ 4 5#include "arch/faults.hh" 6#include "arch/isa_traits.hh" 7#include "cpu/exec_context.hh" 8#include "cpu/thread_state.hh" 9 10class Event; 11class Process; 12 13#if FULL_SYSTEM 14class EndQuiesceEvent; 15class FunctionProfile; 16class ProfileNode; 17#else 18class Process; 19class FunctionalMemory; 20#endif 21 22// In the new CPU case this may be quite small...It depends on what I define 23// ThreadState to be. Currently it's only the state that exists within 24// ExecContext basically. Leaves the interface and manipulation up to the 25// CPU. Not sure this is useful/flexible...probably can be if I can avoid 26// including state here that parts of the pipeline can't modify directly, 27// or at least don't let them. The only problem is for state that's needed 28// per thread, per structure. I.e. rename table, memreqs. 29// On the other hand, it might be nice to not have to pay the extra pointer 30// lookup to get frequently used state such as a memreq (that isn't used much 31// elsewhere)... 32 33// Maybe this ozone thread state should only really have committed state? 34// I need to think about why I'm using this and what it's useful for. Clearly 35// has benefits for SMT; basically serves same use as CPUExecContext. 36// Makes the ExecContext proxy easier. Gives organization/central access point 37// to state of a thread that can be accessed normally (i.e. not in-flight 38// stuff within a OoO processor). Does this need an XC proxy within it? 39template <class Impl> 40struct O3ThreadState : public ThreadState { 41 typedef ExecContext::Status Status; 42 typedef typename Impl::FullCPU FullCPU; 43 44 Status _status; 45 46 // Current instruction? 47 TheISA::MachInst inst; 48 private: 49 FullCPU *cpu; 50 public: 51 52 bool inSyscall; 53 54 bool trapPending; 55 56#if FULL_SYSTEM 57 O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem) 58 : ThreadState(-1, _thread_num, _mem), 59 inSyscall(0), trapPending(0) 60 { } 61#else 62 O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid) 63 : ThreadState(-1, _thread_num, NULL, _process, _asid), 64 cpu(_cpu), inSyscall(0), trapPending(0) 65 { } 66 67 O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 68 int _asid) 69 : ThreadState(-1, _thread_num, _mem, NULL, _asid), 70 cpu(_cpu), inSyscall(0), trapPending(0) 71 { } 72#endif 73 74 ExecContext *xcProxy; 75 76 ExecContext *getXCProxy() { return xcProxy; } 77 78 Status status() const { return _status; } 79 80 void setStatus(Status new_status) { _status = new_status; } 81 82#if !FULL_SYSTEM 83 84 Fault dummyTranslation(MemReqPtr &req) 85 { 86#if 0 87 assert((req->vaddr >> 48 & 0xffff) == 0); 88#endif 89 90 // put the asid in the upper 16 bits of the paddr 91 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 92 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 93 return NoFault; 94 } 95 Fault translateInstReq(MemReqPtr &req) 96 { 97 return dummyTranslation(req); 98 } 99 Fault translateDataReadReq(MemReqPtr &req) 100 { 101 return dummyTranslation(req); 102 } 103 Fault translateDataWriteReq(MemReqPtr &req) 104 { 105 return dummyTranslation(req); 106 } 107 108 bool validInstAddr(Addr addr) 109 { return process->validInstAddr(addr); } 110 111 bool validDataAddr(Addr addr) 112 { return process->validDataAddr(addr); } 113#else 114 Fault translateInstReq(MemReqPtr &req) 115 { 116 return cpu->itb->translate(req); 117 } 118 119 Fault translateDataReadReq(MemReqPtr &req) 120 { 121 return cpu->dtb->translate(req, false); 122 } 123 124 Fault translateDataWriteReq(MemReqPtr &req) 125 { 126 return cpu->dtb->translate(req, true); 127 } 128#endif 129 130 bool misspeculating() { return false; } 131 132 void setInst(TheISA::MachInst _inst) { inst = _inst; } 133 134 Counter readFuncExeInst() { return funcExeInst; } 135 136 void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } 137 138#if !FULL_SYSTEM 139 void syscall() { process->syscall(xcProxy); } 140#endif 141}; 142 143#endif // __CPU_O3_THREAD_STATE_HH__ 144