thread_state.hh revision 2669
12329SN/A/*
22329SN/A * Copyright (c) 2006 The Regents of The University of Michigan
32329SN/A * All rights reserved.
42329SN/A *
52329SN/A * Redistribution and use in source and binary forms, with or without
62329SN/A * modification, are permitted provided that the following conditions are
72329SN/A * met: redistributions of source code must retain the above copyright
82329SN/A * notice, this list of conditions and the following disclaimer;
92329SN/A * redistributions in binary form must reproduce the above copyright
102329SN/A * notice, this list of conditions and the following disclaimer in the
112329SN/A * documentation and/or other materials provided with the distribution;
122329SN/A * neither the name of the copyright holders nor the names of its
132329SN/A * contributors may be used to endorse or promote products derived from
142329SN/A * this software without specific prior written permission.
152329SN/A *
162329SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172329SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182329SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192329SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202329SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212329SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222329SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232329SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242329SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252329SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262329SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272329SN/A */
282292SN/A
292292SN/A#ifndef __CPU_O3_THREAD_STATE_HH__
302292SN/A#define __CPU_O3_THREAD_STATE_HH__
312292SN/A
322292SN/A#include "arch/faults.hh"
332292SN/A#include "arch/isa_traits.hh"
342292SN/A#include "cpu/exec_context.hh"
352292SN/A#include "cpu/thread_state.hh"
362292SN/A
372292SN/Aclass Event;
382292SN/Aclass Process;
392292SN/A
402292SN/A#if FULL_SYSTEM
412292SN/Aclass EndQuiesceEvent;
422292SN/Aclass FunctionProfile;
432292SN/Aclass ProfileNode;
442292SN/A#else
452329SN/Aclass FunctionalMemory;
462292SN/Aclass Process;
472292SN/A#endif
482292SN/A
492329SN/A/**
502329SN/A * Class that has various thread state, such as the status, the
512329SN/A * current instruction being processed, whether or not the thread has
522329SN/A * a trap pending or is being externally updated, the ExecContext
532329SN/A * proxy pointer, etc.  It also handles anything related to a specific
542329SN/A * thread's process, such as syscalls and checking valid addresses.
552329SN/A */
562292SN/Atemplate <class Impl>
572292SN/Astruct O3ThreadState : public ThreadState {
582292SN/A    typedef ExecContext::Status Status;
592292SN/A    typedef typename Impl::FullCPU FullCPU;
602292SN/A
612292SN/A    Status _status;
622292SN/A
632329SN/A    // Current instruction
642292SN/A    TheISA::MachInst inst;
652292SN/A  private:
662292SN/A    FullCPU *cpu;
672292SN/A  public:
682292SN/A
692292SN/A    bool inSyscall;
702292SN/A
712292SN/A    bool trapPending;
722292SN/A
732292SN/A#if FULL_SYSTEM
742292SN/A    O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
752292SN/A        : ThreadState(-1, _thread_num, _mem),
762292SN/A          inSyscall(0), trapPending(0)
772292SN/A    { }
782292SN/A#else
792292SN/A    O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
802669Sktlim@umich.edu        : ThreadState(-1, _thread_num, NULL, _process, _asid),
812292SN/A          cpu(_cpu), inSyscall(0), trapPending(0)
822292SN/A    { }
832292SN/A
842292SN/A    O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
852292SN/A                  int _asid)
862292SN/A        : ThreadState(-1, _thread_num, _mem, NULL, _asid),
872292SN/A          cpu(_cpu), inSyscall(0), trapPending(0)
882292SN/A    { }
892292SN/A#endif
902292SN/A
912292SN/A    ExecContext *xcProxy;
922292SN/A
932292SN/A    ExecContext *getXCProxy() { return xcProxy; }
942292SN/A
952292SN/A    Status status() const { return _status; }
962292SN/A
972292SN/A    void setStatus(Status new_status) { _status = new_status; }
982292SN/A
992292SN/A    bool misspeculating() { return false; }
1002292SN/A
1012292SN/A    void setInst(TheISA::MachInst _inst) { inst = _inst; }
1022292SN/A
1032292SN/A    Counter readFuncExeInst() { return funcExeInst; }
1042292SN/A
1052292SN/A    void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
1062292SN/A
1072292SN/A#if !FULL_SYSTEM
1082669Sktlim@umich.edu    void syscall(int64_t callnum) { process->syscall(callnum, xcProxy); }
1092292SN/A#endif
1102292SN/A};
1112292SN/A
1122292SN/A#endif // __CPU_O3_THREAD_STATE_HH__
113