thread_context_impl.hh revision 9436:4a0223da4924 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "cpu/o3/thread_context.hh"
48#include "cpu/quiesce_event.hh"
49#include "debug/O3CPU.hh"
50
51template <class Impl>
52FSTranslatingPortProxy&
53O3ThreadContext<Impl>::getVirtProxy()
54{
55    return thread->getVirtProxy();
56}
57
58template <class Impl>
59void
60O3ThreadContext<Impl>::dumpFuncProfile()
61{
62    thread->dumpFuncProfile();
63}
64
65template <class Impl>
66void
67O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
68{
69    // some things should already be set up
70    assert(getSystemPtr() == old_context->getSystemPtr());
71    assert(getProcessPtr() == old_context->getProcessPtr());
72
73    // copy over functional state
74    setStatus(old_context->status());
75    copyArchRegs(old_context);
76    setContextId(old_context->contextId());
77    setThreadId(old_context->threadId());
78
79    if (FullSystem) {
80        EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
81        if (other_quiesce) {
82            // Point the quiesce event's TC at this TC so that it wakes up
83            // the proper CPU.
84            other_quiesce->tc = this;
85        }
86        if (thread->quiesceEvent) {
87            thread->quiesceEvent->tc = this;
88        }
89
90        // Transfer kernel stats from one CPU to the other.
91        thread->kernelStats = old_context->getKernelStats();
92    } else {
93        thread->funcExeInst = old_context->readFuncExeInst();
94    }
95
96    old_context->setStatus(ThreadContext::Halted);
97
98    thread->noSquashFromTC = false;
99    thread->trapPending = false;
100}
101
102template <class Impl>
103void
104O3ThreadContext<Impl>::activate(Cycles delay)
105{
106    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
107            threadId());
108
109    if (thread->status() == ThreadContext::Active)
110        return;
111
112    thread->lastActivate = curTick();
113    thread->setStatus(ThreadContext::Active);
114
115    // status() == Suspended
116    cpu->activateContext(thread->threadId(), delay);
117}
118
119template <class Impl>
120void
121O3ThreadContext<Impl>::suspend(Cycles delay)
122{
123    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
124            threadId());
125
126    if (thread->status() == ThreadContext::Suspended)
127        return;
128
129    thread->lastActivate = curTick();
130    thread->lastSuspend = curTick();
131
132    thread->setStatus(ThreadContext::Suspended);
133    cpu->suspendContext(thread->threadId());
134}
135
136template <class Impl>
137void
138O3ThreadContext<Impl>::halt(Cycles delay)
139{
140    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
141            threadId());
142
143    if (thread->status() == ThreadContext::Halted)
144        return;
145
146    thread->setStatus(ThreadContext::Halted);
147    cpu->haltContext(thread->threadId());
148}
149
150template <class Impl>
151void
152O3ThreadContext<Impl>::regStats(const std::string &name)
153{
154    if (FullSystem) {
155        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
156        thread->kernelStats->regStats(name + ".kern");
157    }
158}
159
160template <class Impl>
161Tick
162O3ThreadContext<Impl>::readLastActivate()
163{
164    return thread->lastActivate;
165}
166
167template <class Impl>
168Tick
169O3ThreadContext<Impl>::readLastSuspend()
170{
171    return thread->lastSuspend;
172}
173
174template <class Impl>
175void
176O3ThreadContext<Impl>::profileClear()
177{
178    thread->profileClear();
179}
180
181template <class Impl>
182void
183O3ThreadContext<Impl>::profileSample()
184{
185    thread->profileSample();
186}
187
188template <class Impl>
189void
190O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
191{
192    // Prevent squashing
193    thread->noSquashFromTC = true;
194    TheISA::copyRegs(tc, this);
195    thread->noSquashFromTC = false;
196
197    if (!FullSystem)
198        this->thread->funcExeInst = tc->readFuncExeInst();
199}
200
201template <class Impl>
202void
203O3ThreadContext<Impl>::clearArchRegs()
204{
205    cpu->isa[thread->threadId()]->clear();
206}
207
208template <class Impl>
209uint64_t
210O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
211{
212    return cpu->readArchIntReg(reg_idx, thread->threadId());
213}
214
215template <class Impl>
216TheISA::FloatReg
217O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
218{
219    return cpu->readArchFloatReg(reg_idx, thread->threadId());
220}
221
222template <class Impl>
223TheISA::FloatRegBits
224O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
225{
226    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
227}
228
229template <class Impl>
230void
231O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
232{
233    cpu->setArchIntReg(reg_idx, val, thread->threadId());
234
235    conditionalSquash();
236}
237
238template <class Impl>
239void
240O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
241{
242    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
243
244    conditionalSquash();
245}
246
247template <class Impl>
248void
249O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
250{
251    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
252
253    conditionalSquash();
254}
255
256template <class Impl>
257void
258O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
259{
260    cpu->pcState(val, thread->threadId());
261
262    conditionalSquash();
263}
264
265template <class Impl>
266void
267O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
268{
269    cpu->pcState(val, thread->threadId());
270
271    conditionalSquash();
272}
273
274template <class Impl>
275int
276O3ThreadContext<Impl>::flattenIntIndex(int reg)
277{
278    return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
279}
280
281template <class Impl>
282int
283O3ThreadContext<Impl>::flattenFloatIndex(int reg)
284{
285    return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
286}
287
288template <class Impl>
289void
290O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
291{
292    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
293
294    conditionalSquash();
295}
296
297template <class Impl>
298void
299O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
300{
301    cpu->setMiscReg(misc_reg, val, thread->threadId());
302
303    conditionalSquash();
304}
305
306