thread_context_impl.hh revision 8852 
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "config/use_checker.hh"
48#include "cpu/o3/thread_context.hh"
49#include "cpu/quiesce_event.hh"
50#include "debug/O3CPU.hh"
51
52template <class Impl>
53FSTranslatingPortProxy&
54O3ThreadContext<Impl>::getVirtProxy()
55{
56    return thread->getVirtProxy();
57}
58
59template <class Impl>
60void
61O3ThreadContext<Impl>::dumpFuncProfile()
62{
63    thread->dumpFuncProfile();
64}
65
66template <class Impl>
67void
68O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
69{
70    // some things should already be set up
71    assert(getSystemPtr() == old_context->getSystemPtr());
72    assert(getProcessPtr() == old_context->getProcessPtr());
73
74    // copy over functional state
75    setStatus(old_context->status());
76    copyArchRegs(old_context);
77    setContextId(old_context->contextId());
78    setThreadId(old_context->threadId());
79
80    if (FullSystem) {
81        EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
82        if (other_quiesce) {
83            // Point the quiesce event's TC at this TC so that it wakes up
84            // the proper CPU.
85            other_quiesce->tc = this;
86        }
87        if (thread->quiesceEvent) {
88            thread->quiesceEvent->tc = this;
89        }
90
91        // Transfer kernel stats from one CPU to the other.
92        thread->kernelStats = old_context->getKernelStats();
93        cpu->lockFlag = false;
94    } else {
95        thread->funcExeInst = old_context->readFuncExeInst();
96    }
97
98    old_context->setStatus(ThreadContext::Halted);
99
100    thread->inSyscall = false;
101    thread->trapPending = false;
102}
103
104template <class Impl>
105void
106O3ThreadContext<Impl>::activate(int delay)
107{
108    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
109            threadId());
110
111    if (thread->status() == ThreadContext::Active)
112        return;
113
114    thread->lastActivate = curTick();
115    thread->setStatus(ThreadContext::Active);
116
117    // status() == Suspended
118    cpu->activateContext(thread->threadId(), delay);
119}
120
121template <class Impl>
122void
123O3ThreadContext<Impl>::suspend(int delay)
124{
125    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
126            threadId());
127
128    if (thread->status() == ThreadContext::Suspended)
129        return;
130
131    thread->lastActivate = curTick();
132    thread->lastSuspend = curTick();
133
134    thread->setStatus(ThreadContext::Suspended);
135    cpu->suspendContext(thread->threadId());
136}
137
138template <class Impl>
139void
140O3ThreadContext<Impl>::halt(int delay)
141{
142    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
143            threadId());
144
145    if (thread->status() == ThreadContext::Halted)
146        return;
147
148    thread->setStatus(ThreadContext::Halted);
149    cpu->haltContext(thread->threadId());
150}
151
152template <class Impl>
153void
154O3ThreadContext<Impl>::regStats(const std::string &name)
155{
156    if (FullSystem) {
157        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
158        thread->kernelStats->regStats(name + ".kern");
159    }
160}
161
162template <class Impl>
163void
164O3ThreadContext<Impl>::serialize(std::ostream &os)
165{
166    if (FullSystem && thread->kernelStats)
167        thread->kernelStats->serialize(os);
168}
169
170template <class Impl>
171void
172O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
173{
174    if (FullSystem && thread->kernelStats)
175        thread->kernelStats->unserialize(cp, section);
176}
177
178template <class Impl>
179Tick
180O3ThreadContext<Impl>::readLastActivate()
181{
182    return thread->lastActivate;
183}
184
185template <class Impl>
186Tick
187O3ThreadContext<Impl>::readLastSuspend()
188{
189    return thread->lastSuspend;
190}
191
192template <class Impl>
193void
194O3ThreadContext<Impl>::profileClear()
195{
196    thread->profileClear();
197}
198
199template <class Impl>
200void
201O3ThreadContext<Impl>::profileSample()
202{
203    thread->profileSample();
204}
205
206template <class Impl>
207void
208O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
209{
210    // Prevent squashing
211    thread->inSyscall = true;
212    TheISA::copyRegs(tc, this);
213    thread->inSyscall = false;
214
215    if (!FullSystem)
216        this->thread->funcExeInst = tc->readFuncExeInst();
217}
218
219template <class Impl>
220void
221O3ThreadContext<Impl>::clearArchRegs()
222{
223    cpu->isa[thread->threadId()].clear();
224}
225
226template <class Impl>
227uint64_t
228O3ThreadContext<Impl>::readIntReg(int reg_idx)
229{
230    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
231    return cpu->readArchIntReg(reg_idx, thread->threadId());
232}
233
234template <class Impl>
235TheISA::FloatReg
236O3ThreadContext<Impl>::readFloatReg(int reg_idx)
237{
238    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
239    return cpu->readArchFloatReg(reg_idx, thread->threadId());
240}
241
242template <class Impl>
243TheISA::FloatRegBits
244O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
245{
246    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
247    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
248}
249
250template <class Impl>
251void
252O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
253{
254    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
255    cpu->setArchIntReg(reg_idx, val, thread->threadId());
256
257    // Squash if we're not already in a state update mode.
258    if (!thread->trapPending && !thread->inSyscall) {
259        cpu->squashFromTC(thread->threadId());
260    }
261}
262
263template <class Impl>
264void
265O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
266{
267    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
268    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
269
270    if (!thread->trapPending && !thread->inSyscall) {
271        cpu->squashFromTC(thread->threadId());
272    }
273}
274
275template <class Impl>
276void
277O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
278{
279    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
280    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
281
282    // Squash if we're not already in a state update mode.
283    if (!thread->trapPending && !thread->inSyscall) {
284        cpu->squashFromTC(thread->threadId());
285    }
286}
287
288template <class Impl>
289void
290O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
291{
292    cpu->pcState(val, thread->threadId());
293
294    // Squash if we're not already in a state update mode.
295    if (!thread->trapPending && !thread->inSyscall) {
296        cpu->squashFromTC(thread->threadId());
297    }
298}
299
300#if USE_CHECKER
301template <class Impl>
302void
303O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
304{
305    cpu->pcState(val, thread->threadId());
306
307    // Squash if we're not already in a state update mode.
308    if (!thread->trapPending && !thread->inSyscall) {
309        cpu->squashFromTC(thread->threadId());
310    }
311}
312#endif
313
314template <class Impl>
315int
316O3ThreadContext<Impl>::flattenIntIndex(int reg)
317{
318    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
319}
320
321template <class Impl>
322int
323O3ThreadContext<Impl>::flattenFloatIndex(int reg)
324{
325    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
326}
327
328template <class Impl>
329void
330O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
331{
332    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
333
334    // Squash if we're not already in a state update mode.
335    if (!thread->trapPending && !thread->inSyscall) {
336        cpu->squashFromTC(thread->threadId());
337    }
338}
339
340template <class Impl>
341void
342O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
343{
344    cpu->setMiscReg(misc_reg, val, thread->threadId());
345
346    // Squash if we're not already in a state update mode.
347    if (!thread->trapPending && !thread->inSyscall) {
348        cpu->squashFromTC(thread->threadId());
349    }
350}
351
352