thread_context_impl.hh revision 8777:dd43f1c9fa0a 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include "arch/registers.hh"
45#include "config/the_isa.hh"
46#include "cpu/o3/thread_context.hh"
47#include "cpu/quiesce_event.hh"
48#include "debug/O3CPU.hh"
49
50template <class Impl>
51VirtualPort *
52O3ThreadContext<Impl>::getVirtPort()
53{
54    return thread->getVirtPort();
55}
56
57template <class Impl>
58void
59O3ThreadContext<Impl>::dumpFuncProfile()
60{
61    thread->dumpFuncProfile();
62}
63
64template <class Impl>
65void
66O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
67{
68    // some things should already be set up
69#if FULL_SYSTEM
70    assert(getSystemPtr() == old_context->getSystemPtr());
71#endif
72    assert(getProcessPtr() == old_context->getProcessPtr());
73
74    // copy over functional state
75    setStatus(old_context->status());
76    copyArchRegs(old_context);
77    setContextId(old_context->contextId());
78    setThreadId(old_context->threadId());
79
80#if !FULL_SYSTEM
81    thread->funcExeInst = old_context->readFuncExeInst();
82#else
83    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
84    if (other_quiesce) {
85        // Point the quiesce event's TC at this TC so that it wakes up
86        // the proper CPU.
87        other_quiesce->tc = this;
88    }
89    if (thread->quiesceEvent) {
90        thread->quiesceEvent->tc = this;
91    }
92
93    // Transfer kernel stats from one CPU to the other.
94    thread->kernelStats = old_context->getKernelStats();
95//    storeCondFailures = 0;
96    cpu->lockFlag = false;
97#endif
98
99    old_context->setStatus(ThreadContext::Halted);
100
101    thread->inSyscall = false;
102    thread->trapPending = false;
103}
104
105template <class Impl>
106void
107O3ThreadContext<Impl>::activate(int delay)
108{
109    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
110            threadId());
111
112    if (thread->status() == ThreadContext::Active)
113        return;
114
115#if FULL_SYSTEM
116    thread->lastActivate = curTick();
117#endif
118
119    thread->setStatus(ThreadContext::Active);
120
121    // status() == Suspended
122    cpu->activateContext(thread->threadId(), delay);
123}
124
125template <class Impl>
126void
127O3ThreadContext<Impl>::suspend(int delay)
128{
129    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
130            threadId());
131
132    if (thread->status() == ThreadContext::Suspended)
133        return;
134
135#if FULL_SYSTEM
136    thread->lastActivate = curTick();
137    thread->lastSuspend = curTick();
138#endif
139/*
140#if FULL_SYSTEM
141    // Don't change the status from active if there are pending interrupts
142    if (cpu->checkInterrupts()) {
143        assert(status() == ThreadContext::Active);
144        return;
145    }
146#endif
147*/
148    thread->setStatus(ThreadContext::Suspended);
149    cpu->suspendContext(thread->threadId());
150}
151
152template <class Impl>
153void
154O3ThreadContext<Impl>::halt(int delay)
155{
156    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
157            threadId());
158
159    if (thread->status() == ThreadContext::Halted)
160        return;
161
162    thread->setStatus(ThreadContext::Halted);
163    cpu->haltContext(thread->threadId());
164}
165
166template <class Impl>
167void
168O3ThreadContext<Impl>::regStats(const std::string &name)
169{
170#if FULL_SYSTEM
171    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
172    thread->kernelStats->regStats(name + ".kern");
173#endif
174}
175
176template <class Impl>
177void
178O3ThreadContext<Impl>::serialize(std::ostream &os)
179{
180#if FULL_SYSTEM
181    if (thread->kernelStats)
182        thread->kernelStats->serialize(os);
183#endif
184
185}
186
187template <class Impl>
188void
189O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
190{
191#if FULL_SYSTEM
192    if (thread->kernelStats)
193        thread->kernelStats->unserialize(cp, section);
194#endif
195
196}
197
198template <class Impl>
199Tick
200O3ThreadContext<Impl>::readLastActivate()
201{
202    return thread->lastActivate;
203}
204
205template <class Impl>
206Tick
207O3ThreadContext<Impl>::readLastSuspend()
208{
209    return thread->lastSuspend;
210}
211
212template <class Impl>
213void
214O3ThreadContext<Impl>::profileClear()
215{
216    thread->profileClear();
217}
218
219template <class Impl>
220void
221O3ThreadContext<Impl>::profileSample()
222{
223    thread->profileSample();
224}
225
226template <class Impl>
227void
228O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
229{
230    // Prevent squashing
231    thread->inSyscall = true;
232    TheISA::copyRegs(tc, this);
233    thread->inSyscall = false;
234
235#if !FULL_SYSTEM
236    this->thread->funcExeInst = tc->readFuncExeInst();
237#endif
238}
239
240template <class Impl>
241void
242O3ThreadContext<Impl>::clearArchRegs()
243{
244    cpu->isa[thread->threadId()].clear();
245}
246
247template <class Impl>
248uint64_t
249O3ThreadContext<Impl>::readIntReg(int reg_idx)
250{
251    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
252    return cpu->readArchIntReg(reg_idx, thread->threadId());
253}
254
255template <class Impl>
256TheISA::FloatReg
257O3ThreadContext<Impl>::readFloatReg(int reg_idx)
258{
259    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
260    return cpu->readArchFloatReg(reg_idx, thread->threadId());
261}
262
263template <class Impl>
264TheISA::FloatRegBits
265O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
266{
267    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
268    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
269}
270
271template <class Impl>
272void
273O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
274{
275    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
276    cpu->setArchIntReg(reg_idx, val, thread->threadId());
277
278    // Squash if we're not already in a state update mode.
279    if (!thread->trapPending && !thread->inSyscall) {
280        cpu->squashFromTC(thread->threadId());
281    }
282}
283
284template <class Impl>
285void
286O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
287{
288    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
289    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
290
291    if (!thread->trapPending && !thread->inSyscall) {
292        cpu->squashFromTC(thread->threadId());
293    }
294}
295
296template <class Impl>
297void
298O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
299{
300    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
301    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
302
303    // Squash if we're not already in a state update mode.
304    if (!thread->trapPending && !thread->inSyscall) {
305        cpu->squashFromTC(thread->threadId());
306    }
307}
308
309template <class Impl>
310void
311O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
312{
313    cpu->pcState(val, thread->threadId());
314
315    // Squash if we're not already in a state update mode.
316    if (!thread->trapPending && !thread->inSyscall) {
317        cpu->squashFromTC(thread->threadId());
318    }
319}
320
321template <class Impl>
322int
323O3ThreadContext<Impl>::flattenIntIndex(int reg)
324{
325    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
326}
327
328template <class Impl>
329int
330O3ThreadContext<Impl>::flattenFloatIndex(int reg)
331{
332    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
333}
334
335template <class Impl>
336void
337O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
338{
339    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
340
341    // Squash if we're not already in a state update mode.
342    if (!thread->trapPending && !thread->inSyscall) {
343        cpu->squashFromTC(thread->threadId());
344    }
345}
346
347template <class Impl>
348void
349O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
350{
351    cpu->setMiscReg(misc_reg, val, thread->threadId());
352
353    // Squash if we're not already in a state update mode.
354    if (!thread->trapPending && !thread->inSyscall) {
355        cpu->squashFromTC(thread->threadId());
356    }
357}
358
359