thread_context_impl.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "arch/registers.hh"
33#include "config/the_isa.hh"
34#include "cpu/o3/thread_context.hh"
35#include "cpu/quiesce_event.hh"
36
37#if FULL_SYSTEM
38template <class Impl>
39VirtualPort *
40O3ThreadContext<Impl>::getVirtPort()
41{
42    return thread->getVirtPort();
43}
44
45template <class Impl>
46void
47O3ThreadContext<Impl>::dumpFuncProfile()
48{
49    thread->dumpFuncProfile();
50}
51#endif
52
53template <class Impl>
54void
55O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
56{
57    // some things should already be set up
58#if FULL_SYSTEM
59    assert(getSystemPtr() == old_context->getSystemPtr());
60#else
61    assert(getProcessPtr() == old_context->getProcessPtr());
62#endif
63
64    // copy over functional state
65    setStatus(old_context->status());
66    copyArchRegs(old_context);
67    setContextId(old_context->contextId());
68    setThreadId(old_context->threadId());
69
70#if !FULL_SYSTEM
71    thread->funcExeInst = old_context->readFuncExeInst();
72#else
73    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
74    if (other_quiesce) {
75        // Point the quiesce event's TC at this TC so that it wakes up
76        // the proper CPU.
77        other_quiesce->tc = this;
78    }
79    if (thread->quiesceEvent) {
80        thread->quiesceEvent->tc = this;
81    }
82
83    // Transfer kernel stats from one CPU to the other.
84    thread->kernelStats = old_context->getKernelStats();
85//    storeCondFailures = 0;
86    cpu->lockFlag = false;
87#endif
88
89    old_context->setStatus(ThreadContext::Halted);
90
91    thread->inSyscall = false;
92    thread->trapPending = false;
93}
94
95template <class Impl>
96void
97O3ThreadContext<Impl>::activate(int delay)
98{
99    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
100            threadId());
101
102    if (thread->status() == ThreadContext::Active)
103        return;
104
105#if FULL_SYSTEM
106    thread->lastActivate = curTick;
107#endif
108
109    thread->setStatus(ThreadContext::Active);
110
111    // status() == Suspended
112    cpu->activateContext(thread->threadId(), delay);
113}
114
115template <class Impl>
116void
117O3ThreadContext<Impl>::suspend(int delay)
118{
119    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
120            threadId());
121
122    if (thread->status() == ThreadContext::Suspended)
123        return;
124
125#if FULL_SYSTEM
126    thread->lastActivate = curTick;
127    thread->lastSuspend = curTick;
128#endif
129/*
130#if FULL_SYSTEM
131    // Don't change the status from active if there are pending interrupts
132    if (cpu->checkInterrupts()) {
133        assert(status() == ThreadContext::Active);
134        return;
135    }
136#endif
137*/
138    thread->setStatus(ThreadContext::Suspended);
139    cpu->suspendContext(thread->threadId());
140}
141
142template <class Impl>
143void
144O3ThreadContext<Impl>::halt(int delay)
145{
146    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
147            threadId());
148
149    if (thread->status() == ThreadContext::Halted)
150        return;
151
152    thread->setStatus(ThreadContext::Halted);
153    cpu->haltContext(thread->threadId());
154}
155
156template <class Impl>
157void
158O3ThreadContext<Impl>::regStats(const std::string &name)
159{
160#if FULL_SYSTEM
161    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
162    thread->kernelStats->regStats(name + ".kern");
163#endif
164}
165
166template <class Impl>
167void
168O3ThreadContext<Impl>::serialize(std::ostream &os)
169{
170#if FULL_SYSTEM
171    if (thread->kernelStats)
172        thread->kernelStats->serialize(os);
173#endif
174
175}
176
177template <class Impl>
178void
179O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
180{
181#if FULL_SYSTEM
182    if (thread->kernelStats)
183        thread->kernelStats->unserialize(cp, section);
184#endif
185
186}
187
188#if FULL_SYSTEM
189template <class Impl>
190Tick
191O3ThreadContext<Impl>::readLastActivate()
192{
193    return thread->lastActivate;
194}
195
196template <class Impl>
197Tick
198O3ThreadContext<Impl>::readLastSuspend()
199{
200    return thread->lastSuspend;
201}
202
203template <class Impl>
204void
205O3ThreadContext<Impl>::profileClear()
206{
207    thread->profileClear();
208}
209
210template <class Impl>
211void
212O3ThreadContext<Impl>::profileSample()
213{
214    thread->profileSample();
215}
216#endif
217
218template <class Impl>
219void
220O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
221{
222    // This function will mess things up unless the ROB is empty and
223    // there are no instructions in the pipeline.
224    ThreadID tid = thread->threadId();
225    PhysRegIndex renamed_reg;
226
227    // First loop through the integer registers.
228    for (int i = 0; i < TheISA::NumIntRegs; ++i) {
229        renamed_reg = cpu->renameMap[tid].lookup(i);
230
231        DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
232                "now has data %lli.\n",
233                renamed_reg, cpu->readIntReg(renamed_reg),
234                tc->readIntReg(i));
235
236        cpu->setIntReg(renamed_reg, tc->readIntReg(i));
237    }
238
239    // Then loop through the floating point registers.
240    for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
241        renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
242        cpu->setFloatRegBits(renamed_reg,
243                             tc->readFloatRegBits(i));
244    }
245
246    // Copy the misc regs.
247    TheISA::copyMiscRegs(tc, this);
248
249    // Then finally set the PC, the next PC, the nextNPC, the micropc, and the
250    // next micropc.
251    cpu->pcState(tc->pcState(), tid);
252#if !FULL_SYSTEM
253    this->thread->funcExeInst = tc->readFuncExeInst();
254#endif
255}
256
257template <class Impl>
258void
259O3ThreadContext<Impl>::clearArchRegs()
260{}
261
262template <class Impl>
263uint64_t
264O3ThreadContext<Impl>::readIntReg(int reg_idx)
265{
266    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
267    return cpu->readArchIntReg(reg_idx, thread->threadId());
268}
269
270template <class Impl>
271TheISA::FloatReg
272O3ThreadContext<Impl>::readFloatReg(int reg_idx)
273{
274    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
275    return cpu->readArchFloatReg(reg_idx, thread->threadId());
276}
277
278template <class Impl>
279TheISA::FloatRegBits
280O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
281{
282    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
283    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
284}
285
286template <class Impl>
287void
288O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
289{
290    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
291    cpu->setArchIntReg(reg_idx, val, thread->threadId());
292
293    // Squash if we're not already in a state update mode.
294    if (!thread->trapPending && !thread->inSyscall) {
295        cpu->squashFromTC(thread->threadId());
296    }
297}
298
299template <class Impl>
300void
301O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
302{
303    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
304    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
305
306    if (!thread->trapPending && !thread->inSyscall) {
307        cpu->squashFromTC(thread->threadId());
308    }
309}
310
311template <class Impl>
312void
313O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
314{
315    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
316    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
317
318    // Squash if we're not already in a state update mode.
319    if (!thread->trapPending && !thread->inSyscall) {
320        cpu->squashFromTC(thread->threadId());
321    }
322}
323
324template <class Impl>
325void
326O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
327{
328    cpu->pcState(val, thread->threadId());
329
330    // Squash if we're not already in a state update mode.
331    if (!thread->trapPending && !thread->inSyscall) {
332        cpu->squashFromTC(thread->threadId());
333    }
334}
335
336template <class Impl>
337int
338O3ThreadContext<Impl>::flattenIntIndex(int reg)
339{
340    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
341}
342
343template <class Impl>
344int
345O3ThreadContext<Impl>::flattenFloatIndex(int reg)
346{
347    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
348}
349
350template <class Impl>
351void
352O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
353{
354    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
355
356    // Squash if we're not already in a state update mode.
357    if (!thread->trapPending && !thread->inSyscall) {
358        cpu->squashFromTC(thread->threadId());
359    }
360}
361
362template <class Impl>
363void
364O3ThreadContext<Impl>::setMiscReg(int misc_reg,
365                                                const MiscReg &val)
366{
367    cpu->setMiscReg(misc_reg, val, thread->threadId());
368
369    // Squash if we're not already in a state update mode.
370    if (!thread->trapPending && !thread->inSyscall) {
371        cpu->squashFromTC(thread->threadId());
372    }
373}
374
375