thread_context_impl.hh revision 14022
1/* 2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 47 48#include "arch/generic/traits.hh" 49#include "arch/kernel_stats.hh" 50#include "arch/registers.hh" 51#include "config/the_isa.hh" 52#include "cpu/o3/thread_context.hh" 53#include "cpu/quiesce_event.hh" 54#include "debug/O3CPU.hh" 55 56template <class Impl> 57PortProxy& 58O3ThreadContext<Impl>::getVirtProxy() 59{ 60 return thread->getVirtProxy(); 61} 62 63template <class Impl> 64void 65O3ThreadContext<Impl>::dumpFuncProfile() 66{ 67 thread->dumpFuncProfile(); 68} 69 70template <class Impl> 71void 72O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 73{ 74 ::takeOverFrom(*this, *old_context); 75 TheISA::Decoder *newDecoder = getDecoderPtr(); 76 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 77 newDecoder->takeOverFrom(oldDecoder); 78 79 thread->kernelStats = old_context->getKernelStats(); 80 thread->funcExeInst = old_context->readFuncExeInst(); 81 82 thread->noSquashFromTC = false; 83 thread->trapPending = false; 84} 85 86template <class Impl> 87void 88O3ThreadContext<Impl>::activate() 89{ 90 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 91 threadId()); 92 93 if (thread->status() == ThreadContext::Active) 94 return; 95 96 thread->lastActivate = curTick(); 97 thread->setStatus(ThreadContext::Active); 98 99 // status() == Suspended 100 cpu->activateContext(thread->threadId()); 101} 102 103template <class Impl> 104void 105O3ThreadContext<Impl>::suspend() 106{ 107 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 108 threadId()); 109 110 if (thread->status() == ThreadContext::Suspended) 111 return; 112 113 if (cpu->isDraining()) { 114 DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n"); 115 return; 116 } 117 118 thread->lastActivate = curTick(); 119 thread->lastSuspend = curTick(); 120 121 thread->setStatus(ThreadContext::Suspended); 122 cpu->suspendContext(thread->threadId()); 123} 124 125template <class Impl> 126void 127O3ThreadContext<Impl>::halt() 128{ 129 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId()); 130 131 if (thread->status() == ThreadContext::Halting || 132 thread->status() == ThreadContext::Halted) 133 return; 134 135 // the thread is not going to halt/terminate immediately in this cycle. 136 // The thread will be removed after an exit trap is processed 137 // (e.g., after trapLatency cycles). Until then, the thread's status 138 // will be Halting. 139 thread->setStatus(ThreadContext::Halting); 140 141 // add this thread to the exiting list to mark that it is trying to exit. 142 cpu->addThreadToExitingList(thread->threadId()); 143} 144 145template <class Impl> 146void 147O3ThreadContext<Impl>::regStats(const std::string &name) 148{ 149 if (FullSystem) { 150 thread->kernelStats = new TheISA::Kernel::Statistics(); 151 thread->kernelStats->regStats(name + ".kern"); 152 } 153} 154 155template <class Impl> 156Tick 157O3ThreadContext<Impl>::readLastActivate() 158{ 159 return thread->lastActivate; 160} 161 162template <class Impl> 163Tick 164O3ThreadContext<Impl>::readLastSuspend() 165{ 166 return thread->lastSuspend; 167} 168 169template <class Impl> 170void 171O3ThreadContext<Impl>::profileClear() 172{ 173 thread->profileClear(); 174} 175 176template <class Impl> 177void 178O3ThreadContext<Impl>::profileSample() 179{ 180 thread->profileSample(); 181} 182 183template <class Impl> 184void 185O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 186{ 187 // Set vector renaming mode before copying registers 188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState())); 189 190 // Prevent squashing 191 thread->noSquashFromTC = true; 192 TheISA::copyRegs(tc, this); 193 thread->noSquashFromTC = false; 194 195 if (!FullSystem) 196 this->thread->funcExeInst = tc->readFuncExeInst(); 197} 198 199template <class Impl> 200void 201O3ThreadContext<Impl>::clearArchRegs() 202{ 203 cpu->isa[thread->threadId()]->clear(); 204} 205 206template <class Impl> 207RegVal 208O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const 209{ 210 return cpu->readArchIntReg(reg_idx, thread->threadId()); 211} 212 213template <class Impl> 214RegVal 215O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const 216{ 217 return cpu->readArchFloatReg(reg_idx, thread->threadId()); 218} 219 220template <class Impl> 221const TheISA::VecRegContainer& 222O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const 223{ 224 return cpu->readArchVecReg(reg_id, thread->threadId()); 225} 226 227template <class Impl> 228TheISA::VecRegContainer& 229O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id) 230{ 231 return cpu->getWritableArchVecReg(reg_id, thread->threadId()); 232} 233 234template <class Impl> 235const TheISA::VecElem& 236O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx, 237 const ElemIndex& elemIndex) const 238{ 239 return cpu->readArchVecElem(idx, elemIndex, thread->threadId()); 240} 241 242template <class Impl> 243const TheISA::VecPredRegContainer& 244O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const 245{ 246 return cpu->readArchVecPredReg(reg_id, thread->threadId()); 247} 248 249template <class Impl> 250TheISA::VecPredRegContainer& 251O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id) 252{ 253 return cpu->getWritableArchVecPredReg(reg_id, thread->threadId()); 254} 255 256template <class Impl> 257RegVal 258O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const 259{ 260 return cpu->readArchCCReg(reg_idx, thread->threadId()); 261} 262 263template <class Impl> 264void 265O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val) 266{ 267 cpu->setArchIntReg(reg_idx, val, thread->threadId()); 268 269 conditionalSquash(); 270} 271 272template <class Impl> 273void 274O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val) 275{ 276 cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 277 278 conditionalSquash(); 279} 280 281template <class Impl> 282void 283O3ThreadContext<Impl>::setVecRegFlat( 284 RegIndex reg_idx, const VecRegContainer& val) 285{ 286 cpu->setArchVecReg(reg_idx, val, thread->threadId()); 287 288 conditionalSquash(); 289} 290 291template <class Impl> 292void 293O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx, 294 const ElemIndex& elemIndex, const VecElem& val) 295{ 296 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId()); 297 conditionalSquash(); 298} 299 300template <class Impl> 301void 302O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx, 303 const VecPredRegContainer& val) 304{ 305 cpu->setArchVecPredReg(reg_idx, val, thread->threadId()); 306 307 conditionalSquash(); 308} 309 310template <class Impl> 311void 312O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val) 313{ 314 cpu->setArchCCReg(reg_idx, val, thread->threadId()); 315 316 conditionalSquash(); 317} 318 319template <class Impl> 320void 321O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 322{ 323 cpu->pcState(val, thread->threadId()); 324 325 conditionalSquash(); 326} 327 328template <class Impl> 329void 330O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 331{ 332 cpu->pcState(val, thread->threadId()); 333 334 conditionalSquash(); 335} 336 337template <class Impl> 338RegId 339O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const 340{ 341 return cpu->isa[thread->threadId()]->flattenRegId(regId); 342} 343 344template <class Impl> 345void 346O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) 347{ 348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 349 350 conditionalSquash(); 351} 352 353template <class Impl> 354void 355O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val) 356{ 357 cpu->setMiscReg(misc_reg, val, thread->threadId()); 358 359 conditionalSquash(); 360} 361 362#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 363