thread_context_impl.hh revision 12429:beefb9f5f551 
1/*
2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/kernel_stats.hh"
49#include "arch/registers.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/quiesce_event.hh"
53#include "debug/O3CPU.hh"
54
55template <class Impl>
56FSTranslatingPortProxy&
57O3ThreadContext<Impl>::getVirtProxy()
58{
59    return thread->getVirtProxy();
60}
61
62template <class Impl>
63void
64O3ThreadContext<Impl>::dumpFuncProfile()
65{
66    thread->dumpFuncProfile();
67}
68
69template <class Impl>
70void
71O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
72{
73    ::takeOverFrom(*this, *old_context);
74    TheISA::Decoder *newDecoder = getDecoderPtr();
75    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
76    newDecoder->takeOverFrom(oldDecoder);
77
78    thread->kernelStats = old_context->getKernelStats();
79    thread->funcExeInst = old_context->readFuncExeInst();
80
81    thread->noSquashFromTC = false;
82    thread->trapPending = false;
83}
84
85template <class Impl>
86void
87O3ThreadContext<Impl>::activate()
88{
89    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
90            threadId());
91
92    if (thread->status() == ThreadContext::Active)
93        return;
94
95    thread->lastActivate = curTick();
96    thread->setStatus(ThreadContext::Active);
97
98    // status() == Suspended
99    cpu->activateContext(thread->threadId());
100}
101
102template <class Impl>
103void
104O3ThreadContext<Impl>::suspend()
105{
106    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
107            threadId());
108
109    if (thread->status() == ThreadContext::Suspended)
110        return;
111
112    if (cpu->isDraining()) {
113        DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
114        return;
115    }
116
117    thread->lastActivate = curTick();
118    thread->lastSuspend = curTick();
119
120    thread->setStatus(ThreadContext::Suspended);
121    cpu->suspendContext(thread->threadId());
122}
123
124template <class Impl>
125void
126O3ThreadContext<Impl>::halt()
127{
128    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
129
130    if (thread->status() == ThreadContext::Halted)
131        return;
132
133    thread->setStatus(ThreadContext::Halted);
134    cpu->haltContext(thread->threadId());
135}
136
137template <class Impl>
138void
139O3ThreadContext<Impl>::regStats(const std::string &name)
140{
141    if (FullSystem) {
142        thread->kernelStats = new TheISA::Kernel::Statistics();
143        thread->kernelStats->regStats(name + ".kern");
144    }
145}
146
147template <class Impl>
148Tick
149O3ThreadContext<Impl>::readLastActivate()
150{
151    return thread->lastActivate;
152}
153
154template <class Impl>
155Tick
156O3ThreadContext<Impl>::readLastSuspend()
157{
158    return thread->lastSuspend;
159}
160
161template <class Impl>
162void
163O3ThreadContext<Impl>::profileClear()
164{
165    thread->profileClear();
166}
167
168template <class Impl>
169void
170O3ThreadContext<Impl>::profileSample()
171{
172    thread->profileSample();
173}
174
175template <class Impl>
176void
177O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
178{
179    // Prevent squashing
180    thread->noSquashFromTC = true;
181    TheISA::copyRegs(tc, this);
182    thread->noSquashFromTC = false;
183
184    if (!FullSystem)
185        this->thread->funcExeInst = tc->readFuncExeInst();
186}
187
188template <class Impl>
189void
190O3ThreadContext<Impl>::clearArchRegs()
191{
192    cpu->isa[thread->threadId()]->clear();
193}
194
195template <class Impl>
196uint64_t
197O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
198{
199    return cpu->readArchIntReg(reg_idx, thread->threadId());
200}
201
202template <class Impl>
203TheISA::FloatReg
204O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
205{
206    return cpu->readArchFloatReg(reg_idx, thread->threadId());
207}
208
209template <class Impl>
210TheISA::FloatRegBits
211O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
212{
213    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
214}
215
216template <class Impl>
217const TheISA::VecRegContainer&
218O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
219{
220    return cpu->readArchVecReg(reg_id, thread->threadId());
221}
222
223template <class Impl>
224TheISA::VecRegContainer&
225O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
226{
227    return cpu->getWritableArchVecReg(reg_id, thread->threadId());
228}
229
230template <class Impl>
231const TheISA::VecElem&
232O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
233                                           const ElemIndex& elemIndex) const
234{
235    return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
236}
237
238template <class Impl>
239TheISA::CCReg
240O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
241{
242    return cpu->readArchCCReg(reg_idx, thread->threadId());
243}
244
245template <class Impl>
246void
247O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
248{
249    cpu->setArchIntReg(reg_idx, val, thread->threadId());
250
251    conditionalSquash();
252}
253
254template <class Impl>
255void
256O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
257{
258    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
259
260    conditionalSquash();
261}
262
263template <class Impl>
264void
265O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
266{
267    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
268
269    conditionalSquash();
270}
271
272template <class Impl>
273void
274O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
275{
276    cpu->setArchVecReg(reg_idx, val, thread->threadId());
277
278    conditionalSquash();
279}
280
281template <class Impl>
282void
283O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
284        const ElemIndex& elemIndex, const VecElem& val)
285{
286    cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
287    conditionalSquash();
288}
289
290template <class Impl>
291void
292O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
293{
294    cpu->setArchCCReg(reg_idx, val, thread->threadId());
295
296    conditionalSquash();
297}
298
299template <class Impl>
300void
301O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
302{
303    cpu->pcState(val, thread->threadId());
304
305    conditionalSquash();
306}
307
308template <class Impl>
309void
310O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
311{
312    cpu->pcState(val, thread->threadId());
313
314    conditionalSquash();
315}
316
317template <class Impl>
318RegId
319O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
320{
321    return cpu->isa[thread->threadId()]->flattenRegId(regId);
322}
323
324template <class Impl>
325void
326O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
327{
328    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
329
330    conditionalSquash();
331}
332
333#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
334template <class Impl>
335void
336O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
337{
338    cpu->setMiscReg(misc_reg, val, thread->threadId());
339
340    conditionalSquash();
341}
342
343