thread_context_impl.hh revision 12181:2150eff234c1
1/* 2 * Copyright (c) 2010-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 47 48#include "arch/kernel_stats.hh" 49#include "arch/registers.hh" 50#include "config/the_isa.hh" 51#include "cpu/o3/thread_context.hh" 52#include "cpu/quiesce_event.hh" 53#include "debug/O3CPU.hh" 54 55template <class Impl> 56FSTranslatingPortProxy& 57O3ThreadContext<Impl>::getVirtProxy() 58{ 59 return thread->getVirtProxy(); 60} 61 62template <class Impl> 63void 64O3ThreadContext<Impl>::dumpFuncProfile() 65{ 66 thread->dumpFuncProfile(); 67} 68 69template <class Impl> 70void 71O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 72{ 73 ::takeOverFrom(*this, *old_context); 74 TheISA::Decoder *newDecoder = getDecoderPtr(); 75 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 76 newDecoder->takeOverFrom(oldDecoder); 77 78 thread->kernelStats = old_context->getKernelStats(); 79 thread->funcExeInst = old_context->readFuncExeInst(); 80 81 thread->noSquashFromTC = false; 82 thread->trapPending = false; 83} 84 85template <class Impl> 86void 87O3ThreadContext<Impl>::activate() 88{ 89 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 90 threadId()); 91 92 if (thread->status() == ThreadContext::Active) 93 return; 94 95 thread->lastActivate = curTick(); 96 thread->setStatus(ThreadContext::Active); 97 98 // status() == Suspended 99 cpu->activateContext(thread->threadId()); 100} 101 102template <class Impl> 103void 104O3ThreadContext<Impl>::suspend() 105{ 106 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 107 threadId()); 108 109 if (thread->status() == ThreadContext::Suspended) 110 return; 111 112 thread->lastActivate = curTick(); 113 thread->lastSuspend = curTick(); 114 115 thread->setStatus(ThreadContext::Suspended); 116 cpu->suspendContext(thread->threadId()); 117} 118 119template <class Impl> 120void 121O3ThreadContext<Impl>::halt() 122{ 123 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId()); 124 125 if (thread->status() == ThreadContext::Halted) 126 return; 127 128 thread->setStatus(ThreadContext::Halted); 129 cpu->haltContext(thread->threadId()); 130} 131 132template <class Impl> 133void 134O3ThreadContext<Impl>::regStats(const std::string &name) 135{ 136 if (FullSystem) { 137 thread->kernelStats = new TheISA::Kernel::Statistics(); 138 thread->kernelStats->regStats(name + ".kern"); 139 } 140} 141 142template <class Impl> 143Tick 144O3ThreadContext<Impl>::readLastActivate() 145{ 146 return thread->lastActivate; 147} 148 149template <class Impl> 150Tick 151O3ThreadContext<Impl>::readLastSuspend() 152{ 153 return thread->lastSuspend; 154} 155 156template <class Impl> 157void 158O3ThreadContext<Impl>::profileClear() 159{ 160 thread->profileClear(); 161} 162 163template <class Impl> 164void 165O3ThreadContext<Impl>::profileSample() 166{ 167 thread->profileSample(); 168} 169 170template <class Impl> 171void 172O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 173{ 174 // Prevent squashing 175 thread->noSquashFromTC = true; 176 TheISA::copyRegs(tc, this); 177 thread->noSquashFromTC = false; 178 179 if (!FullSystem) 180 this->thread->funcExeInst = tc->readFuncExeInst(); 181} 182 183template <class Impl> 184void 185O3ThreadContext<Impl>::clearArchRegs() 186{ 187 cpu->isa[thread->threadId()]->clear(); 188} 189 190template <class Impl> 191uint64_t 192O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 193{ 194 return cpu->readArchIntReg(reg_idx, thread->threadId()); 195} 196 197template <class Impl> 198TheISA::FloatReg 199O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 200{ 201 return cpu->readArchFloatReg(reg_idx, thread->threadId()); 202} 203 204template <class Impl> 205TheISA::FloatRegBits 206O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) 207{ 208 return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 209} 210 211template <class Impl> 212const TheISA::VecRegContainer& 213O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const 214{ 215 return cpu->readArchVecReg(reg_id, thread->threadId()); 216} 217 218template <class Impl> 219TheISA::VecRegContainer& 220O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id) 221{ 222 return cpu->getWritableArchVecReg(reg_id, thread->threadId()); 223} 224 225template <class Impl> 226const TheISA::VecElem& 227O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx, 228 const ElemIndex& elemIndex) const 229{ 230 return cpu->readArchVecElem(idx, elemIndex, thread->threadId()); 231} 232 233template <class Impl> 234TheISA::CCReg 235O3ThreadContext<Impl>::readCCRegFlat(int reg_idx) 236{ 237 return cpu->readArchCCReg(reg_idx, thread->threadId()); 238} 239 240template <class Impl> 241void 242O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) 243{ 244 cpu->setArchIntReg(reg_idx, val, thread->threadId()); 245 246 conditionalSquash(); 247} 248 249template <class Impl> 250void 251O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val) 252{ 253 cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 254 255 conditionalSquash(); 256} 257 258template <class Impl> 259void 260O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) 261{ 262 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 263 264 conditionalSquash(); 265} 266 267template <class Impl> 268void 269O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val) 270{ 271 cpu->setArchVecReg(reg_idx, val, thread->threadId()); 272 273 conditionalSquash(); 274} 275 276template <class Impl> 277void 278O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx, 279 const ElemIndex& elemIndex, const VecElem& val) 280{ 281 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId()); 282 conditionalSquash(); 283} 284 285template <class Impl> 286void 287O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val) 288{ 289 cpu->setArchCCReg(reg_idx, val, thread->threadId()); 290 291 conditionalSquash(); 292} 293 294template <class Impl> 295void 296O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 297{ 298 cpu->pcState(val, thread->threadId()); 299 300 conditionalSquash(); 301} 302 303template <class Impl> 304void 305O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 306{ 307 cpu->pcState(val, thread->threadId()); 308 309 conditionalSquash(); 310} 311 312template <class Impl> 313RegId 314O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const 315{ 316 return cpu->isa[thread->threadId()]->flattenRegId(regId); 317} 318 319template <class Impl> 320void 321O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 322{ 323 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 324 325 conditionalSquash(); 326} 327 328#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 329template <class Impl> 330void 331O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 332{ 333 cpu->setMiscReg(misc_reg, val, thread->threadId()); 334 335 conditionalSquash(); 336} 337 338