thread_context_impl.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
46#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
47
48#include "arch/kernel_stats.hh"
49#include "arch/registers.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/quiesce_event.hh"
53#include "debug/O3CPU.hh"
54
55template <class Impl>
56FSTranslatingPortProxy&
57O3ThreadContext<Impl>::getVirtProxy()
58{
59    return thread->getVirtProxy();
60}
61
62template <class Impl>
63void
64O3ThreadContext<Impl>::dumpFuncProfile()
65{
66    thread->dumpFuncProfile();
67}
68
69template <class Impl>
70void
71O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
72{
73    ::takeOverFrom(*this, *old_context);
74    TheISA::Decoder *newDecoder = getDecoderPtr();
75    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
76    newDecoder->takeOverFrom(oldDecoder);
77
78    thread->kernelStats = old_context->getKernelStats();
79    thread->funcExeInst = old_context->readFuncExeInst();
80
81    thread->noSquashFromTC = false;
82    thread->trapPending = false;
83}
84
85template <class Impl>
86void
87O3ThreadContext<Impl>::activate()
88{
89    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
90            threadId());
91
92    if (thread->status() == ThreadContext::Active)
93        return;
94
95    thread->lastActivate = curTick();
96    thread->setStatus(ThreadContext::Active);
97
98    // status() == Suspended
99    cpu->activateContext(thread->threadId());
100}
101
102template <class Impl>
103void
104O3ThreadContext<Impl>::suspend()
105{
106    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
107            threadId());
108
109    if (thread->status() == ThreadContext::Suspended)
110        return;
111
112    thread->lastActivate = curTick();
113    thread->lastSuspend = curTick();
114
115    thread->setStatus(ThreadContext::Suspended);
116    cpu->suspendContext(thread->threadId());
117}
118
119template <class Impl>
120void
121O3ThreadContext<Impl>::halt()
122{
123    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
124
125    if (thread->status() == ThreadContext::Halted)
126        return;
127
128    thread->setStatus(ThreadContext::Halted);
129    cpu->haltContext(thread->threadId());
130}
131
132template <class Impl>
133void
134O3ThreadContext<Impl>::regStats(const std::string &name)
135{
136    if (FullSystem) {
137        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
138        thread->kernelStats->regStats(name + ".kern");
139    }
140}
141
142template <class Impl>
143Tick
144O3ThreadContext<Impl>::readLastActivate()
145{
146    return thread->lastActivate;
147}
148
149template <class Impl>
150Tick
151O3ThreadContext<Impl>::readLastSuspend()
152{
153    return thread->lastSuspend;
154}
155
156template <class Impl>
157void
158O3ThreadContext<Impl>::profileClear()
159{
160    thread->profileClear();
161}
162
163template <class Impl>
164void
165O3ThreadContext<Impl>::profileSample()
166{
167    thread->profileSample();
168}
169
170template <class Impl>
171void
172O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
173{
174    // Prevent squashing
175    thread->noSquashFromTC = true;
176    TheISA::copyRegs(tc, this);
177    thread->noSquashFromTC = false;
178
179    if (!FullSystem)
180        this->thread->funcExeInst = tc->readFuncExeInst();
181}
182
183template <class Impl>
184void
185O3ThreadContext<Impl>::clearArchRegs()
186{
187    cpu->isa[thread->threadId()]->clear();
188}
189
190template <class Impl>
191uint64_t
192O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
193{
194    return cpu->readArchIntReg(reg_idx, thread->threadId());
195}
196
197template <class Impl>
198TheISA::FloatReg
199O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
200{
201    return cpu->readArchFloatReg(reg_idx, thread->threadId());
202}
203
204template <class Impl>
205TheISA::FloatRegBits
206O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
207{
208    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
209}
210
211template <class Impl>
212TheISA::CCReg
213O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
214{
215    return cpu->readArchCCReg(reg_idx, thread->threadId());
216}
217
218template <class Impl>
219void
220O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
221{
222    cpu->setArchIntReg(reg_idx, val, thread->threadId());
223
224    conditionalSquash();
225}
226
227template <class Impl>
228void
229O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
230{
231    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
232
233    conditionalSquash();
234}
235
236template <class Impl>
237void
238O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
239{
240    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
241
242    conditionalSquash();
243}
244
245template <class Impl>
246void
247O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
248{
249    cpu->setArchCCReg(reg_idx, val, thread->threadId());
250
251    conditionalSquash();
252}
253
254template <class Impl>
255void
256O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
257{
258    cpu->pcState(val, thread->threadId());
259
260    conditionalSquash();
261}
262
263template <class Impl>
264void
265O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
266{
267    cpu->pcState(val, thread->threadId());
268
269    conditionalSquash();
270}
271
272template <class Impl>
273RegId
274O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
275{
276    return cpu->isa[thread->threadId()]->flattenRegId(regId);
277}
278
279template <class Impl>
280void
281O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
282{
283    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
284
285    conditionalSquash();
286}
287
288#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
289template <class Impl>
290void
291O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
292{
293    cpu->setMiscReg(misc_reg, val, thread->threadId());
294
295    conditionalSquash();
296}
297
298