thread_context_impl.hh revision 9478
12817Sksewell@umich.edu/*
29426SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited
37763SAli.Saidi@ARM.com * All rights reserved
47763SAli.Saidi@ARM.com *
57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97763SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137763SAli.Saidi@ARM.com *
142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan
152817Sksewell@umich.edu * All rights reserved.
162817Sksewell@umich.edu *
172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are
192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
262817Sksewell@umich.edu * this software without specific prior written permission.
272817Sksewell@umich.edu *
282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392817Sksewell@umich.edu *
402817Sksewell@umich.edu * Authors: Kevin Lim
412817Sksewell@umich.edu *          Korey Sewell
422817Sksewell@umich.edu */
432817Sksewell@umich.edu
448793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh"
456329Sgblack@eecs.umich.edu#include "arch/registers.hh"
466658Snate@binkert.org#include "config/the_isa.hh"
472817Sksewell@umich.edu#include "cpu/o3/thread_context.hh"
482834Sksewell@umich.edu#include "cpu/quiesce_event.hh"
498232Snate@binkert.org#include "debug/O3CPU.hh"
502817Sksewell@umich.edu
512817Sksewell@umich.edutemplate <class Impl>
528852Sandreas.hansson@arm.comFSTranslatingPortProxy&
538706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy()
542817Sksewell@umich.edu{
558706Sandreas.hansson@arm.com    return thread->getVirtProxy();
562817Sksewell@umich.edu}
572817Sksewell@umich.edu
582817Sksewell@umich.edutemplate <class Impl>
592817Sksewell@umich.eduvoid
602817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile()
612817Sksewell@umich.edu{
623126Sktlim@umich.edu    thread->dumpFuncProfile();
632817Sksewell@umich.edu}
642817Sksewell@umich.edu
652817Sksewell@umich.edutemplate <class Impl>
662817Sksewell@umich.eduvoid
672817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
682817Sksewell@umich.edu{
699441SAndreas.Sandberg@ARM.com    ::takeOverFrom(*this, *old_context);
709478Snilay@cs.wisc.edu    TheISA::Decoder *newDecoder = getDecoderPtr();
719478Snilay@cs.wisc.edu    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
729478Snilay@cs.wisc.edu    newDecoder->takeOverFrom(oldDecoder);
732817Sksewell@umich.edu
749441SAndreas.Sandberg@ARM.com    thread->kernelStats = old_context->getKernelStats();
759441SAndreas.Sandberg@ARM.com    thread->funcExeInst = old_context->readFuncExeInst();
762817Sksewell@umich.edu
779382SAli.Saidi@ARM.com    thread->noSquashFromTC = false;
782817Sksewell@umich.edu    thread->trapPending = false;
792817Sksewell@umich.edu}
802817Sksewell@umich.edu
812817Sksewell@umich.edutemplate <class Impl>
822817Sksewell@umich.eduvoid
839180Sandreas.hansson@arm.comO3ThreadContext<Impl>::activate(Cycles delay)
842817Sksewell@umich.edu{
852875Sksewell@umich.edu    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
865715Shsul@eecs.umich.edu            threadId());
872817Sksewell@umich.edu
882817Sksewell@umich.edu    if (thread->status() == ThreadContext::Active)
892817Sksewell@umich.edu        return;
902817Sksewell@umich.edu
917823Ssteve.reinhardt@amd.com    thread->lastActivate = curTick();
922817Sksewell@umich.edu    thread->setStatus(ThreadContext::Active);
932817Sksewell@umich.edu
942817Sksewell@umich.edu    // status() == Suspended
955715Shsul@eecs.umich.edu    cpu->activateContext(thread->threadId(), delay);
962817Sksewell@umich.edu}
972817Sksewell@umich.edu
982817Sksewell@umich.edutemplate <class Impl>
992817Sksewell@umich.eduvoid
1009180Sandreas.hansson@arm.comO3ThreadContext<Impl>::suspend(Cycles delay)
1012817Sksewell@umich.edu{
1022875Sksewell@umich.edu    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
1035715Shsul@eecs.umich.edu            threadId());
1042817Sksewell@umich.edu
1052817Sksewell@umich.edu    if (thread->status() == ThreadContext::Suspended)
1062817Sksewell@umich.edu        return;
1072817Sksewell@umich.edu
1087823Ssteve.reinhardt@amd.com    thread->lastActivate = curTick();
1097823Ssteve.reinhardt@amd.com    thread->lastSuspend = curTick();
1108793Sgblack@eecs.umich.edu
1112817Sksewell@umich.edu    thread->setStatus(ThreadContext::Suspended);
1125715Shsul@eecs.umich.edu    cpu->suspendContext(thread->threadId());
1132817Sksewell@umich.edu}
1142817Sksewell@umich.edu
1152817Sksewell@umich.edutemplate <class Impl>
1162817Sksewell@umich.eduvoid
1179180Sandreas.hansson@arm.comO3ThreadContext<Impl>::halt(Cycles delay)
1182817Sksewell@umich.edu{
1192875Sksewell@umich.edu    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
1205715Shsul@eecs.umich.edu            threadId());
1212817Sksewell@umich.edu
1222817Sksewell@umich.edu    if (thread->status() == ThreadContext::Halted)
1232817Sksewell@umich.edu        return;
1242817Sksewell@umich.edu
1252817Sksewell@umich.edu    thread->setStatus(ThreadContext::Halted);
1265715Shsul@eecs.umich.edu    cpu->haltContext(thread->threadId());
1272817Sksewell@umich.edu}
1282817Sksewell@umich.edu
1292817Sksewell@umich.edutemplate <class Impl>
1302817Sksewell@umich.eduvoid
1312817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name)
1322817Sksewell@umich.edu{
1338793Sgblack@eecs.umich.edu    if (FullSystem) {
1348793Sgblack@eecs.umich.edu        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
1358793Sgblack@eecs.umich.edu        thread->kernelStats->regStats(name + ".kern");
1368793Sgblack@eecs.umich.edu    }
1372817Sksewell@umich.edu}
1382817Sksewell@umich.edu
1392817Sksewell@umich.edutemplate <class Impl>
1402817Sksewell@umich.eduTick
1412817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate()
1422817Sksewell@umich.edu{
1432817Sksewell@umich.edu    return thread->lastActivate;
1442817Sksewell@umich.edu}
1452817Sksewell@umich.edu
1462817Sksewell@umich.edutemplate <class Impl>
1472817Sksewell@umich.eduTick
1482817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend()
1492817Sksewell@umich.edu{
1502817Sksewell@umich.edu    return thread->lastSuspend;
1512817Sksewell@umich.edu}
1522817Sksewell@umich.edu
1532817Sksewell@umich.edutemplate <class Impl>
1542817Sksewell@umich.eduvoid
1552817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear()
1563126Sktlim@umich.edu{
1573126Sktlim@umich.edu    thread->profileClear();
1583126Sktlim@umich.edu}
1592817Sksewell@umich.edu
1602817Sksewell@umich.edutemplate <class Impl>
1612817Sksewell@umich.eduvoid
1622817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample()
1633126Sktlim@umich.edu{
1643126Sktlim@umich.edu    thread->profileSample();
1653126Sktlim@umich.edu}
1662817Sksewell@umich.edu
1672817Sksewell@umich.edutemplate <class Impl>
1682817Sksewell@umich.eduvoid
1692817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
1702817Sksewell@umich.edu{
1718208SAli.Saidi@ARM.com    // Prevent squashing
1729382SAli.Saidi@ARM.com    thread->noSquashFromTC = true;
1738208SAli.Saidi@ARM.com    TheISA::copyRegs(tc, this);
1749382SAli.Saidi@ARM.com    thread->noSquashFromTC = false;
1752817Sksewell@umich.edu
1768793Sgblack@eecs.umich.edu    if (!FullSystem)
1778793Sgblack@eecs.umich.edu        this->thread->funcExeInst = tc->readFuncExeInst();
1782817Sksewell@umich.edu}
1792817Sksewell@umich.edu
1802817Sksewell@umich.edutemplate <class Impl>
1812817Sksewell@umich.eduvoid
1822817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs()
1837763SAli.Saidi@ARM.com{
1849384SAndreas.Sandberg@arm.com    cpu->isa[thread->threadId()]->clear();
1857763SAli.Saidi@ARM.com}
1862817Sksewell@umich.edu
1872817Sksewell@umich.edutemplate <class Impl>
1882817Sksewell@umich.eduuint64_t
1899426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
1902817Sksewell@umich.edu{
1915715Shsul@eecs.umich.edu    return cpu->readArchIntReg(reg_idx, thread->threadId());
1922817Sksewell@umich.edu}
1932817Sksewell@umich.edu
1942817Sksewell@umich.edutemplate <class Impl>
1952986Sgblack@eecs.umich.eduTheISA::FloatReg
1969426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
1972817Sksewell@umich.edu{
1986314Sgblack@eecs.umich.edu    return cpu->readArchFloatReg(reg_idx, thread->threadId());
1992817Sksewell@umich.edu}
2002817Sksewell@umich.edu
2012817Sksewell@umich.edutemplate <class Impl>
2022986Sgblack@eecs.umich.eduTheISA::FloatRegBits
2039426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
2042817Sksewell@umich.edu{
2055715Shsul@eecs.umich.edu    return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
2062817Sksewell@umich.edu}
2072817Sksewell@umich.edu
2082817Sksewell@umich.edutemplate <class Impl>
2092817Sksewell@umich.eduvoid
2109426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
2112817Sksewell@umich.edu{
2125715Shsul@eecs.umich.edu    cpu->setArchIntReg(reg_idx, val, thread->threadId());
2132817Sksewell@umich.edu
2149382SAli.Saidi@ARM.com    conditionalSquash();
2152817Sksewell@umich.edu}
2162817Sksewell@umich.edu
2172817Sksewell@umich.edutemplate <class Impl>
2182817Sksewell@umich.eduvoid
2199426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
2202817Sksewell@umich.edu{
2216314Sgblack@eecs.umich.edu    cpu->setArchFloatReg(reg_idx, val, thread->threadId());
2222817Sksewell@umich.edu
2239382SAli.Saidi@ARM.com    conditionalSquash();
2242817Sksewell@umich.edu}
2252817Sksewell@umich.edu
2262817Sksewell@umich.edutemplate <class Impl>
2272817Sksewell@umich.eduvoid
2289426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
2292817Sksewell@umich.edu{
2305715Shsul@eecs.umich.edu    cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
2312817Sksewell@umich.edu
2329382SAli.Saidi@ARM.com    conditionalSquash();
2332817Sksewell@umich.edu}
2342817Sksewell@umich.edu
2352817Sksewell@umich.edutemplate <class Impl>
2362817Sksewell@umich.eduvoid
2377720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
2382817Sksewell@umich.edu{
2397720Sgblack@eecs.umich.edu    cpu->pcState(val, thread->threadId());
2405258Sksewell@umich.edu
2419382SAli.Saidi@ARM.com    conditionalSquash();
2425258Sksewell@umich.edu}
2435258Sksewell@umich.edu
2448733Sgeoffrey.blake@arm.comtemplate <class Impl>
2458733Sgeoffrey.blake@arm.comvoid
2468733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
2478733Sgeoffrey.blake@arm.com{
2488733Sgeoffrey.blake@arm.com    cpu->pcState(val, thread->threadId());
2498733Sgeoffrey.blake@arm.com
2509382SAli.Saidi@ARM.com    conditionalSquash();
2518733Sgeoffrey.blake@arm.com}
2528733Sgeoffrey.blake@arm.com
2535258Sksewell@umich.edutemplate <class Impl>
2546313Sgblack@eecs.umich.eduint
2556313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg)
2566313Sgblack@eecs.umich.edu{
2579384SAndreas.Sandberg@arm.com    return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
2586313Sgblack@eecs.umich.edu}
2596313Sgblack@eecs.umich.edu
2606313Sgblack@eecs.umich.edutemplate <class Impl>
2616313Sgblack@eecs.umich.eduint
2626313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg)
2636313Sgblack@eecs.umich.edu{
2649384SAndreas.Sandberg@arm.com    return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
2656313Sgblack@eecs.umich.edu}
2666313Sgblack@eecs.umich.edu
2676313Sgblack@eecs.umich.edutemplate <class Impl>
2685258Sksewell@umich.eduvoid
2694172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
2702817Sksewell@umich.edu{
2715715Shsul@eecs.umich.edu    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
2722817Sksewell@umich.edu
2739382SAli.Saidi@ARM.com    conditionalSquash();
2742817Sksewell@umich.edu}
2752817Sksewell@umich.edu
2762817Sksewell@umich.edutemplate <class Impl>
2773468Sgblack@eecs.umich.eduvoid
2788518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
2792817Sksewell@umich.edu{
2805715Shsul@eecs.umich.edu    cpu->setMiscReg(misc_reg, val, thread->threadId());
2812817Sksewell@umich.edu
2829382SAli.Saidi@ARM.com    conditionalSquash();
2832817Sksewell@umich.edu}
2842817Sksewell@umich.edu
285