thread_context_impl.hh revision 9478
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2010-2012 ARM Limited 35222Sksewell@umich.edu * All rights reserved 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65222Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75222Sksewell@umich.edu * property including but not limited to intellectual property relating 85222Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95222Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105222Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115222Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125222Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135222Sksewell@umich.edu * 145222Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 155222Sksewell@umich.edu * All rights reserved. 165222Sksewell@umich.edu * 175222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 185222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 195222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 205222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 215222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 225222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 235222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 245222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 255222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 265222Sksewell@umich.edu * this software without specific prior written permission. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395222Sksewell@umich.edu * 405222Sksewell@umich.edu * Authors: Kevin Lim 415222Sksewell@umich.edu * Korey Sewell 425222Sksewell@umich.edu */ 435222Sksewell@umich.edu 445222Sksewell@umich.edu#include "arch/kernel_stats.hh" 455222Sksewell@umich.edu#include "arch/registers.hh" 465222Sksewell@umich.edu#include "config/the_isa.hh" 475222Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 485222Sksewell@umich.edu#include "cpu/quiesce_event.hh" 495222Sksewell@umich.edu#include "debug/O3CPU.hh" 505222Sksewell@umich.edu 515222Sksewell@umich.edutemplate <class Impl> 525222Sksewell@umich.eduFSTranslatingPortProxy& 53O3ThreadContext<Impl>::getVirtProxy() 54{ 55 return thread->getVirtProxy(); 56} 57 58template <class Impl> 59void 60O3ThreadContext<Impl>::dumpFuncProfile() 61{ 62 thread->dumpFuncProfile(); 63} 64 65template <class Impl> 66void 67O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 68{ 69 ::takeOverFrom(*this, *old_context); 70 TheISA::Decoder *newDecoder = getDecoderPtr(); 71 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 72 newDecoder->takeOverFrom(oldDecoder); 73 74 thread->kernelStats = old_context->getKernelStats(); 75 thread->funcExeInst = old_context->readFuncExeInst(); 76 77 thread->noSquashFromTC = false; 78 thread->trapPending = false; 79} 80 81template <class Impl> 82void 83O3ThreadContext<Impl>::activate(Cycles delay) 84{ 85 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 86 threadId()); 87 88 if (thread->status() == ThreadContext::Active) 89 return; 90 91 thread->lastActivate = curTick(); 92 thread->setStatus(ThreadContext::Active); 93 94 // status() == Suspended 95 cpu->activateContext(thread->threadId(), delay); 96} 97 98template <class Impl> 99void 100O3ThreadContext<Impl>::suspend(Cycles delay) 101{ 102 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 103 threadId()); 104 105 if (thread->status() == ThreadContext::Suspended) 106 return; 107 108 thread->lastActivate = curTick(); 109 thread->lastSuspend = curTick(); 110 111 thread->setStatus(ThreadContext::Suspended); 112 cpu->suspendContext(thread->threadId()); 113} 114 115template <class Impl> 116void 117O3ThreadContext<Impl>::halt(Cycles delay) 118{ 119 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 120 threadId()); 121 122 if (thread->status() == ThreadContext::Halted) 123 return; 124 125 thread->setStatus(ThreadContext::Halted); 126 cpu->haltContext(thread->threadId()); 127} 128 129template <class Impl> 130void 131O3ThreadContext<Impl>::regStats(const std::string &name) 132{ 133 if (FullSystem) { 134 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 135 thread->kernelStats->regStats(name + ".kern"); 136 } 137} 138 139template <class Impl> 140Tick 141O3ThreadContext<Impl>::readLastActivate() 142{ 143 return thread->lastActivate; 144} 145 146template <class Impl> 147Tick 148O3ThreadContext<Impl>::readLastSuspend() 149{ 150 return thread->lastSuspend; 151} 152 153template <class Impl> 154void 155O3ThreadContext<Impl>::profileClear() 156{ 157 thread->profileClear(); 158} 159 160template <class Impl> 161void 162O3ThreadContext<Impl>::profileSample() 163{ 164 thread->profileSample(); 165} 166 167template <class Impl> 168void 169O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 170{ 171 // Prevent squashing 172 thread->noSquashFromTC = true; 173 TheISA::copyRegs(tc, this); 174 thread->noSquashFromTC = false; 175 176 if (!FullSystem) 177 this->thread->funcExeInst = tc->readFuncExeInst(); 178} 179 180template <class Impl> 181void 182O3ThreadContext<Impl>::clearArchRegs() 183{ 184 cpu->isa[thread->threadId()]->clear(); 185} 186 187template <class Impl> 188uint64_t 189O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 190{ 191 return cpu->readArchIntReg(reg_idx, thread->threadId()); 192} 193 194template <class Impl> 195TheISA::FloatReg 196O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 197{ 198 return cpu->readArchFloatReg(reg_idx, thread->threadId()); 199} 200 201template <class Impl> 202TheISA::FloatRegBits 203O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) 204{ 205 return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 206} 207 208template <class Impl> 209void 210O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) 211{ 212 cpu->setArchIntReg(reg_idx, val, thread->threadId()); 213 214 conditionalSquash(); 215} 216 217template <class Impl> 218void 219O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val) 220{ 221 cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 222 223 conditionalSquash(); 224} 225 226template <class Impl> 227void 228O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) 229{ 230 cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 231 232 conditionalSquash(); 233} 234 235template <class Impl> 236void 237O3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 238{ 239 cpu->pcState(val, thread->threadId()); 240 241 conditionalSquash(); 242} 243 244template <class Impl> 245void 246O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 247{ 248 cpu->pcState(val, thread->threadId()); 249 250 conditionalSquash(); 251} 252 253template <class Impl> 254int 255O3ThreadContext<Impl>::flattenIntIndex(int reg) 256{ 257 return cpu->isa[thread->threadId()]->flattenIntIndex(reg); 258} 259 260template <class Impl> 261int 262O3ThreadContext<Impl>::flattenFloatIndex(int reg) 263{ 264 return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); 265} 266 267template <class Impl> 268void 269O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 270{ 271 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 272 273 conditionalSquash(); 274} 275 276template <class Impl> 277void 278O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 279{ 280 cpu->setMiscReg(misc_reg, val, thread->threadId()); 281 282 conditionalSquash(); 283} 284 285