thread_context_impl.hh revision 8852
12817Sksewell@umich.edu/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37763SAli.Saidi@ARM.com * All rights reserved 47763SAli.Saidi@ARM.com * 57763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137763SAli.Saidi@ARM.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu * Korey Sewell 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 448793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 456329Sgblack@eecs.umich.edu#include "arch/registers.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 478733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 482817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 492834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 508232Snate@binkert.org#include "debug/O3CPU.hh" 512817Sksewell@umich.edu 522817Sksewell@umich.edutemplate <class Impl> 538852Sandreas.hansson@arm.comFSTranslatingPortProxy& 548706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 552817Sksewell@umich.edu{ 568706Sandreas.hansson@arm.com return thread->getVirtProxy(); 572817Sksewell@umich.edu} 582817Sksewell@umich.edu 592817Sksewell@umich.edutemplate <class Impl> 602817Sksewell@umich.eduvoid 612817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 622817Sksewell@umich.edu{ 633126Sktlim@umich.edu thread->dumpFuncProfile(); 642817Sksewell@umich.edu} 652817Sksewell@umich.edu 662817Sksewell@umich.edutemplate <class Impl> 672817Sksewell@umich.eduvoid 682817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 692817Sksewell@umich.edu{ 702817Sksewell@umich.edu // some things should already be set up 712817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 722817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 732817Sksewell@umich.edu 742817Sksewell@umich.edu // copy over functional state 752817Sksewell@umich.edu setStatus(old_context->status()); 762817Sksewell@umich.edu copyArchRegs(old_context); 775714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 785715Shsul@eecs.umich.edu setThreadId(old_context->threadId()); 792817Sksewell@umich.edu 808793Sgblack@eecs.umich.edu if (FullSystem) { 818793Sgblack@eecs.umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 828793Sgblack@eecs.umich.edu if (other_quiesce) { 838793Sgblack@eecs.umich.edu // Point the quiesce event's TC at this TC so that it wakes up 848793Sgblack@eecs.umich.edu // the proper CPU. 858793Sgblack@eecs.umich.edu other_quiesce->tc = this; 868793Sgblack@eecs.umich.edu } 878793Sgblack@eecs.umich.edu if (thread->quiesceEvent) { 888793Sgblack@eecs.umich.edu thread->quiesceEvent->tc = this; 898793Sgblack@eecs.umich.edu } 908793Sgblack@eecs.umich.edu 918793Sgblack@eecs.umich.edu // Transfer kernel stats from one CPU to the other. 928793Sgblack@eecs.umich.edu thread->kernelStats = old_context->getKernelStats(); 938793Sgblack@eecs.umich.edu cpu->lockFlag = false; 948793Sgblack@eecs.umich.edu } else { 958793Sgblack@eecs.umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 962817Sksewell@umich.edu } 972817Sksewell@umich.edu 986029Ssteve.reinhardt@amd.com old_context->setStatus(ThreadContext::Halted); 992817Sksewell@umich.edu 1002817Sksewell@umich.edu thread->inSyscall = false; 1012817Sksewell@umich.edu thread->trapPending = false; 1022817Sksewell@umich.edu} 1032817Sksewell@umich.edu 1042817Sksewell@umich.edutemplate <class Impl> 1052817Sksewell@umich.eduvoid 1062817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 1072817Sksewell@umich.edu{ 1082875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1095715Shsul@eecs.umich.edu threadId()); 1102817Sksewell@umich.edu 1112817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1122817Sksewell@umich.edu return; 1132817Sksewell@umich.edu 1147823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1152817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1162817Sksewell@umich.edu 1172817Sksewell@umich.edu // status() == Suspended 1185715Shsul@eecs.umich.edu cpu->activateContext(thread->threadId(), delay); 1192817Sksewell@umich.edu} 1202817Sksewell@umich.edu 1212817Sksewell@umich.edutemplate <class Impl> 1222817Sksewell@umich.eduvoid 1235250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1242817Sksewell@umich.edu{ 1252875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1265715Shsul@eecs.umich.edu threadId()); 1272817Sksewell@umich.edu 1282817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1292817Sksewell@umich.edu return; 1302817Sksewell@umich.edu 1317823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1327823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1338793Sgblack@eecs.umich.edu 1342817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1355715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1362817Sksewell@umich.edu} 1372817Sksewell@umich.edu 1382817Sksewell@umich.edutemplate <class Impl> 1392817Sksewell@umich.eduvoid 1405250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1412817Sksewell@umich.edu{ 1422875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1435715Shsul@eecs.umich.edu threadId()); 1442817Sksewell@umich.edu 1452817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1462817Sksewell@umich.edu return; 1472817Sksewell@umich.edu 1482817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1495715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1502817Sksewell@umich.edu} 1512817Sksewell@umich.edu 1522817Sksewell@umich.edutemplate <class Impl> 1532817Sksewell@umich.eduvoid 1542817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1552817Sksewell@umich.edu{ 1568793Sgblack@eecs.umich.edu if (FullSystem) { 1578793Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1588793Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1598793Sgblack@eecs.umich.edu } 1602817Sksewell@umich.edu} 1612817Sksewell@umich.edu 1622817Sksewell@umich.edutemplate <class Impl> 1632817Sksewell@umich.eduvoid 1642817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1652817Sksewell@umich.edu{ 1668793Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1672817Sksewell@umich.edu thread->kernelStats->serialize(os); 1682817Sksewell@umich.edu} 1692817Sksewell@umich.edu 1702817Sksewell@umich.edutemplate <class Impl> 1712817Sksewell@umich.eduvoid 1722817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1732817Sksewell@umich.edu{ 1748793Sgblack@eecs.umich.edu if (FullSystem && thread->kernelStats) 1752817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 1762817Sksewell@umich.edu} 1772817Sksewell@umich.edu 1782817Sksewell@umich.edutemplate <class Impl> 1792817Sksewell@umich.eduTick 1802817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1812817Sksewell@umich.edu{ 1822817Sksewell@umich.edu return thread->lastActivate; 1832817Sksewell@umich.edu} 1842817Sksewell@umich.edu 1852817Sksewell@umich.edutemplate <class Impl> 1862817Sksewell@umich.eduTick 1872817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1882817Sksewell@umich.edu{ 1892817Sksewell@umich.edu return thread->lastSuspend; 1902817Sksewell@umich.edu} 1912817Sksewell@umich.edu 1922817Sksewell@umich.edutemplate <class Impl> 1932817Sksewell@umich.eduvoid 1942817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 1953126Sktlim@umich.edu{ 1963126Sktlim@umich.edu thread->profileClear(); 1973126Sktlim@umich.edu} 1982817Sksewell@umich.edu 1992817Sksewell@umich.edutemplate <class Impl> 2002817Sksewell@umich.eduvoid 2012817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2023126Sktlim@umich.edu{ 2033126Sktlim@umich.edu thread->profileSample(); 2043126Sktlim@umich.edu} 2052817Sksewell@umich.edu 2062817Sksewell@umich.edutemplate <class Impl> 2072817Sksewell@umich.eduvoid 2082817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2092817Sksewell@umich.edu{ 2108208SAli.Saidi@ARM.com // Prevent squashing 2118208SAli.Saidi@ARM.com thread->inSyscall = true; 2128208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 2138208SAli.Saidi@ARM.com thread->inSyscall = false; 2142817Sksewell@umich.edu 2158793Sgblack@eecs.umich.edu if (!FullSystem) 2168793Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2172817Sksewell@umich.edu} 2182817Sksewell@umich.edu 2192817Sksewell@umich.edutemplate <class Impl> 2202817Sksewell@umich.eduvoid 2212817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2227763SAli.Saidi@ARM.com{ 2237763SAli.Saidi@ARM.com cpu->isa[thread->threadId()].clear(); 2247763SAli.Saidi@ARM.com} 2252817Sksewell@umich.edu 2262817Sksewell@umich.edutemplate <class Impl> 2272817Sksewell@umich.eduuint64_t 2282817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2292817Sksewell@umich.edu{ 2306313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2315715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 2322817Sksewell@umich.edu} 2332817Sksewell@umich.edu 2342817Sksewell@umich.edutemplate <class Impl> 2352986Sgblack@eecs.umich.eduTheISA::FloatReg 2362817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 2372817Sksewell@umich.edu{ 2386313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2396314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2402817Sksewell@umich.edu} 2412817Sksewell@umich.edu 2422817Sksewell@umich.edutemplate <class Impl> 2432986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2442817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 2452817Sksewell@umich.edu{ 2466313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2475715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2482817Sksewell@umich.edu} 2492817Sksewell@umich.edu 2502817Sksewell@umich.edutemplate <class Impl> 2512817Sksewell@umich.eduvoid 2522817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 2532817Sksewell@umich.edu{ 2546313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); 2555715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2562817Sksewell@umich.edu 2572817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2582817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2595715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2602817Sksewell@umich.edu } 2612817Sksewell@umich.edu} 2622817Sksewell@umich.edu 2632817Sksewell@umich.edutemplate <class Impl> 2642817Sksewell@umich.eduvoid 2652817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 2662817Sksewell@umich.edu{ 2676313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2686314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2692817Sksewell@umich.edu 2702817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2715715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2722817Sksewell@umich.edu } 2732817Sksewell@umich.edu} 2742817Sksewell@umich.edu 2752817Sksewell@umich.edutemplate <class Impl> 2762817Sksewell@umich.eduvoid 2772817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 2782817Sksewell@umich.edu{ 2796313Sgblack@eecs.umich.edu reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); 2805715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 2812817Sksewell@umich.edu 2822817Sksewell@umich.edu // Squash if we're not already in a state update mode. 2832817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2845715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2852817Sksewell@umich.edu } 2862817Sksewell@umich.edu} 2872817Sksewell@umich.edu 2882817Sksewell@umich.edutemplate <class Impl> 2892817Sksewell@umich.eduvoid 2907720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 2912817Sksewell@umich.edu{ 2927720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 2935258Sksewell@umich.edu 2945258Sksewell@umich.edu // Squash if we're not already in a state update mode. 2955258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 2965715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 2975258Sksewell@umich.edu } 2985258Sksewell@umich.edu} 2995258Sksewell@umich.edu 3008733Sgeoffrey.blake@arm.com#if USE_CHECKER 3018733Sgeoffrey.blake@arm.comtemplate <class Impl> 3028733Sgeoffrey.blake@arm.comvoid 3038733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 3048733Sgeoffrey.blake@arm.com{ 3058733Sgeoffrey.blake@arm.com cpu->pcState(val, thread->threadId()); 3068733Sgeoffrey.blake@arm.com 3078733Sgeoffrey.blake@arm.com // Squash if we're not already in a state update mode. 3088733Sgeoffrey.blake@arm.com if (!thread->trapPending && !thread->inSyscall) { 3098733Sgeoffrey.blake@arm.com cpu->squashFromTC(thread->threadId()); 3108733Sgeoffrey.blake@arm.com } 3118733Sgeoffrey.blake@arm.com} 3128733Sgeoffrey.blake@arm.com#endif 3138733Sgeoffrey.blake@arm.com 3145258Sksewell@umich.edutemplate <class Impl> 3156313Sgblack@eecs.umich.eduint 3166313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenIntIndex(int reg) 3176313Sgblack@eecs.umich.edu{ 3186313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenIntIndex(reg); 3196313Sgblack@eecs.umich.edu} 3206313Sgblack@eecs.umich.edu 3216313Sgblack@eecs.umich.edutemplate <class Impl> 3226313Sgblack@eecs.umich.eduint 3236313Sgblack@eecs.umich.eduO3ThreadContext<Impl>::flattenFloatIndex(int reg) 3246313Sgblack@eecs.umich.edu{ 3256313Sgblack@eecs.umich.edu return cpu->isa[thread->threadId()].flattenFloatIndex(reg); 3266313Sgblack@eecs.umich.edu} 3276313Sgblack@eecs.umich.edu 3286313Sgblack@eecs.umich.edutemplate <class Impl> 3295258Sksewell@umich.eduvoid 3304172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3312817Sksewell@umich.edu{ 3325715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 3332817Sksewell@umich.edu 3342817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3352817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3365715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3372817Sksewell@umich.edu } 3382817Sksewell@umich.edu} 3392817Sksewell@umich.edu 3402817Sksewell@umich.edutemplate <class Impl> 3413468Sgblack@eecs.umich.eduvoid 3428518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 3432817Sksewell@umich.edu{ 3445715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 3452817Sksewell@umich.edu 3462817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3472817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3485715Shsul@eecs.umich.edu cpu->squashFromTC(thread->threadId()); 3492817Sksewell@umich.edu } 3502817Sksewell@umich.edu} 3512817Sksewell@umich.edu 352