thread_context_impl.hh revision 5714
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 323776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 332817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 342834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 352817Sksewell@umich.edu 362817Sksewell@umich.edu#if FULL_SYSTEM 372817Sksewell@umich.edutemplate <class Impl> 382817Sksewell@umich.eduVirtualPort * 395499Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::getVirtPort() 402817Sksewell@umich.edu{ 415499Ssaidi@eecs.umich.edu return thread->getVirtPort(); 422817Sksewell@umich.edu} 432817Sksewell@umich.edu 442817Sksewell@umich.edutemplate <class Impl> 452817Sksewell@umich.eduvoid 462817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 472817Sksewell@umich.edu{ 483126Sktlim@umich.edu thread->dumpFuncProfile(); 492817Sksewell@umich.edu} 502817Sksewell@umich.edu#endif 512817Sksewell@umich.edu 522817Sksewell@umich.edutemplate <class Impl> 532817Sksewell@umich.eduvoid 542817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 552817Sksewell@umich.edu{ 562817Sksewell@umich.edu // some things should already be set up 572817Sksewell@umich.edu#if FULL_SYSTEM 582817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 592817Sksewell@umich.edu#else 602817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 612817Sksewell@umich.edu#endif 622817Sksewell@umich.edu 632817Sksewell@umich.edu // copy over functional state 642817Sksewell@umich.edu setStatus(old_context->status()); 652817Sksewell@umich.edu copyArchRegs(old_context); 665714Shsul@eecs.umich.edu setContextId(old_context->contextId()); 672817Sksewell@umich.edu 682817Sksewell@umich.edu#if !FULL_SYSTEM 692817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 702817Sksewell@umich.edu#else 712817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 722817Sksewell@umich.edu if (other_quiesce) { 732817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 742817Sksewell@umich.edu // the proper CPU. 752817Sksewell@umich.edu other_quiesce->tc = this; 762817Sksewell@umich.edu } 772817Sksewell@umich.edu if (thread->quiesceEvent) { 782817Sksewell@umich.edu thread->quiesceEvent->tc = this; 792817Sksewell@umich.edu } 802817Sksewell@umich.edu 812817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 822817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 832817Sksewell@umich.edu// storeCondFailures = 0; 842817Sksewell@umich.edu cpu->lockFlag = false; 852817Sksewell@umich.edu#endif 862817Sksewell@umich.edu 872817Sksewell@umich.edu old_context->setStatus(ThreadContext::Unallocated); 882817Sksewell@umich.edu 892817Sksewell@umich.edu thread->inSyscall = false; 902817Sksewell@umich.edu thread->trapPending = false; 912817Sksewell@umich.edu} 922817Sksewell@umich.edu 932817Sksewell@umich.edutemplate <class Impl> 942817Sksewell@umich.eduvoid 952817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 962817Sksewell@umich.edu{ 972875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 982875Sksewell@umich.edu getThreadNum()); 992817Sksewell@umich.edu 1002817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1012817Sksewell@umich.edu return; 1022817Sksewell@umich.edu 1032817Sksewell@umich.edu#if FULL_SYSTEM 1042817Sksewell@umich.edu thread->lastActivate = curTick; 1052817Sksewell@umich.edu#endif 1062817Sksewell@umich.edu 1072817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) { 1082817Sksewell@umich.edu cpu->activateWhenReady(thread->readTid()); 1092817Sksewell@umich.edu return; 1102817Sksewell@umich.edu } 1112817Sksewell@umich.edu 1122817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1132817Sksewell@umich.edu 1142817Sksewell@umich.edu // status() == Suspended 1152817Sksewell@umich.edu cpu->activateContext(thread->readTid(), delay); 1162817Sksewell@umich.edu} 1172817Sksewell@umich.edu 1182817Sksewell@umich.edutemplate <class Impl> 1192817Sksewell@umich.eduvoid 1205250Sksewell@umich.eduO3ThreadContext<Impl>::suspend(int delay) 1212817Sksewell@umich.edu{ 1222875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1232875Sksewell@umich.edu getThreadNum()); 1242817Sksewell@umich.edu 1252817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1262817Sksewell@umich.edu return; 1272817Sksewell@umich.edu 1282817Sksewell@umich.edu#if FULL_SYSTEM 1292817Sksewell@umich.edu thread->lastActivate = curTick; 1302817Sksewell@umich.edu thread->lastSuspend = curTick; 1312817Sksewell@umich.edu#endif 1322817Sksewell@umich.edu/* 1332817Sksewell@umich.edu#if FULL_SYSTEM 1342817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1355704Snate@binkert.org if (cpu->checkInterrupts()) { 1362817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1372817Sksewell@umich.edu return; 1382817Sksewell@umich.edu } 1392817Sksewell@umich.edu#endif 1402817Sksewell@umich.edu*/ 1412817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1422817Sksewell@umich.edu cpu->suspendContext(thread->readTid()); 1432817Sksewell@umich.edu} 1442817Sksewell@umich.edu 1452817Sksewell@umich.edutemplate <class Impl> 1462817Sksewell@umich.eduvoid 1472875Sksewell@umich.eduO3ThreadContext<Impl>::deallocate(int delay) 1482817Sksewell@umich.edu{ 1493221Sktlim@umich.edu DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", 1503221Sktlim@umich.edu getThreadNum(), delay); 1512817Sksewell@umich.edu 1522817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) 1532817Sksewell@umich.edu return; 1542817Sksewell@umich.edu 1552817Sksewell@umich.edu thread->setStatus(ThreadContext::Unallocated); 1563221Sktlim@umich.edu cpu->deallocateContext(thread->readTid(), true, delay); 1572817Sksewell@umich.edu} 1582817Sksewell@umich.edu 1592817Sksewell@umich.edutemplate <class Impl> 1602817Sksewell@umich.eduvoid 1615250Sksewell@umich.eduO3ThreadContext<Impl>::halt(int delay) 1622817Sksewell@umich.edu{ 1632875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1642875Sksewell@umich.edu getThreadNum()); 1652817Sksewell@umich.edu 1662817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1672817Sksewell@umich.edu return; 1682817Sksewell@umich.edu 1692817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1702817Sksewell@umich.edu cpu->haltContext(thread->readTid()); 1712817Sksewell@umich.edu} 1722817Sksewell@umich.edu 1732817Sksewell@umich.edutemplate <class Impl> 1742817Sksewell@umich.eduvoid 1752817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1762817Sksewell@umich.edu{ 1772817Sksewell@umich.edu#if FULL_SYSTEM 1783548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1792817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1802817Sksewell@umich.edu#endif 1812817Sksewell@umich.edu} 1822817Sksewell@umich.edu 1832817Sksewell@umich.edutemplate <class Impl> 1842817Sksewell@umich.eduvoid 1852817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 1862817Sksewell@umich.edu{ 1872817Sksewell@umich.edu#if FULL_SYSTEM 1882817Sksewell@umich.edu if (thread->kernelStats) 1892817Sksewell@umich.edu thread->kernelStats->serialize(os); 1902817Sksewell@umich.edu#endif 1912817Sksewell@umich.edu 1922817Sksewell@umich.edu} 1932817Sksewell@umich.edu 1942817Sksewell@umich.edutemplate <class Impl> 1952817Sksewell@umich.eduvoid 1962817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1972817Sksewell@umich.edu{ 1982817Sksewell@umich.edu#if FULL_SYSTEM 1992817Sksewell@umich.edu if (thread->kernelStats) 2002817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 2012817Sksewell@umich.edu#endif 2022817Sksewell@umich.edu 2032817Sksewell@umich.edu} 2042817Sksewell@umich.edu 2052817Sksewell@umich.edu#if FULL_SYSTEM 2062817Sksewell@umich.edutemplate <class Impl> 2072817Sksewell@umich.eduTick 2082817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2092817Sksewell@umich.edu{ 2102817Sksewell@umich.edu return thread->lastActivate; 2112817Sksewell@umich.edu} 2122817Sksewell@umich.edu 2132817Sksewell@umich.edutemplate <class Impl> 2142817Sksewell@umich.eduTick 2152817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2162817Sksewell@umich.edu{ 2172817Sksewell@umich.edu return thread->lastSuspend; 2182817Sksewell@umich.edu} 2192817Sksewell@umich.edu 2202817Sksewell@umich.edutemplate <class Impl> 2212817Sksewell@umich.eduvoid 2222817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2233126Sktlim@umich.edu{ 2243126Sktlim@umich.edu thread->profileClear(); 2253126Sktlim@umich.edu} 2262817Sksewell@umich.edu 2272817Sksewell@umich.edutemplate <class Impl> 2282817Sksewell@umich.eduvoid 2292817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2303126Sktlim@umich.edu{ 2313126Sktlim@umich.edu thread->profileSample(); 2323126Sktlim@umich.edu} 2332817Sksewell@umich.edu#endif 2342817Sksewell@umich.edu 2352817Sksewell@umich.edutemplate <class Impl> 2362817Sksewell@umich.eduTheISA::MachInst 2372817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2382817Sksewell@umich.edu{ 2392817Sksewell@umich.edu return thread->getInst(); 2402817Sksewell@umich.edu} 2412817Sksewell@umich.edu 2422817Sksewell@umich.edutemplate <class Impl> 2432817Sksewell@umich.eduvoid 2442817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2452817Sksewell@umich.edu{ 2462817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2472817Sksewell@umich.edu // there are no instructions in the pipeline. 2482817Sksewell@umich.edu unsigned tid = thread->readTid(); 2492817Sksewell@umich.edu PhysRegIndex renamed_reg; 2502817Sksewell@umich.edu 2512817Sksewell@umich.edu // First loop through the integer registers. 2522817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2532817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2542817Sksewell@umich.edu 2552817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2562817Sksewell@umich.edu "now has data %lli.\n", 2572817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2582817Sksewell@umich.edu tc->readIntReg(i)); 2592817Sksewell@umich.edu 2602817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2612817Sksewell@umich.edu } 2622817Sksewell@umich.edu 2632817Sksewell@umich.edu // Then loop through the floating point registers. 2642817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2652817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2662817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2672817Sksewell@umich.edu tc->readFloatRegBits(i)); 2682817Sksewell@umich.edu } 2692817Sksewell@umich.edu 2702817Sksewell@umich.edu // Copy the misc regs. 2712986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2722817Sksewell@umich.edu 2735258Sksewell@umich.edu // Then finally set the PC, the next PC, the nextNPC, the micropc, and the 2745258Sksewell@umich.edu // next micropc. 2752817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2762817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2775258Sksewell@umich.edu cpu->setNextNPC(tc->readNextNPC(), tid); 2785258Sksewell@umich.edu cpu->setMicroPC(tc->readMicroPC(), tid); 2795258Sksewell@umich.edu cpu->setNextMicroPC(tc->readNextMicroPC(), tid); 2802817Sksewell@umich.edu#if !FULL_SYSTEM 2812817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2822817Sksewell@umich.edu#endif 2832817Sksewell@umich.edu} 2842817Sksewell@umich.edu 2852817Sksewell@umich.edutemplate <class Impl> 2862817Sksewell@umich.eduvoid 2872817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 2882817Sksewell@umich.edu{} 2892817Sksewell@umich.edu 2902817Sksewell@umich.edutemplate <class Impl> 2912817Sksewell@umich.eduuint64_t 2922817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 2932817Sksewell@umich.edu{ 2943776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 2952817Sksewell@umich.edu return cpu->readArchIntReg(reg_idx, thread->readTid()); 2962817Sksewell@umich.edu} 2972817Sksewell@umich.edu 2982817Sksewell@umich.edutemplate <class Impl> 2992986Sgblack@eecs.umich.eduTheISA::FloatReg 3002817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 3012817Sksewell@umich.edu{ 3025258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3032817Sksewell@umich.edu switch(width) { 3042817Sksewell@umich.edu case 32: 3052817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3062817Sksewell@umich.edu case 64: 3072817Sksewell@umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); 3082817Sksewell@umich.edu default: 3092817Sksewell@umich.edu panic("Unsupported width!"); 3102817Sksewell@umich.edu return 0; 3112817Sksewell@umich.edu } 3122817Sksewell@umich.edu} 3132817Sksewell@umich.edu 3142817Sksewell@umich.edutemplate <class Impl> 3152986Sgblack@eecs.umich.eduTheISA::FloatReg 3162817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 3172817Sksewell@umich.edu{ 3185258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3192817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3202817Sksewell@umich.edu} 3212817Sksewell@umich.edu 3222817Sksewell@umich.edutemplate <class Impl> 3232986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3242817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3252817Sksewell@umich.edu{ 3262817Sksewell@umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3275258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3282817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3292817Sksewell@umich.edu} 3302817Sksewell@umich.edu 3312817Sksewell@umich.edutemplate <class Impl> 3322986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3332817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3342817Sksewell@umich.edu{ 3355258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3362817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3372817Sksewell@umich.edu} 3382817Sksewell@umich.edu 3392817Sksewell@umich.edutemplate <class Impl> 3402817Sksewell@umich.eduvoid 3412817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3422817Sksewell@umich.edu{ 3433776Sgblack@eecs.umich.edu reg_idx = TheISA::flattenIntIndex(this, reg_idx); 3442817Sksewell@umich.edu cpu->setArchIntReg(reg_idx, val, thread->readTid()); 3452817Sksewell@umich.edu 3462817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3472817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3482817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3492817Sksewell@umich.edu } 3502817Sksewell@umich.edu} 3512817Sksewell@umich.edu 3522817Sksewell@umich.edutemplate <class Impl> 3532817Sksewell@umich.eduvoid 3542817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3552817Sksewell@umich.edu{ 3565258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3572817Sksewell@umich.edu switch(width) { 3582817Sksewell@umich.edu case 32: 3592817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3602817Sksewell@umich.edu break; 3612817Sksewell@umich.edu case 64: 3622817Sksewell@umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); 3632817Sksewell@umich.edu break; 3642817Sksewell@umich.edu } 3652817Sksewell@umich.edu 3662817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3672817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3682817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3692817Sksewell@umich.edu } 3702817Sksewell@umich.edu} 3712817Sksewell@umich.edu 3722817Sksewell@umich.edutemplate <class Impl> 3732817Sksewell@umich.eduvoid 3742817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3752817Sksewell@umich.edu{ 3765258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3772817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3782817Sksewell@umich.edu 3792817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3802817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3812817Sksewell@umich.edu } 3822817Sksewell@umich.edu} 3832817Sksewell@umich.edu 3842817Sksewell@umich.edutemplate <class Impl> 3852817Sksewell@umich.eduvoid 3862817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3872817Sksewell@umich.edu int width) 3882817Sksewell@umich.edu{ 3892817Sksewell@umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3905258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 3912817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 3922817Sksewell@umich.edu 3932817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3942817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3952817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3962817Sksewell@umich.edu } 3972817Sksewell@umich.edu} 3982817Sksewell@umich.edu 3992817Sksewell@umich.edutemplate <class Impl> 4002817Sksewell@umich.eduvoid 4012817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4022817Sksewell@umich.edu{ 4035258Sksewell@umich.edu reg_idx = TheISA::flattenFloatIndex(this, reg_idx); 4042817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 4052817Sksewell@umich.edu 4062817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4072817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4082817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4092817Sksewell@umich.edu } 4102817Sksewell@umich.edu} 4112817Sksewell@umich.edu 4122817Sksewell@umich.edutemplate <class Impl> 4132817Sksewell@umich.eduvoid 4142817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 4152817Sksewell@umich.edu{ 4162817Sksewell@umich.edu cpu->setPC(val, thread->readTid()); 4172817Sksewell@umich.edu 4182817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4192817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4202817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4212817Sksewell@umich.edu } 4222817Sksewell@umich.edu} 4232817Sksewell@umich.edu 4242817Sksewell@umich.edutemplate <class Impl> 4252817Sksewell@umich.eduvoid 4262817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4272817Sksewell@umich.edu{ 4282817Sksewell@umich.edu cpu->setNextPC(val, thread->readTid()); 4292817Sksewell@umich.edu 4302817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4312817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4322817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4332817Sksewell@umich.edu } 4342817Sksewell@umich.edu} 4352817Sksewell@umich.edu 4362817Sksewell@umich.edutemplate <class Impl> 4373468Sgblack@eecs.umich.eduvoid 4385258Sksewell@umich.eduO3ThreadContext<Impl>::setMicroPC(uint64_t val) 4395258Sksewell@umich.edu{ 4405258Sksewell@umich.edu cpu->setMicroPC(val, thread->readTid()); 4415258Sksewell@umich.edu 4425258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4435258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4445258Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4455258Sksewell@umich.edu } 4465258Sksewell@umich.edu} 4475258Sksewell@umich.edu 4485258Sksewell@umich.edutemplate <class Impl> 4495258Sksewell@umich.eduvoid 4505258Sksewell@umich.eduO3ThreadContext<Impl>::setNextMicroPC(uint64_t val) 4515258Sksewell@umich.edu{ 4525258Sksewell@umich.edu cpu->setNextMicroPC(val, thread->readTid()); 4535258Sksewell@umich.edu 4545258Sksewell@umich.edu // Squash if we're not already in a state update mode. 4555258Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4565258Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4575258Sksewell@umich.edu } 4585258Sksewell@umich.edu} 4595258Sksewell@umich.edu 4605258Sksewell@umich.edutemplate <class Impl> 4615258Sksewell@umich.eduvoid 4624172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4632817Sksewell@umich.edu{ 4644172Ssaidi@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); 4652817Sksewell@umich.edu 4662817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4672817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4682817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4692817Sksewell@umich.edu } 4702817Sksewell@umich.edu} 4712817Sksewell@umich.edu 4722817Sksewell@umich.edutemplate <class Impl> 4733468Sgblack@eecs.umich.eduvoid 4744172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, 4752817Sksewell@umich.edu const MiscReg &val) 4762817Sksewell@umich.edu{ 4774172Ssaidi@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->readTid()); 4782817Sksewell@umich.edu 4792817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4802817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4812817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4822817Sksewell@umich.edu } 4832817Sksewell@umich.edu} 4842817Sksewell@umich.edu 4852817Sksewell@umich.edu#if !FULL_SYSTEM 4862817Sksewell@umich.edu 4872817Sksewell@umich.edutemplate <class Impl> 4882817Sksewell@umich.eduTheISA::IntReg 4892817Sksewell@umich.eduO3ThreadContext<Impl>::getSyscallArg(int i) 4902817Sksewell@umich.edu{ 4912817Sksewell@umich.edu return cpu->getSyscallArg(i, thread->readTid()); 4922817Sksewell@umich.edu} 4932817Sksewell@umich.edu 4942817Sksewell@umich.edutemplate <class Impl> 4952817Sksewell@umich.eduvoid 4962817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 4972817Sksewell@umich.edu{ 4982817Sksewell@umich.edu cpu->setSyscallArg(i, val, thread->readTid()); 4992817Sksewell@umich.edu} 5002817Sksewell@umich.edu 5012817Sksewell@umich.edutemplate <class Impl> 5022817Sksewell@umich.eduvoid 5032817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 5042817Sksewell@umich.edu{ 5052817Sksewell@umich.edu cpu->setSyscallReturn(return_value, thread->readTid()); 5062817Sksewell@umich.edu} 5072817Sksewell@umich.edu 5082817Sksewell@umich.edu#endif // FULL_SYSTEM 5092817Sksewell@umich.edu 510