thread_context_impl.hh revision 3686
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 32817Sksewell@umich.edu * All rights reserved. 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142817Sksewell@umich.edu * this software without specific prior written permission. 152817Sksewell@umich.edu * 162817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * Authors: Kevin Lim 292817Sksewell@umich.edu * Korey Sewell 302817Sksewell@umich.edu */ 312817Sksewell@umich.edu 322817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 332834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 342817Sksewell@umich.edu 352817Sksewell@umich.edu#if FULL_SYSTEM 362817Sksewell@umich.edutemplate <class Impl> 372817Sksewell@umich.eduVirtualPort * 382817Sksewell@umich.eduO3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc) 392817Sksewell@umich.edu{ 402817Sksewell@umich.edu if (!src_tc) 412817Sksewell@umich.edu return thread->getVirtPort(); 422817Sksewell@umich.edu 432817Sksewell@umich.edu VirtualPort *vp; 442817Sksewell@umich.edu 452817Sksewell@umich.edu vp = new VirtualPort("tc-vport", src_tc); 463675Sktlim@umich.edu thread->connectToMemFunc(vp); 472817Sksewell@umich.edu return vp; 482817Sksewell@umich.edu} 492817Sksewell@umich.edu 502817Sksewell@umich.edutemplate <class Impl> 512817Sksewell@umich.eduvoid 522817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 532817Sksewell@umich.edu{ 543126Sktlim@umich.edu thread->dumpFuncProfile(); 552817Sksewell@umich.edu} 562817Sksewell@umich.edu#endif 572817Sksewell@umich.edu 582817Sksewell@umich.edutemplate <class Impl> 592817Sksewell@umich.eduvoid 602817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 612817Sksewell@umich.edu{ 622817Sksewell@umich.edu // some things should already be set up 632817Sksewell@umich.edu#if FULL_SYSTEM 642817Sksewell@umich.edu assert(getSystemPtr() == old_context->getSystemPtr()); 652817Sksewell@umich.edu#else 662817Sksewell@umich.edu assert(getProcessPtr() == old_context->getProcessPtr()); 672817Sksewell@umich.edu#endif 682817Sksewell@umich.edu 692817Sksewell@umich.edu // copy over functional state 702817Sksewell@umich.edu setStatus(old_context->status()); 712817Sksewell@umich.edu copyArchRegs(old_context); 722817Sksewell@umich.edu setCpuId(old_context->readCpuId()); 732817Sksewell@umich.edu 742817Sksewell@umich.edu#if !FULL_SYSTEM 752817Sksewell@umich.edu thread->funcExeInst = old_context->readFuncExeInst(); 762817Sksewell@umich.edu#else 772817Sksewell@umich.edu EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); 782817Sksewell@umich.edu if (other_quiesce) { 792817Sksewell@umich.edu // Point the quiesce event's TC at this TC so that it wakes up 802817Sksewell@umich.edu // the proper CPU. 812817Sksewell@umich.edu other_quiesce->tc = this; 822817Sksewell@umich.edu } 832817Sksewell@umich.edu if (thread->quiesceEvent) { 842817Sksewell@umich.edu thread->quiesceEvent->tc = this; 852817Sksewell@umich.edu } 862817Sksewell@umich.edu 872817Sksewell@umich.edu // Transfer kernel stats from one CPU to the other. 882817Sksewell@umich.edu thread->kernelStats = old_context->getKernelStats(); 892817Sksewell@umich.edu// storeCondFailures = 0; 902817Sksewell@umich.edu cpu->lockFlag = false; 912817Sksewell@umich.edu#endif 922817Sksewell@umich.edu 932817Sksewell@umich.edu old_context->setStatus(ThreadContext::Unallocated); 942817Sksewell@umich.edu 952817Sksewell@umich.edu thread->inSyscall = false; 962817Sksewell@umich.edu thread->trapPending = false; 972817Sksewell@umich.edu} 982817Sksewell@umich.edu 992817Sksewell@umich.edu#if FULL_SYSTEM 1002817Sksewell@umich.edutemplate <class Impl> 1012817Sksewell@umich.eduvoid 1022817Sksewell@umich.eduO3ThreadContext<Impl>::delVirtPort(VirtualPort *vp) 1032817Sksewell@umich.edu{ 1043686Sktlim@umich.edu if (vp != thread->getVirtPort()) { 1053686Sktlim@umich.edu delete vp->getPeer(); 1063686Sktlim@umich.edu delete vp; 1073686Sktlim@umich.edu } 1082817Sksewell@umich.edu} 1092817Sksewell@umich.edu#endif 1102817Sksewell@umich.edu 1112817Sksewell@umich.edutemplate <class Impl> 1122817Sksewell@umich.eduvoid 1132817Sksewell@umich.eduO3ThreadContext<Impl>::activate(int delay) 1142817Sksewell@umich.edu{ 1152875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 1162875Sksewell@umich.edu getThreadNum()); 1172817Sksewell@umich.edu 1182817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 1192817Sksewell@umich.edu return; 1202817Sksewell@umich.edu 1212817Sksewell@umich.edu#if FULL_SYSTEM 1222817Sksewell@umich.edu thread->lastActivate = curTick; 1232817Sksewell@umich.edu#endif 1242817Sksewell@umich.edu 1252817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) { 1262817Sksewell@umich.edu cpu->activateWhenReady(thread->readTid()); 1272817Sksewell@umich.edu return; 1282817Sksewell@umich.edu } 1292817Sksewell@umich.edu 1302817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 1312817Sksewell@umich.edu 1322817Sksewell@umich.edu // status() == Suspended 1332817Sksewell@umich.edu cpu->activateContext(thread->readTid(), delay); 1342817Sksewell@umich.edu} 1352817Sksewell@umich.edu 1362817Sksewell@umich.edutemplate <class Impl> 1372817Sksewell@umich.eduvoid 1382817Sksewell@umich.eduO3ThreadContext<Impl>::suspend() 1392817Sksewell@umich.edu{ 1402875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1412875Sksewell@umich.edu getThreadNum()); 1422817Sksewell@umich.edu 1432817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1442817Sksewell@umich.edu return; 1452817Sksewell@umich.edu 1462817Sksewell@umich.edu#if FULL_SYSTEM 1472817Sksewell@umich.edu thread->lastActivate = curTick; 1482817Sksewell@umich.edu thread->lastSuspend = curTick; 1492817Sksewell@umich.edu#endif 1502817Sksewell@umich.edu/* 1512817Sksewell@umich.edu#if FULL_SYSTEM 1522817Sksewell@umich.edu // Don't change the status from active if there are pending interrupts 1532817Sksewell@umich.edu if (cpu->check_interrupts()) { 1542817Sksewell@umich.edu assert(status() == ThreadContext::Active); 1552817Sksewell@umich.edu return; 1562817Sksewell@umich.edu } 1572817Sksewell@umich.edu#endif 1582817Sksewell@umich.edu*/ 1592817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1602817Sksewell@umich.edu cpu->suspendContext(thread->readTid()); 1612817Sksewell@umich.edu} 1622817Sksewell@umich.edu 1632817Sksewell@umich.edutemplate <class Impl> 1642817Sksewell@umich.eduvoid 1652875Sksewell@umich.eduO3ThreadContext<Impl>::deallocate(int delay) 1662817Sksewell@umich.edu{ 1673221Sktlim@umich.edu DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n", 1683221Sktlim@umich.edu getThreadNum(), delay); 1692817Sksewell@umich.edu 1702817Sksewell@umich.edu if (thread->status() == ThreadContext::Unallocated) 1712817Sksewell@umich.edu return; 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu thread->setStatus(ThreadContext::Unallocated); 1743221Sktlim@umich.edu cpu->deallocateContext(thread->readTid(), true, delay); 1752817Sksewell@umich.edu} 1762817Sksewell@umich.edu 1772817Sksewell@umich.edutemplate <class Impl> 1782817Sksewell@umich.eduvoid 1792817Sksewell@umich.eduO3ThreadContext<Impl>::halt() 1802817Sksewell@umich.edu{ 1812875Sksewell@umich.edu DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", 1822875Sksewell@umich.edu getThreadNum()); 1832817Sksewell@umich.edu 1842817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1852817Sksewell@umich.edu return; 1862817Sksewell@umich.edu 1872817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1882817Sksewell@umich.edu cpu->haltContext(thread->readTid()); 1892817Sksewell@umich.edu} 1902817Sksewell@umich.edu 1912817Sksewell@umich.edutemplate <class Impl> 1922817Sksewell@umich.eduvoid 1932817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1942817Sksewell@umich.edu{ 1952817Sksewell@umich.edu#if FULL_SYSTEM 1963548Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1972817Sksewell@umich.edu thread->kernelStats->regStats(name + ".kern"); 1982817Sksewell@umich.edu#endif 1992817Sksewell@umich.edu} 2002817Sksewell@umich.edu 2012817Sksewell@umich.edutemplate <class Impl> 2022817Sksewell@umich.eduvoid 2032817Sksewell@umich.eduO3ThreadContext<Impl>::serialize(std::ostream &os) 2042817Sksewell@umich.edu{ 2052817Sksewell@umich.edu#if FULL_SYSTEM 2062817Sksewell@umich.edu if (thread->kernelStats) 2072817Sksewell@umich.edu thread->kernelStats->serialize(os); 2082817Sksewell@umich.edu#endif 2092817Sksewell@umich.edu 2102817Sksewell@umich.edu} 2112817Sksewell@umich.edu 2122817Sksewell@umich.edutemplate <class Impl> 2132817Sksewell@umich.eduvoid 2142817Sksewell@umich.eduO3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 2152817Sksewell@umich.edu{ 2162817Sksewell@umich.edu#if FULL_SYSTEM 2172817Sksewell@umich.edu if (thread->kernelStats) 2182817Sksewell@umich.edu thread->kernelStats->unserialize(cp, section); 2192817Sksewell@umich.edu#endif 2202817Sksewell@umich.edu 2212817Sksewell@umich.edu} 2222817Sksewell@umich.edu 2232817Sksewell@umich.edu#if FULL_SYSTEM 2242817Sksewell@umich.edutemplate <class Impl> 2252817Sksewell@umich.eduTick 2262817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 2272817Sksewell@umich.edu{ 2282817Sksewell@umich.edu return thread->lastActivate; 2292817Sksewell@umich.edu} 2302817Sksewell@umich.edu 2312817Sksewell@umich.edutemplate <class Impl> 2322817Sksewell@umich.eduTick 2332817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 2342817Sksewell@umich.edu{ 2352817Sksewell@umich.edu return thread->lastSuspend; 2362817Sksewell@umich.edu} 2372817Sksewell@umich.edu 2382817Sksewell@umich.edutemplate <class Impl> 2392817Sksewell@umich.eduvoid 2402817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 2413126Sktlim@umich.edu{ 2423126Sktlim@umich.edu thread->profileClear(); 2433126Sktlim@umich.edu} 2442817Sksewell@umich.edu 2452817Sksewell@umich.edutemplate <class Impl> 2462817Sksewell@umich.eduvoid 2472817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 2483126Sktlim@umich.edu{ 2493126Sktlim@umich.edu thread->profileSample(); 2503126Sktlim@umich.edu} 2512817Sksewell@umich.edu#endif 2522817Sksewell@umich.edu 2532817Sksewell@umich.edutemplate <class Impl> 2542817Sksewell@umich.eduTheISA::MachInst 2552817Sksewell@umich.eduO3ThreadContext<Impl>:: getInst() 2562817Sksewell@umich.edu{ 2572817Sksewell@umich.edu return thread->getInst(); 2582817Sksewell@umich.edu} 2592817Sksewell@umich.edu 2602817Sksewell@umich.edutemplate <class Impl> 2612817Sksewell@umich.eduvoid 2622817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 2632817Sksewell@umich.edu{ 2642817Sksewell@umich.edu // This function will mess things up unless the ROB is empty and 2652817Sksewell@umich.edu // there are no instructions in the pipeline. 2662817Sksewell@umich.edu unsigned tid = thread->readTid(); 2672817Sksewell@umich.edu PhysRegIndex renamed_reg; 2682817Sksewell@umich.edu 2692817Sksewell@umich.edu // First loop through the integer registers. 2702817Sksewell@umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 2712817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i); 2722817Sksewell@umich.edu 2732817Sksewell@umich.edu DPRINTF(O3CPU, "Copying over register %i, had data %lli, " 2742817Sksewell@umich.edu "now has data %lli.\n", 2752817Sksewell@umich.edu renamed_reg, cpu->readIntReg(renamed_reg), 2762817Sksewell@umich.edu tc->readIntReg(i)); 2772817Sksewell@umich.edu 2782817Sksewell@umich.edu cpu->setIntReg(renamed_reg, tc->readIntReg(i)); 2792817Sksewell@umich.edu } 2802817Sksewell@umich.edu 2812817Sksewell@umich.edu // Then loop through the floating point registers. 2822817Sksewell@umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 2832817Sksewell@umich.edu renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag); 2842817Sksewell@umich.edu cpu->setFloatRegBits(renamed_reg, 2852817Sksewell@umich.edu tc->readFloatRegBits(i)); 2862817Sksewell@umich.edu } 2872817Sksewell@umich.edu 2882817Sksewell@umich.edu // Copy the misc regs. 2892986Sgblack@eecs.umich.edu TheISA::copyMiscRegs(tc, this); 2902817Sksewell@umich.edu 2912817Sksewell@umich.edu // Then finally set the PC and the next PC. 2922817Sksewell@umich.edu cpu->setPC(tc->readPC(), tid); 2932817Sksewell@umich.edu cpu->setNextPC(tc->readNextPC(), tid); 2942817Sksewell@umich.edu#if !FULL_SYSTEM 2952817Sksewell@umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 2962817Sksewell@umich.edu#endif 2972817Sksewell@umich.edu} 2982817Sksewell@umich.edu 2992817Sksewell@umich.edutemplate <class Impl> 3002817Sksewell@umich.eduvoid 3012817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 3022817Sksewell@umich.edu{} 3032817Sksewell@umich.edu 3042817Sksewell@umich.edutemplate <class Impl> 3052817Sksewell@umich.eduuint64_t 3062817Sksewell@umich.eduO3ThreadContext<Impl>::readIntReg(int reg_idx) 3072817Sksewell@umich.edu{ 3082817Sksewell@umich.edu return cpu->readArchIntReg(reg_idx, thread->readTid()); 3092817Sksewell@umich.edu} 3102817Sksewell@umich.edu 3112817Sksewell@umich.edutemplate <class Impl> 3122986Sgblack@eecs.umich.eduTheISA::FloatReg 3132817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) 3142817Sksewell@umich.edu{ 3152817Sksewell@umich.edu switch(width) { 3162817Sksewell@umich.edu case 32: 3172817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3182817Sksewell@umich.edu case 64: 3192817Sksewell@umich.edu return cpu->readArchFloatRegDouble(reg_idx, thread->readTid()); 3202817Sksewell@umich.edu default: 3212817Sksewell@umich.edu panic("Unsupported width!"); 3222817Sksewell@umich.edu return 0; 3232817Sksewell@umich.edu } 3242817Sksewell@umich.edu} 3252817Sksewell@umich.edu 3262817Sksewell@umich.edutemplate <class Impl> 3272986Sgblack@eecs.umich.eduTheISA::FloatReg 3282817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatReg(int reg_idx) 3292817Sksewell@umich.edu{ 3302817Sksewell@umich.edu return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); 3312817Sksewell@umich.edu} 3322817Sksewell@umich.edu 3332817Sksewell@umich.edutemplate <class Impl> 3342986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3352817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) 3362817Sksewell@umich.edu{ 3372817Sksewell@umich.edu DPRINTF(Fault, "Reading floatint register through the TC!\n"); 3382817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3392817Sksewell@umich.edu} 3402817Sksewell@umich.edu 3412817Sksewell@umich.edutemplate <class Impl> 3422986Sgblack@eecs.umich.eduTheISA::FloatRegBits 3432817Sksewell@umich.eduO3ThreadContext<Impl>::readFloatRegBits(int reg_idx) 3442817Sksewell@umich.edu{ 3452817Sksewell@umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); 3462817Sksewell@umich.edu} 3472817Sksewell@umich.edu 3482817Sksewell@umich.edutemplate <class Impl> 3492817Sksewell@umich.eduvoid 3502817Sksewell@umich.eduO3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val) 3512817Sksewell@umich.edu{ 3522817Sksewell@umich.edu cpu->setArchIntReg(reg_idx, val, thread->readTid()); 3532817Sksewell@umich.edu 3542817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3552817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3562817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3572817Sksewell@umich.edu } 3582817Sksewell@umich.edu} 3592817Sksewell@umich.edu 3602817Sksewell@umich.edutemplate <class Impl> 3612817Sksewell@umich.eduvoid 3622817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3632817Sksewell@umich.edu{ 3642817Sksewell@umich.edu switch(width) { 3652817Sksewell@umich.edu case 32: 3662817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3672817Sksewell@umich.edu break; 3682817Sksewell@umich.edu case 64: 3692817Sksewell@umich.edu cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid()); 3702817Sksewell@umich.edu break; 3712817Sksewell@umich.edu } 3722817Sksewell@umich.edu 3732817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3742817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3752817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3762817Sksewell@umich.edu } 3772817Sksewell@umich.edu} 3782817Sksewell@umich.edu 3792817Sksewell@umich.edutemplate <class Impl> 3802817Sksewell@umich.eduvoid 3812817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) 3822817Sksewell@umich.edu{ 3832817Sksewell@umich.edu cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); 3842817Sksewell@umich.edu 3852817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 3862817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 3872817Sksewell@umich.edu } 3882817Sksewell@umich.edu} 3892817Sksewell@umich.edu 3902817Sksewell@umich.edutemplate <class Impl> 3912817Sksewell@umich.eduvoid 3922817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, 3932817Sksewell@umich.edu int width) 3942817Sksewell@umich.edu{ 3952817Sksewell@umich.edu DPRINTF(Fault, "Setting floatint register through the TC!\n"); 3962817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 3972817Sksewell@umich.edu 3982817Sksewell@umich.edu // Squash if we're not already in a state update mode. 3992817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4002817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4012817Sksewell@umich.edu } 4022817Sksewell@umich.edu} 4032817Sksewell@umich.edu 4042817Sksewell@umich.edutemplate <class Impl> 4052817Sksewell@umich.eduvoid 4062817Sksewell@umich.eduO3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4072817Sksewell@umich.edu{ 4082817Sksewell@umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); 4092817Sksewell@umich.edu 4102817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4112817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4122817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4132817Sksewell@umich.edu } 4142817Sksewell@umich.edu} 4152817Sksewell@umich.edu 4162817Sksewell@umich.edutemplate <class Impl> 4172817Sksewell@umich.eduvoid 4182817Sksewell@umich.eduO3ThreadContext<Impl>::setPC(uint64_t val) 4192817Sksewell@umich.edu{ 4202817Sksewell@umich.edu cpu->setPC(val, thread->readTid()); 4212817Sksewell@umich.edu 4222817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4232817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4242817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4252817Sksewell@umich.edu } 4262817Sksewell@umich.edu} 4272817Sksewell@umich.edu 4282817Sksewell@umich.edutemplate <class Impl> 4292817Sksewell@umich.eduvoid 4302817Sksewell@umich.eduO3ThreadContext<Impl>::setNextPC(uint64_t val) 4312817Sksewell@umich.edu{ 4322817Sksewell@umich.edu cpu->setNextPC(val, thread->readTid()); 4332817Sksewell@umich.edu 4342817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4352817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4362817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4372817Sksewell@umich.edu } 4382817Sksewell@umich.edu} 4392817Sksewell@umich.edu 4402817Sksewell@umich.edutemplate <class Impl> 4413468Sgblack@eecs.umich.eduvoid 4422817Sksewell@umich.eduO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 4432817Sksewell@umich.edu{ 4443468Sgblack@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->readTid()); 4452817Sksewell@umich.edu 4462817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4472817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4482817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4492817Sksewell@umich.edu } 4502817Sksewell@umich.edu} 4512817Sksewell@umich.edu 4522817Sksewell@umich.edutemplate <class Impl> 4533468Sgblack@eecs.umich.eduvoid 4542817Sksewell@umich.eduO3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg, 4552817Sksewell@umich.edu const MiscReg &val) 4562817Sksewell@umich.edu{ 4573468Sgblack@eecs.umich.edu cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); 4582817Sksewell@umich.edu 4592817Sksewell@umich.edu // Squash if we're not already in a state update mode. 4602817Sksewell@umich.edu if (!thread->trapPending && !thread->inSyscall) { 4612817Sksewell@umich.edu cpu->squashFromTC(thread->readTid()); 4622817Sksewell@umich.edu } 4632817Sksewell@umich.edu} 4642817Sksewell@umich.edu 4652817Sksewell@umich.edu#if !FULL_SYSTEM 4662817Sksewell@umich.edu 4672817Sksewell@umich.edutemplate <class Impl> 4682817Sksewell@umich.eduTheISA::IntReg 4692817Sksewell@umich.eduO3ThreadContext<Impl>::getSyscallArg(int i) 4702817Sksewell@umich.edu{ 4712817Sksewell@umich.edu return cpu->getSyscallArg(i, thread->readTid()); 4722817Sksewell@umich.edu} 4732817Sksewell@umich.edu 4742817Sksewell@umich.edutemplate <class Impl> 4752817Sksewell@umich.eduvoid 4762817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallArg(int i, IntReg val) 4772817Sksewell@umich.edu{ 4782817Sksewell@umich.edu cpu->setSyscallArg(i, val, thread->readTid()); 4792817Sksewell@umich.edu} 4802817Sksewell@umich.edu 4812817Sksewell@umich.edutemplate <class Impl> 4822817Sksewell@umich.eduvoid 4832817Sksewell@umich.eduO3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value) 4842817Sksewell@umich.edu{ 4852817Sksewell@umich.edu cpu->setSyscallReturn(return_value, thread->readTid()); 4862817Sksewell@umich.edu} 4872817Sksewell@umich.edu 4882817Sksewell@umich.edu#endif // FULL_SYSTEM 4892817Sksewell@umich.edu 490