thread_context_impl.hh revision 12106
12817Sksewell@umich.edu/* 29426SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47763SAli.Saidi@ARM.com * All rights reserved 57763SAli.Saidi@ARM.com * 67763SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77763SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87763SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97763SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107763SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117763SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127763SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137763SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147763SAli.Saidi@ARM.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu * Korey Sewell 432817Sksewell@umich.edu */ 442817Sksewell@umich.edu 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__ 479944Smatt.horsnell@ARM.com 488793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 512817Sksewell@umich.edu#include "cpu/o3/thread_context.hh" 522834Sksewell@umich.edu#include "cpu/quiesce_event.hh" 538232Snate@binkert.org#include "debug/O3CPU.hh" 542817Sksewell@umich.edu 552817Sksewell@umich.edutemplate <class Impl> 568852Sandreas.hansson@arm.comFSTranslatingPortProxy& 578706Sandreas.hansson@arm.comO3ThreadContext<Impl>::getVirtProxy() 582817Sksewell@umich.edu{ 598706Sandreas.hansson@arm.com return thread->getVirtProxy(); 602817Sksewell@umich.edu} 612817Sksewell@umich.edu 622817Sksewell@umich.edutemplate <class Impl> 632817Sksewell@umich.eduvoid 642817Sksewell@umich.eduO3ThreadContext<Impl>::dumpFuncProfile() 652817Sksewell@umich.edu{ 663126Sktlim@umich.edu thread->dumpFuncProfile(); 672817Sksewell@umich.edu} 682817Sksewell@umich.edu 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.eduvoid 712817Sksewell@umich.eduO3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context) 722817Sksewell@umich.edu{ 739441SAndreas.Sandberg@ARM.com ::takeOverFrom(*this, *old_context); 749478Snilay@cs.wisc.edu TheISA::Decoder *newDecoder = getDecoderPtr(); 759478Snilay@cs.wisc.edu TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 769478Snilay@cs.wisc.edu newDecoder->takeOverFrom(oldDecoder); 772817Sksewell@umich.edu 789441SAndreas.Sandberg@ARM.com thread->kernelStats = old_context->getKernelStats(); 799441SAndreas.Sandberg@ARM.com thread->funcExeInst = old_context->readFuncExeInst(); 802817Sksewell@umich.edu 819382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 822817Sksewell@umich.edu thread->trapPending = false; 832817Sksewell@umich.edu} 842817Sksewell@umich.edu 852817Sksewell@umich.edutemplate <class Impl> 862817Sksewell@umich.eduvoid 8710407Smitch.hayenga@arm.comO3ThreadContext<Impl>::activate() 882817Sksewell@umich.edu{ 892875Sksewell@umich.edu DPRINTF(O3CPU, "Calling activate on Thread Context %d\n", 905715Shsul@eecs.umich.edu threadId()); 912817Sksewell@umich.edu 922817Sksewell@umich.edu if (thread->status() == ThreadContext::Active) 932817Sksewell@umich.edu return; 942817Sksewell@umich.edu 957823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 962817Sksewell@umich.edu thread->setStatus(ThreadContext::Active); 972817Sksewell@umich.edu 982817Sksewell@umich.edu // status() == Suspended 9910407Smitch.hayenga@arm.com cpu->activateContext(thread->threadId()); 1002817Sksewell@umich.edu} 1012817Sksewell@umich.edu 1022817Sksewell@umich.edutemplate <class Impl> 1032817Sksewell@umich.eduvoid 10410407Smitch.hayenga@arm.comO3ThreadContext<Impl>::suspend() 1052817Sksewell@umich.edu{ 1062875Sksewell@umich.edu DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n", 1075715Shsul@eecs.umich.edu threadId()); 1082817Sksewell@umich.edu 1092817Sksewell@umich.edu if (thread->status() == ThreadContext::Suspended) 1102817Sksewell@umich.edu return; 1112817Sksewell@umich.edu 1127823Ssteve.reinhardt@amd.com thread->lastActivate = curTick(); 1137823Ssteve.reinhardt@amd.com thread->lastSuspend = curTick(); 1148793Sgblack@eecs.umich.edu 1152817Sksewell@umich.edu thread->setStatus(ThreadContext::Suspended); 1165715Shsul@eecs.umich.edu cpu->suspendContext(thread->threadId()); 1172817Sksewell@umich.edu} 1182817Sksewell@umich.edu 1192817Sksewell@umich.edutemplate <class Impl> 1202817Sksewell@umich.eduvoid 12110407Smitch.hayenga@arm.comO3ThreadContext<Impl>::halt() 1222817Sksewell@umich.edu{ 12310407Smitch.hayenga@arm.com DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId()); 1242817Sksewell@umich.edu 1252817Sksewell@umich.edu if (thread->status() == ThreadContext::Halted) 1262817Sksewell@umich.edu return; 1272817Sksewell@umich.edu 1282817Sksewell@umich.edu thread->setStatus(ThreadContext::Halted); 1295715Shsul@eecs.umich.edu cpu->haltContext(thread->threadId()); 1302817Sksewell@umich.edu} 1312817Sksewell@umich.edu 1322817Sksewell@umich.edutemplate <class Impl> 1332817Sksewell@umich.eduvoid 1342817Sksewell@umich.eduO3ThreadContext<Impl>::regStats(const std::string &name) 1352817Sksewell@umich.edu{ 1368793Sgblack@eecs.umich.edu if (FullSystem) { 1378793Sgblack@eecs.umich.edu thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); 1388793Sgblack@eecs.umich.edu thread->kernelStats->regStats(name + ".kern"); 1398793Sgblack@eecs.umich.edu } 1402817Sksewell@umich.edu} 1412817Sksewell@umich.edu 1422817Sksewell@umich.edutemplate <class Impl> 1432817Sksewell@umich.eduTick 1442817Sksewell@umich.eduO3ThreadContext<Impl>::readLastActivate() 1452817Sksewell@umich.edu{ 1462817Sksewell@umich.edu return thread->lastActivate; 1472817Sksewell@umich.edu} 1482817Sksewell@umich.edu 1492817Sksewell@umich.edutemplate <class Impl> 1502817Sksewell@umich.eduTick 1512817Sksewell@umich.eduO3ThreadContext<Impl>::readLastSuspend() 1522817Sksewell@umich.edu{ 1532817Sksewell@umich.edu return thread->lastSuspend; 1542817Sksewell@umich.edu} 1552817Sksewell@umich.edu 1562817Sksewell@umich.edutemplate <class Impl> 1572817Sksewell@umich.eduvoid 1582817Sksewell@umich.eduO3ThreadContext<Impl>::profileClear() 1593126Sktlim@umich.edu{ 1603126Sktlim@umich.edu thread->profileClear(); 1613126Sktlim@umich.edu} 1622817Sksewell@umich.edu 1632817Sksewell@umich.edutemplate <class Impl> 1642817Sksewell@umich.eduvoid 1652817Sksewell@umich.eduO3ThreadContext<Impl>::profileSample() 1663126Sktlim@umich.edu{ 1673126Sktlim@umich.edu thread->profileSample(); 1683126Sktlim@umich.edu} 1692817Sksewell@umich.edu 1702817Sksewell@umich.edutemplate <class Impl> 1712817Sksewell@umich.eduvoid 1722817Sksewell@umich.eduO3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) 1732817Sksewell@umich.edu{ 1748208SAli.Saidi@ARM.com // Prevent squashing 1759382SAli.Saidi@ARM.com thread->noSquashFromTC = true; 1768208SAli.Saidi@ARM.com TheISA::copyRegs(tc, this); 1779382SAli.Saidi@ARM.com thread->noSquashFromTC = false; 1782817Sksewell@umich.edu 1798793Sgblack@eecs.umich.edu if (!FullSystem) 1808793Sgblack@eecs.umich.edu this->thread->funcExeInst = tc->readFuncExeInst(); 1812817Sksewell@umich.edu} 1822817Sksewell@umich.edu 1832817Sksewell@umich.edutemplate <class Impl> 1842817Sksewell@umich.eduvoid 1852817Sksewell@umich.eduO3ThreadContext<Impl>::clearArchRegs() 1867763SAli.Saidi@ARM.com{ 1879384SAndreas.Sandberg@arm.com cpu->isa[thread->threadId()]->clear(); 1887763SAli.Saidi@ARM.com} 1892817Sksewell@umich.edu 1902817Sksewell@umich.edutemplate <class Impl> 1912817Sksewell@umich.eduuint64_t 1929426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readIntRegFlat(int reg_idx) 1932817Sksewell@umich.edu{ 1945715Shsul@eecs.umich.edu return cpu->readArchIntReg(reg_idx, thread->threadId()); 1952817Sksewell@umich.edu} 1962817Sksewell@umich.edu 1972817Sksewell@umich.edutemplate <class Impl> 1982986Sgblack@eecs.umich.eduTheISA::FloatReg 1999426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) 2002817Sksewell@umich.edu{ 2016314Sgblack@eecs.umich.edu return cpu->readArchFloatReg(reg_idx, thread->threadId()); 2022817Sksewell@umich.edu} 2032817Sksewell@umich.edu 2042817Sksewell@umich.edutemplate <class Impl> 2052986Sgblack@eecs.umich.eduTheISA::FloatRegBits 2069426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) 2072817Sksewell@umich.edu{ 2085715Shsul@eecs.umich.edu return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); 2092817Sksewell@umich.edu} 2102817Sksewell@umich.edu 2112817Sksewell@umich.edutemplate <class Impl> 2129920Syasuko.eckert@amd.comTheISA::CCReg 2139920Syasuko.eckert@amd.comO3ThreadContext<Impl>::readCCRegFlat(int reg_idx) 2149920Syasuko.eckert@amd.com{ 2159920Syasuko.eckert@amd.com return cpu->readArchCCReg(reg_idx, thread->threadId()); 2169920Syasuko.eckert@amd.com} 2179920Syasuko.eckert@amd.com 2189920Syasuko.eckert@amd.comtemplate <class Impl> 2192817Sksewell@umich.eduvoid 2209426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) 2212817Sksewell@umich.edu{ 2225715Shsul@eecs.umich.edu cpu->setArchIntReg(reg_idx, val, thread->threadId()); 2232817Sksewell@umich.edu 2249382SAli.Saidi@ARM.com conditionalSquash(); 2252817Sksewell@umich.edu} 2262817Sksewell@umich.edu 2272817Sksewell@umich.edutemplate <class Impl> 2282817Sksewell@umich.eduvoid 2299426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val) 2302817Sksewell@umich.edu{ 2316314Sgblack@eecs.umich.edu cpu->setArchFloatReg(reg_idx, val, thread->threadId()); 2322817Sksewell@umich.edu 2339382SAli.Saidi@ARM.com conditionalSquash(); 2342817Sksewell@umich.edu} 2352817Sksewell@umich.edu 2362817Sksewell@umich.edutemplate <class Impl> 2372817Sksewell@umich.eduvoid 2389426SAndreas.Sandberg@ARM.comO3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) 2392817Sksewell@umich.edu{ 2405715Shsul@eecs.umich.edu cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); 2412817Sksewell@umich.edu 2429382SAli.Saidi@ARM.com conditionalSquash(); 2432817Sksewell@umich.edu} 2442817Sksewell@umich.edu 2452817Sksewell@umich.edutemplate <class Impl> 2462817Sksewell@umich.eduvoid 2479920Syasuko.eckert@amd.comO3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val) 2489920Syasuko.eckert@amd.com{ 2499920Syasuko.eckert@amd.com cpu->setArchCCReg(reg_idx, val, thread->threadId()); 2509920Syasuko.eckert@amd.com 2519920Syasuko.eckert@amd.com conditionalSquash(); 2529920Syasuko.eckert@amd.com} 2539920Syasuko.eckert@amd.com 2549920Syasuko.eckert@amd.comtemplate <class Impl> 2559920Syasuko.eckert@amd.comvoid 2567720Sgblack@eecs.umich.eduO3ThreadContext<Impl>::pcState(const TheISA::PCState &val) 2572817Sksewell@umich.edu{ 2587720Sgblack@eecs.umich.edu cpu->pcState(val, thread->threadId()); 2595258Sksewell@umich.edu 2609382SAli.Saidi@ARM.com conditionalSquash(); 2615258Sksewell@umich.edu} 2625258Sksewell@umich.edu 2638733Sgeoffrey.blake@arm.comtemplate <class Impl> 2648733Sgeoffrey.blake@arm.comvoid 2658733Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val) 2668733Sgeoffrey.blake@arm.com{ 2678733Sgeoffrey.blake@arm.com cpu->pcState(val, thread->threadId()); 2688733Sgeoffrey.blake@arm.com 2699382SAli.Saidi@ARM.com conditionalSquash(); 2708733Sgeoffrey.blake@arm.com} 2718733Sgeoffrey.blake@arm.com 2725258Sksewell@umich.edutemplate <class Impl> 27312106SRekai.GonzalezAlberquilla@arm.comRegId 27412106SRekai.GonzalezAlberquilla@arm.comO3ThreadContext<Impl>::flattenRegId(const RegId& regId) const 2756313Sgblack@eecs.umich.edu{ 27612106SRekai.GonzalezAlberquilla@arm.com return cpu->isa[thread->threadId()]->flattenRegId(regId); 27710033SAli.Saidi@ARM.com} 27810033SAli.Saidi@ARM.com 27910033SAli.Saidi@ARM.comtemplate <class Impl> 2805258Sksewell@umich.eduvoid 2814172Ssaidi@eecs.umich.eduO3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2822817Sksewell@umich.edu{ 2835715Shsul@eecs.umich.edu cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 2842817Sksewell@umich.edu 2859382SAli.Saidi@ARM.com conditionalSquash(); 2862817Sksewell@umich.edu} 2872817Sksewell@umich.edu 2889944Smatt.horsnell@ARM.com#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__ 2892817Sksewell@umich.edutemplate <class Impl> 2903468Sgblack@eecs.umich.eduvoid 2918518Sgeoffrey.blake@arm.comO3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val) 2922817Sksewell@umich.edu{ 2935715Shsul@eecs.umich.edu cpu->setMiscReg(misc_reg, val, thread->threadId()); 2942817Sksewell@umich.edu 2959382SAli.Saidi@ARM.com conditionalSquash(); 2962817Sksewell@umich.edu} 2972817Sksewell@umich.edu 298