thread_context.hh revision 8733
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 44#define __CPU_O3_THREAD_CONTEXT_HH__ 45 46#include "config/the_isa.hh" 47#include "config/use_checker.hh" 48#include "cpu/o3/isa_specific.hh" 49#include "cpu/thread_context.hh" 50 51class EndQuiesceEvent; 52namespace Kernel { 53 class Statistics; 54}; 55 56/** 57 * Derived ThreadContext class for use with the O3CPU. It 58 * provides the interface for any external objects to access a 59 * single thread's state and some general CPU state. Any time 60 * external objects try to update state through this interface, 61 * the CPU will create an event to squash all in-flight 62 * instructions in order to ensure state is maintained correctly. 63 * It must be defined specifically for the O3CPU because 64 * not all architectural state is located within the O3ThreadState 65 * (such as the commit PC, and registers), and specific actions 66 * must be taken when using this interface (such as squashing all 67 * in-flight instructions when doing a write to this interface). 68 */ 69template <class Impl> 70class O3ThreadContext : public ThreadContext 71{ 72 public: 73 typedef typename Impl::O3CPU O3CPU; 74 75 /** Pointer to the CPU. */ 76 O3CPU *cpu; 77 78 /** Pointer to the thread state that this TC corrseponds to. */ 79 O3ThreadState<Impl> *thread; 80 81 /** Returns a pointer to the ITB. */ 82 TheISA::TLB *getITBPtr() { return cpu->itb; } 83 84 /** Returns a pointer to the DTB. */ 85 TheISA::TLB *getDTBPtr() { return cpu->dtb; } 86 87#if USE_CHECKER 88 BaseCPU *getCheckerCpuPtr() { return NULL; } 89#endif 90 91 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } 92 93 /** Returns a pointer to this CPU. */ 94 virtual BaseCPU *getCpuPtr() { return cpu; } 95 96 /** Reads this CPU's ID. */ 97 virtual int cpuId() { return cpu->cpuId(); } 98 99 virtual int contextId() { return thread->contextId(); } 100 101 virtual void setContextId(int id) { thread->setContextId(id); } 102 103 /** Returns this thread's ID number. */ 104 virtual int threadId() { return thread->threadId(); } 105 virtual void setThreadId(int id) { return thread->setThreadId(id); } 106 107 /** Returns a pointer to the system. */ 108 virtual System *getSystemPtr() { return cpu->system; } 109 110#if FULL_SYSTEM 111 /** Returns a pointer to this thread's kernel statistics. */ 112 virtual TheISA::Kernel::Statistics *getKernelStats() 113 { return thread->kernelStats; } 114 115 virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); } 116 117 virtual FSTranslatingPortProxy* getVirtProxy(); 118 119 virtual void initMemProxies(ThreadContext *tc) 120 { thread->initMemProxies(tc); } 121#else 122 virtual SETranslatingPortProxy* getMemProxy() 123 { return thread->getMemProxy(); } 124 125 /** Returns a pointer to this thread's process. */ 126 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 127#endif 128 /** Returns this thread's status. */ 129 virtual Status status() const { return thread->status(); } 130 131 /** Sets this thread's status. */ 132 virtual void setStatus(Status new_status) 133 { thread->setStatus(new_status); } 134 135 /** Set the status to Active. Optional delay indicates number of 136 * cycles to wait before beginning execution. */ 137 virtual void activate(int delay = 1); 138 139 /** Set the status to Suspended. */ 140 virtual void suspend(int delay = 0); 141 142 /** Set the status to Halted. */ 143 virtual void halt(int delay = 0); 144 145#if FULL_SYSTEM 146 /** Dumps the function profiling information. 147 * @todo: Implement. 148 */ 149 virtual void dumpFuncProfile(); 150#endif 151 /** Takes over execution of a thread from another CPU. */ 152 virtual void takeOverFrom(ThreadContext *old_context); 153 154 /** Registers statistics associated with this TC. */ 155 virtual void regStats(const std::string &name); 156 157 /** Serializes state. */ 158 virtual void serialize(std::ostream &os); 159 /** Unserializes state. */ 160 virtual void unserialize(Checkpoint *cp, const std::string §ion); 161 162#if FULL_SYSTEM 163 /** Reads the last tick that this thread was activated on. */ 164 virtual Tick readLastActivate(); 165 /** Reads the last tick that this thread was suspended on. */ 166 virtual Tick readLastSuspend(); 167 168 /** Clears the function profiling information. */ 169 virtual void profileClear(); 170 /** Samples the function profiling information. */ 171 virtual void profileSample(); 172#endif 173 174 /** Copies the architectural registers from another TC into this TC. */ 175 virtual void copyArchRegs(ThreadContext *tc); 176 177 /** Resets all architectural registers to 0. */ 178 virtual void clearArchRegs(); 179 180 /** Reads an integer register. */ 181 virtual uint64_t readIntReg(int reg_idx); 182 183 virtual FloatReg readFloatReg(int reg_idx); 184 185 virtual FloatRegBits readFloatRegBits(int reg_idx); 186 187 /** Sets an integer register to a value. */ 188 virtual void setIntReg(int reg_idx, uint64_t val); 189 190 virtual void setFloatReg(int reg_idx, FloatReg val); 191 192 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 193 194 /** Reads this thread's PC state. */ 195 virtual TheISA::PCState pcState() 196 { return cpu->pcState(thread->threadId()); } 197 198 /** Sets this thread's PC state. */ 199 virtual void pcState(const TheISA::PCState &val); 200 201#if USE_CHECKER 202 virtual void pcStateNoRecord(const TheISA::PCState &val); 203#endif 204 205 /** Reads this thread's PC. */ 206 virtual Addr instAddr() 207 { return cpu->instAddr(thread->threadId()); } 208 209 /** Reads this thread's next PC. */ 210 virtual Addr nextInstAddr() 211 { return cpu->nextInstAddr(thread->threadId()); } 212 213 /** Reads this thread's next PC. */ 214 virtual MicroPC microPC() 215 { return cpu->microPC(thread->threadId()); } 216 217 /** Reads a miscellaneous register. */ 218 virtual MiscReg readMiscRegNoEffect(int misc_reg) 219 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 220 221 /** Reads a misc. register, including any side-effects the 222 * read might have as defined by the architecture. */ 223 virtual MiscReg readMiscReg(int misc_reg) 224 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 225 226 /** Sets a misc. register. */ 227 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 228 229 /** Sets a misc. register, including any side-effects the 230 * write might have as defined by the architecture. */ 231 virtual void setMiscReg(int misc_reg, const MiscReg &val); 232 233 virtual int flattenIntIndex(int reg); 234 virtual int flattenFloatIndex(int reg); 235 236 /** Returns the number of consecutive store conditional failures. */ 237 // @todo: Figure out where these store cond failures should go. 238 virtual unsigned readStCondFailures() 239 { return thread->storeCondFailures; } 240 241 /** Sets the number of consecutive store conditional failures. */ 242 virtual void setStCondFailures(unsigned sc_failures) 243 { thread->storeCondFailures = sc_failures; } 244 245 // Only really makes sense for old CPU model. Lots of code 246 // outside the CPU still checks this function, so it will 247 // always return false to keep everything working. 248 /** Checks if the thread is misspeculating. Because it is 249 * very difficult to determine if the thread is 250 * misspeculating, this is set as false. */ 251 virtual bool misspeculating() { return false; } 252 253#if !FULL_SYSTEM 254 /** Executes a syscall in SE mode. */ 255 virtual void syscall(int64_t callnum) 256 { return cpu->syscall(callnum, thread->threadId()); } 257 258 /** Reads the funcExeInst counter. */ 259 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 260#else 261 /** Returns pointer to the quiesce event. */ 262 virtual EndQuiesceEvent *getQuiesceEvent() 263 { 264 return this->thread->quiesceEvent; 265 } 266#endif 267 268}; 269 270#endif 271