thread_context.hh revision 6658
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 32#define __CPU_O3_THREAD_CONTEXT_HH__ 33 34#include "config/the_isa.hh" 35#include "cpu/thread_context.hh" 36#include "cpu/o3/isa_specific.hh" 37 38class EndQuiesceEvent; 39namespace Kernel { 40 class Statistics; 41}; 42 43class TranslatingPort; 44 45/** 46 * Derived ThreadContext class for use with the O3CPU. It 47 * provides the interface for any external objects to access a 48 * single thread's state and some general CPU state. Any time 49 * external objects try to update state through this interface, 50 * the CPU will create an event to squash all in-flight 51 * instructions in order to ensure state is maintained correctly. 52 * It must be defined specifically for the O3CPU because 53 * not all architectural state is located within the O3ThreadState 54 * (such as the commit PC, and registers), and specific actions 55 * must be taken when using this interface (such as squashing all 56 * in-flight instructions when doing a write to this interface). 57 */ 58template <class Impl> 59class O3ThreadContext : public ThreadContext 60{ 61 public: 62 typedef typename Impl::O3CPU O3CPU; 63 64 /** Pointer to the CPU. */ 65 O3CPU *cpu; 66 67 /** Pointer to the thread state that this TC corrseponds to. */ 68 O3ThreadState<Impl> *thread; 69 70 /** Returns a pointer to the ITB. */ 71 TheISA::TLB *getITBPtr() { return cpu->itb; } 72 73 /** Returns a pointer to the DTB. */ 74 TheISA::TLB *getDTBPtr() { return cpu->dtb; } 75 76 /** Returns a pointer to this CPU. */ 77 virtual BaseCPU *getCpuPtr() { return cpu; } 78 79 /** Reads this CPU's ID. */ 80 virtual int cpuId() { return cpu->cpuId(); } 81 82 virtual int contextId() { return thread->contextId(); } 83 84 virtual void setContextId(int id) { thread->setContextId(id); } 85 86 /** Returns this thread's ID number. */ 87 virtual int threadId() { return thread->threadId(); } 88 virtual void setThreadId(int id) { return thread->setThreadId(id); } 89 90 /** Returns a pointer to the system. */ 91 virtual System *getSystemPtr() { return cpu->system; } 92 93#if FULL_SYSTEM 94 /** Returns a pointer to physical memory. */ 95 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 96 97 /** Returns a pointer to this thread's kernel statistics. */ 98 virtual TheISA::Kernel::Statistics *getKernelStats() 99 { return thread->kernelStats; } 100 101 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 102 103 virtual VirtualPort *getVirtPort(); 104 105 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); } 106#else 107 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 108 109 /** Returns a pointer to this thread's process. */ 110 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 111#endif 112 /** Returns this thread's status. */ 113 virtual Status status() const { return thread->status(); } 114 115 /** Sets this thread's status. */ 116 virtual void setStatus(Status new_status) 117 { thread->setStatus(new_status); } 118 119 /** Set the status to Active. Optional delay indicates number of 120 * cycles to wait before beginning execution. */ 121 virtual void activate(int delay = 1); 122 123 /** Set the status to Suspended. */ 124 virtual void suspend(int delay = 0); 125 126 /** Set the status to Halted. */ 127 virtual void halt(int delay = 0); 128 129#if FULL_SYSTEM 130 /** Dumps the function profiling information. 131 * @todo: Implement. 132 */ 133 virtual void dumpFuncProfile(); 134#endif 135 /** Takes over execution of a thread from another CPU. */ 136 virtual void takeOverFrom(ThreadContext *old_context); 137 138 /** Registers statistics associated with this TC. */ 139 virtual void regStats(const std::string &name); 140 141 /** Serializes state. */ 142 virtual void serialize(std::ostream &os); 143 /** Unserializes state. */ 144 virtual void unserialize(Checkpoint *cp, const std::string §ion); 145 146#if FULL_SYSTEM 147 /** Reads the last tick that this thread was activated on. */ 148 virtual Tick readLastActivate(); 149 /** Reads the last tick that this thread was suspended on. */ 150 virtual Tick readLastSuspend(); 151 152 /** Clears the function profiling information. */ 153 virtual void profileClear(); 154 /** Samples the function profiling information. */ 155 virtual void profileSample(); 156#endif 157 /** Returns the instruction this thread is currently committing. 158 * Only used when an instruction faults. 159 */ 160 virtual TheISA::MachInst getInst(); 161 162 /** Copies the architectural registers from another TC into this TC. */ 163 virtual void copyArchRegs(ThreadContext *tc); 164 165 /** Resets all architectural registers to 0. */ 166 virtual void clearArchRegs(); 167 168 /** Reads an integer register. */ 169 virtual uint64_t readIntReg(int reg_idx); 170 171 virtual FloatReg readFloatReg(int reg_idx); 172 173 virtual FloatRegBits readFloatRegBits(int reg_idx); 174 175 /** Sets an integer register to a value. */ 176 virtual void setIntReg(int reg_idx, uint64_t val); 177 178 virtual void setFloatReg(int reg_idx, FloatReg val); 179 180 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 181 182 /** Reads this thread's PC. */ 183 virtual uint64_t readPC() 184 { return cpu->readPC(thread->threadId()); } 185 186 /** Sets this thread's PC. */ 187 virtual void setPC(uint64_t val); 188 189 /** Reads this thread's next PC. */ 190 virtual uint64_t readNextPC() 191 { return cpu->readNextPC(thread->threadId()); } 192 193 /** Sets this thread's next PC. */ 194 virtual void setNextPC(uint64_t val); 195 196 virtual uint64_t readMicroPC() 197 { return cpu->readMicroPC(thread->threadId()); } 198 199 virtual void setMicroPC(uint64_t val); 200 201 virtual uint64_t readNextMicroPC() 202 { return cpu->readNextMicroPC(thread->threadId()); } 203 204 virtual void setNextMicroPC(uint64_t val); 205 206 /** Reads a miscellaneous register. */ 207 virtual MiscReg readMiscRegNoEffect(int misc_reg) 208 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 209 210 /** Reads a misc. register, including any side-effects the 211 * read might have as defined by the architecture. */ 212 virtual MiscReg readMiscReg(int misc_reg) 213 { return cpu->readMiscReg(misc_reg, thread->threadId()); } 214 215 /** Sets a misc. register. */ 216 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 217 218 /** Sets a misc. register, including any side-effects the 219 * write might have as defined by the architecture. */ 220 virtual void setMiscReg(int misc_reg, const MiscReg &val); 221 222 virtual int flattenIntIndex(int reg); 223 virtual int flattenFloatIndex(int reg); 224 225 /** Returns the number of consecutive store conditional failures. */ 226 // @todo: Figure out where these store cond failures should go. 227 virtual unsigned readStCondFailures() 228 { return thread->storeCondFailures; } 229 230 /** Sets the number of consecutive store conditional failures. */ 231 virtual void setStCondFailures(unsigned sc_failures) 232 { thread->storeCondFailures = sc_failures; } 233 234 // Only really makes sense for old CPU model. Lots of code 235 // outside the CPU still checks this function, so it will 236 // always return false to keep everything working. 237 /** Checks if the thread is misspeculating. Because it is 238 * very difficult to determine if the thread is 239 * misspeculating, this is set as false. */ 240 virtual bool misspeculating() { return false; } 241 242#if !FULL_SYSTEM 243 /** Executes a syscall in SE mode. */ 244 virtual void syscall(int64_t callnum) 245 { return cpu->syscall(callnum, thread->threadId()); } 246 247 /** Reads the funcExeInst counter. */ 248 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 249#else 250 /** Returns pointer to the quiesce event. */ 251 virtual EndQuiesceEvent *getQuiesceEvent() 252 { 253 return this->thread->quiesceEvent; 254 } 255#endif 256 257 virtual uint64_t readNextNPC() 258 { 259 return this->cpu->readNextNPC(this->thread->threadId()); 260 } 261 262 virtual void setNextNPC(uint64_t val) 263 { 264 this->cpu->setNextNPC(val, this->thread->threadId()); 265 } 266}; 267 268#endif 269